1 """core of the python-based POWER9 simulator
3 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
4 not speed, it is for both learning and educational purposes, as well as
5 a method of verifying the HDL.
9 * https://bugs.libre-soc.org/show_bug.cgi?id=424
12 from functools
import wraps
14 from soc
.decoder
.orderedset
import OrderedSet
15 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
17 from soc
.decoder
.power_enums
import (spr_dict
, spr_byname
, XER_bits
,
19 from soc
.decoder
.helpers
import exts
, gtu
, ltu
20 from soc
.consts
import PIb
, MSRb
# big-endian (PowerISA versions)
22 from collections
import namedtuple
26 instruction_info
= namedtuple('instruction_info',
27 'func read_regs uninit_regs write_regs ' +
28 'special_regs op_fields form asmregs')
38 def swap_order(x
, nbytes
):
39 x
= x
.to_bytes(nbytes
, byteorder
='little')
40 x
= int.from_bytes(x
, byteorder
='big', signed
=False)
44 def create_args(reglist
, extra
=None):
56 def __init__(self
, row_bytes
=8, initial_mem
=None):
58 self
.bytes_per_word
= row_bytes
59 self
.word_log2
= math
.ceil(math
.log2(row_bytes
))
60 print("Sim-Mem", initial_mem
, self
.bytes_per_word
, self
.word_log2
)
64 # different types of memory data structures recognised (for convenience)
65 if isinstance(initial_mem
, list):
66 initial_mem
= (0, initial_mem
)
67 if isinstance(initial_mem
, tuple):
68 startaddr
, mem
= initial_mem
70 for i
, val
in enumerate(mem
):
71 initial_mem
[startaddr
+ row_bytes
*i
] = (val
, row_bytes
)
73 for addr
, (val
, width
) in initial_mem
.items():
74 #val = swap_order(val, width)
75 self
.st(addr
, val
, width
, swap
=False)
77 def _get_shifter_mask(self
, wid
, remainder
):
78 shifter
= ((self
.bytes_per_word
- wid
) - remainder
) * \
80 # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
82 shifter
= remainder
* 8
83 mask
= (1 << (wid
* 8)) - 1
84 print("width,rem,shift,mask", wid
, remainder
, hex(shifter
), hex(mask
))
87 # TODO: Implement ld/st of lesser width
88 def ld(self
, address
, width
=8, swap
=True, check_in_mem
=False):
89 print("ld from addr 0x{:x} width {:d}".format(address
, width
))
90 remainder
= address
& (self
.bytes_per_word
- 1)
91 address
= address
>> self
.word_log2
92 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
93 if address
in self
.mem
:
94 val
= self
.mem
[address
]
99 print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address
, remainder
, val
))
101 if width
!= self
.bytes_per_word
:
102 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
103 print("masking", hex(val
), hex(mask
<< shifter
), shifter
)
104 val
= val
& (mask
<< shifter
)
107 val
= swap_order(val
, width
)
108 print("Read 0x{:x} from addr 0x{:x}".format(val
, address
))
111 def st(self
, addr
, v
, width
=8, swap
=True):
113 remainder
= addr
& (self
.bytes_per_word
- 1)
114 addr
= addr
>> self
.word_log2
115 print("Writing 0x{:x} to ST 0x{:x} "
116 "memaddr 0x{:x}/{:x}".format(v
, staddr
, addr
, remainder
, swap
))
117 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
119 v
= swap_order(v
, width
)
120 if width
!= self
.bytes_per_word
:
125 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
126 val
&= ~
(mask
<< shifter
)
131 print("mem @ 0x{:x}: 0x{:x}".format(addr
, self
.mem
[addr
]))
133 def __call__(self
, addr
, sz
):
134 val
= self
.ld(addr
.value
, sz
, swap
=False)
135 print("memread", addr
, sz
, val
)
136 return SelectableInt(val
, sz
*8)
138 def memassign(self
, addr
, sz
, val
):
139 print("memassign", addr
, sz
, val
)
140 self
.st(addr
.value
, val
.value
, sz
, swap
=False)
144 def __init__(self
, decoder
, regfile
):
148 self
[i
] = SelectableInt(regfile
[i
], 64)
150 def __call__(self
, ridx
):
153 def set_form(self
, form
):
156 def getz(self
, rnum
):
157 # rnum = rnum.value # only SelectableInt allowed
158 print("GPR getzero", rnum
)
160 return SelectableInt(0, 64)
163 def _get_regnum(self
, attr
):
164 getform
= self
.sd
.sigforms
[self
.form
]
165 rnum
= getattr(getform
, attr
)
168 def ___getitem__(self
, attr
):
169 print("GPR getitem", attr
)
170 rnum
= self
._get
_regnum
(attr
)
171 return self
.regfile
[rnum
]
174 for i
in range(0, len(self
), 8):
177 s
.append("%08x" % self
[i
+j
].value
)
179 print("reg", "%2d" % i
, s
)
183 def __init__(self
, pc_init
=0):
184 self
.CIA
= SelectableInt(pc_init
, 64)
185 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
187 def update(self
, namespace
):
188 self
.CIA
= namespace
['NIA'].narrow(64)
189 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
190 namespace
['CIA'] = self
.CIA
191 namespace
['NIA'] = self
.NIA
195 def __init__(self
, dec2
, initial_sprs
={}):
198 for key
, v
in initial_sprs
.items():
199 if isinstance(key
, SelectableInt
):
201 key
= special_sprs
.get(key
, key
)
202 if isinstance(key
, int):
205 info
= spr_byname
[key
]
206 if not isinstance(v
, SelectableInt
):
207 v
= SelectableInt(v
, info
.length
)
210 def __getitem__(self
, key
):
211 print("get spr", key
)
212 print("dict", self
.items())
213 # if key in special_sprs get the special spr, otherwise return key
214 if isinstance(key
, SelectableInt
):
216 if isinstance(key
, int):
217 key
= spr_dict
[key
].SPR
218 key
= special_sprs
.get(key
, key
)
219 if key
== 'HSRR0': # HACK!
221 if key
== 'HSRR1': # HACK!
224 res
= dict.__getitem
__(self
, key
)
226 if isinstance(key
, int):
229 info
= spr_byname
[key
]
230 dict.__setitem
__(self
, key
, SelectableInt(0, info
.length
))
231 res
= dict.__getitem
__(self
, key
)
232 print("spr returning", key
, res
)
235 def __setitem__(self
, key
, value
):
236 if isinstance(key
, SelectableInt
):
238 if isinstance(key
, int):
239 key
= spr_dict
[key
].SPR
240 print("spr key", key
)
241 key
= special_sprs
.get(key
, key
)
242 if key
== 'HSRR0': # HACK!
243 self
.__setitem
__('SRR0', value
)
244 if key
== 'HSRR1': # HACK!
245 self
.__setitem
__('SRR1', value
)
246 print("setting spr", key
, value
)
247 dict.__setitem
__(self
, key
, value
)
249 def __call__(self
, ridx
):
254 # decoder2 - an instance of power_decoder2
255 # regfile - a list of initial values for the registers
256 # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
257 # respect_pc - tracks the program counter. requires initial_insns
258 def __init__(self
, decoder2
, regfile
, initial_sprs
=None, initial_cr
=0,
259 initial_mem
=None, initial_msr
=0,
260 initial_insns
=None, respect_pc
=False,
265 self
.bigendian
= bigendian
267 self
.respect_pc
= respect_pc
268 if initial_sprs
is None:
270 if initial_mem
is None:
272 if initial_insns
is None:
274 assert self
.respect_pc
== False, "instructions required to honor pc"
276 print("ISACaller insns", respect_pc
, initial_insns
, disassembly
)
277 print("ISACaller initial_msr", initial_msr
)
279 # "fake program counter" mode (for unit testing)
283 if isinstance(initial_mem
, tuple):
284 self
.fake_pc
= initial_mem
[0]
285 disasm_start
= self
.fake_pc
287 disasm_start
= initial_pc
289 # disassembly: we need this for now (not given from the decoder)
290 self
.disassembly
= {}
292 for i
, code
in enumerate(disassembly
):
293 self
.disassembly
[i
*4 + disasm_start
] = code
295 # set up registers, instruction memory, data memory, PC, SPRs, MSR
296 self
.gpr
= GPR(decoder2
, regfile
)
297 self
.mem
= Mem(row_bytes
=8, initial_mem
=initial_mem
)
298 self
.imem
= Mem(row_bytes
=4, initial_mem
=initial_insns
)
300 self
.spr
= SPR(decoder2
, initial_sprs
)
301 self
.msr
= SelectableInt(initial_msr
, 64) # underlying reg
304 # FPR (same as GPR except for FP nums)
305 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
306 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
307 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
308 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
310 # 2.3.2 LR (actually SPR #8) -- Done
311 # 2.3.3 CTR (actually SPR #9) -- Done
312 # 2.3.4 TAR (actually SPR #815)
313 # 3.2.2 p45 XER (actually SPR #1) -- Done
314 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
316 # create CR then allow portions of it to be "selectable" (below)
317 self
._cr
= SelectableInt(initial_cr
, 64) # underlying reg
318 self
.cr
= FieldSelectableInt(self
._cr
, list(range(32, 64)))
320 # "undefined", just set to variable-bit-width int (use exts "max")
321 self
.undefined
= SelectableInt(0, 256) # TODO, not hard-code 256!
324 self
.namespace
.update(self
.spr
)
325 self
.namespace
.update({'GPR': self
.gpr
,
328 'memassign': self
.memassign
,
333 'undefined': self
.undefined
,
334 'mode_is_64bit': True,
338 # update pc to requested start point
339 self
.set_pc(initial_pc
)
341 # field-selectable versions of Condition Register TODO check bitranges?
344 bits
= tuple(range(i
*4, (i
+1)*4)) # errr... maybe?
345 _cr
= FieldSelectableInt(self
.cr
, bits
)
347 self
.namespace
["CR%d" % i
] = _cr
349 self
.decoder
= decoder2
.dec
352 def TRAP(self
, trap_addr
=0x700, trap_bit
=PIb
.TRAP
):
353 print("TRAP:", hex(trap_addr
), hex(self
.namespace
['MSR'].value
))
354 # store CIA(+4?) in SRR0, set NIA to 0x700
355 # store MSR in SRR1, set MSR to um errr something, have to check spec
356 self
.spr
['SRR0'].value
= self
.pc
.CIA
.value
357 self
.spr
['SRR1'].value
= self
.namespace
['MSR'].value
358 self
.trap_nia
= SelectableInt(trap_addr
, 64)
359 self
.spr
['SRR1'][trap_bit
] = 1 # change *copy* of MSR in SRR1
361 # set exception bits. TODO: this should, based on the address
362 # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
363 # bits appropriately. however it turns out that *for now* in all
364 # cases (all trap_addrs) the exact same thing is needed.
365 self
.msr
[MSRb
.IR
] = 0
366 self
.msr
[MSRb
.DR
] = 0
367 self
.msr
[MSRb
.FE0
] = 0
368 self
.msr
[MSRb
.FE1
] = 0
369 self
.msr
[MSRb
.EE
] = 0
370 self
.msr
[MSRb
.RI
] = 0
371 self
.msr
[MSRb
.SF
] = 1
372 self
.msr
[MSRb
.TM
] = 0
373 self
.msr
[MSRb
.VEC
] = 0
374 self
.msr
[MSRb
.VSX
] = 0
375 self
.msr
[MSRb
.PR
] = 0
376 self
.msr
[MSRb
.FP
] = 0
377 self
.msr
[MSRb
.PMM
] = 0
378 self
.msr
[MSRb
.TEs
] = 0
379 self
.msr
[MSRb
.TEe
] = 0
380 self
.msr
[MSRb
.UND
] = 0
381 self
.msr
[MSRb
.LE
] = 1
383 def memassign(self
, ea
, sz
, val
):
384 self
.mem
.memassign(ea
, sz
, val
)
386 def prep_namespace(self
, formname
, op_fields
):
387 # TODO: get field names from form in decoder*1* (not decoder2)
388 # decoder2 is hand-created, and decoder1.sigform is auto-generated
390 # then "yield" fields only from op_fields rather than hard-coded
392 fields
= self
.decoder
.sigforms
[formname
]
393 for name
in op_fields
:
395 sig
= getattr(fields
, name
.upper())
397 sig
= getattr(fields
, name
)
399 if name
in ['BF', 'BFA']:
400 self
.namespace
[name
] = val
402 self
.namespace
[name
] = SelectableInt(val
, sig
.width
)
404 self
.namespace
['XER'] = self
.spr
['XER']
405 self
.namespace
['CA'] = self
.spr
['XER'][XER_bits
['CA']].value
406 self
.namespace
['CA32'] = self
.spr
['XER'][XER_bits
['CA32']].value
408 def handle_carry_(self
, inputs
, outputs
, already_done
):
409 inv_a
= yield self
.dec2
.e
.do
.invert_in
411 inputs
[0] = ~inputs
[0]
413 imm_ok
= yield self
.dec2
.e
.do
.imm_data
.ok
415 imm
= yield self
.dec2
.e
.do
.imm_data
.data
416 inputs
.append(SelectableInt(imm
, 64))
417 assert len(outputs
) >= 1
418 print("outputs", repr(outputs
))
419 if isinstance(outputs
, list) or isinstance(outputs
, tuple):
425 print("gt input", x
, output
)
426 gt
= (gtu(x
, output
))
429 cy
= 1 if any(gts
) else 0
430 print ("CA", cy
, gts
)
431 if not (1 & already_done
):
432 self
.spr
['XER'][XER_bits
['CA']] = cy
434 print("inputs", already_done
, inputs
)
436 # ARGH... different for OP_ADD... *sigh*...
437 op
= yield self
.dec2
.e
.do
.insn_type
438 if op
== MicrOp
.OP_ADD
.value
:
439 res32
= (output
.value
& (1<<32)) != 0
440 a32
= (inputs
[0].value
& (1<<32)) != 0
442 b32
= (inputs
[1].value
& (1<<32)) != 0
445 cy32
= res32 ^ a32 ^ b32
446 print ("CA32 ADD", cy32
)
450 print("input", x
, output
)
451 print(" x[32:64]", x
, x
[32:64])
452 print(" o[32:64]", output
, output
[32:64])
453 gt
= (gtu(x
[32:64], output
[32:64])) == SelectableInt(1, 1)
455 cy32
= 1 if any(gts
) else 0
456 print ("CA32", cy32
, gts
)
457 if not (2 & already_done
):
458 self
.spr
['XER'][XER_bits
['CA32']] = cy32
460 def handle_overflow(self
, inputs
, outputs
, div_overflow
):
461 inv_a
= yield self
.dec2
.e
.do
.invert_in
463 inputs
[0] = ~inputs
[0]
465 imm_ok
= yield self
.dec2
.e
.do
.imm_data
.ok
467 imm
= yield self
.dec2
.e
.do
.imm_data
.data
468 inputs
.append(SelectableInt(imm
, 64))
469 assert len(outputs
) >= 1
470 print("handle_overflow", inputs
, outputs
, div_overflow
)
471 if len(inputs
) < 2 and div_overflow
is None:
474 # div overflow is different: it's returned by the pseudo-code
475 # because it's more complex than can be done by analysing the output
476 if div_overflow
is not None:
477 ov
, ov32
= div_overflow
, div_overflow
478 # arithmetic overflow can be done by analysing the input and output
479 elif len(inputs
) >= 2:
483 input_sgn
= [exts(x
.value
, x
.bits
) < 0 for x
in inputs
]
484 output_sgn
= exts(output
.value
, output
.bits
) < 0
485 ov
= 1 if input_sgn
[0] == input_sgn
[1] and \
486 output_sgn
!= input_sgn
[0] else 0
489 input32_sgn
= [exts(x
.value
, 32) < 0 for x
in inputs
]
490 output32_sgn
= exts(output
.value
, 32) < 0
491 ov32
= 1 if input32_sgn
[0] == input32_sgn
[1] and \
492 output32_sgn
!= input32_sgn
[0] else 0
494 self
.spr
['XER'][XER_bits
['OV']] = ov
495 self
.spr
['XER'][XER_bits
['OV32']] = ov32
496 so
= self
.spr
['XER'][XER_bits
['SO']]
498 self
.spr
['XER'][XER_bits
['SO']] = so
500 def handle_comparison(self
, outputs
):
502 assert isinstance(out
, SelectableInt
), \
503 "out zero not a SelectableInt %s" % repr(outputs
)
504 print("handle_comparison", out
.bits
, hex(out
.value
))
505 # TODO - XXX *processor* in 32-bit mode
506 # https://bugs.libre-soc.org/show_bug.cgi?id=424
508 # o32 = exts(out.value, 32)
509 # print ("handle_comparison exts 32 bit", hex(o32))
510 out
= exts(out
.value
, out
.bits
)
511 print("handle_comparison exts", hex(out
))
512 zero
= SelectableInt(out
== 0, 1)
513 positive
= SelectableInt(out
> 0, 1)
514 negative
= SelectableInt(out
< 0, 1)
515 SO
= self
.spr
['XER'][XER_bits
['SO']]
516 print("handle_comparison SO", SO
)
517 cr_field
= selectconcat(negative
, positive
, zero
, SO
)
518 self
.crl
[0].eq(cr_field
)
520 def set_pc(self
, pc_val
):
521 self
.namespace
['NIA'] = SelectableInt(pc_val
, 64)
522 self
.pc
.update(self
.namespace
)
525 """set up one instruction
528 pc
= self
.pc
.CIA
.value
532 ins
= self
.imem
.ld(pc
, 4, False, True)
534 raise KeyError("no instruction at 0x%x" % pc
)
535 print("setup: 0x%x 0x%x %s" % (pc
, ins
& 0xffffffff, bin(ins
)))
536 print("CIA NIA", self
.respect_pc
, self
.pc
.CIA
.value
, self
.pc
.NIA
.value
)
538 yield self
.dec2
.dec
.raw_opcode_in
.eq(ins
& 0xffffffff)
539 yield self
.dec2
.dec
.bigendian
.eq(self
.bigendian
)
540 yield self
.dec2
.state
.msr
.eq(self
.msr
.value
)
541 yield self
.dec2
.state
.pc
.eq(pc
)
543 def execute_one(self
):
544 """execute one instruction
546 # get the disassembly code for this instruction
547 code
= self
.disassembly
[self
._pc
]
548 print("sim-execute", hex(self
._pc
), code
)
549 opname
= code
.split(' ')[0]
550 yield from self
.call(opname
)
552 if not self
.respect_pc
:
554 print("execute one, CIA NIA", self
.pc
.CIA
.value
, self
.pc
.NIA
.value
)
556 def get_assembly_name(self
):
557 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
558 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
559 dec_insn
= yield self
.dec2
.e
.do
.insn
560 asmcode
= yield self
.dec2
.dec
.op
.asmcode
561 print("get assembly name asmcode", asmcode
, hex(dec_insn
))
562 asmop
= insns
.get(asmcode
, None)
563 int_op
= yield self
.dec2
.dec
.op
.internal_op
565 # sigh reconstruct the assembly instruction name
566 ov_en
= yield self
.dec2
.e
.do
.oe
.oe
567 ov_ok
= yield self
.dec2
.e
.do
.oe
.ok
568 rc_en
= yield self
.dec2
.e
.do
.rc
.data
569 rc_ok
= yield self
.dec2
.e
.do
.rc
.ok
570 # grrrr have to special-case MUL op (see DecodeOE)
571 print("ov %d en %d rc %d en %d op %d" % \
572 (ov_ok
, ov_en
, rc_ok
, rc_en
, int_op
))
573 if int_op
in [MicrOp
.OP_MUL_H64
.value
, MicrOp
.OP_MUL_H32
.value
]:
578 if not asmop
.endswith("."): # don't add "." to "andis."
581 lk
= yield self
.dec2
.e
.do
.lk
584 print("int_op", int_op
)
585 if int_op
in [MicrOp
.OP_B
.value
, MicrOp
.OP_BC
.value
]:
586 AA
= yield self
.dec2
.dec
.fields
.FormI
.AA
[0:-1]
590 spr_msb
= yield from self
.get_spr_msb()
591 if int_op
== MicrOp
.OP_MFCR
.value
:
596 # XXX TODO: for whatever weird reason this doesn't work
597 # https://bugs.libre-soc.org/show_bug.cgi?id=390
598 if int_op
== MicrOp
.OP_MTCRF
.value
:
605 def get_spr_msb(self
):
606 dec_insn
= yield self
.dec2
.e
.do
.insn
607 return dec_insn
& (1 << 20) != 0 # sigh - XFF.spr[-1]?
609 def call(self
, name
):
610 name
= name
.strip() # remove spaces if not already done so
612 print("halted - not executing", name
)
615 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
616 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
617 asmop
= yield from self
.get_assembly_name()
618 print("call", name
, asmop
)
621 int_op
= yield self
.dec2
.dec
.op
.internal_op
622 spr_msb
= yield from self
.get_spr_msb()
624 instr_is_privileged
= False
625 if int_op
in [MicrOp
.OP_ATTN
.value
,
626 MicrOp
.OP_MFMSR
.value
,
627 MicrOp
.OP_MTMSR
.value
,
628 MicrOp
.OP_MTMSRD
.value
,
630 MicrOp
.OP_RFID
.value
]:
631 instr_is_privileged
= True
632 if int_op
in [MicrOp
.OP_MFSPR
.value
,
633 MicrOp
.OP_MTSPR
.value
] and spr_msb
:
634 instr_is_privileged
= True
636 print("is priv", instr_is_privileged
, hex(self
.msr
.value
),
638 # check MSR priv bit and whether op is privileged: if so, throw trap
639 if instr_is_privileged
and self
.msr
[MSRb
.PR
] == 1:
640 self
.TRAP(0x700, PIb
.PRIV
)
641 self
.namespace
['NIA'] = self
.trap_nia
642 self
.pc
.update(self
.namespace
)
645 # check halted condition
650 # check illegal instruction
652 if name
not in ['mtcrf', 'mtocrf']:
653 illegal
= name
!= asmop
656 print ("illegal", name
, asmop
)
657 self
.TRAP(0x700, PIb
.ILLEG
)
658 self
.namespace
['NIA'] = self
.trap_nia
659 self
.pc
.update(self
.namespace
)
660 print("name %s != %s - calling ILLEGAL trap, PC: %x" %
661 (name
, asmop
, self
.pc
.CIA
.value
))
664 info
= self
.instrs
[name
]
665 yield from self
.prep_namespace(info
.form
, info
.op_fields
)
667 # preserve order of register names
668 input_names
= create_args(list(info
.read_regs
) +
669 list(info
.uninit_regs
))
672 # main registers (RT, RA ...)
674 for name
in input_names
:
675 regnum
= yield getattr(self
.decoder
, name
)
677 self
.namespace
[regname
] = regnum
678 print('reading reg %d' % regnum
)
679 inputs
.append(self
.gpr(regnum
))
681 # "special" registers
682 for special
in info
.special_regs
:
683 if special
in special_sprs
:
684 inputs
.append(self
.spr
[special
])
686 inputs
.append(self
.namespace
[special
])
688 # clear trap (trap) NIA
692 results
= info
.func(self
, *inputs
)
695 # "inject" decorator takes namespace from function locals: we need to
696 # overwrite NIA being overwritten (sigh)
697 if self
.trap_nia
is not None:
698 self
.namespace
['NIA'] = self
.trap_nia
700 print("after func", self
.namespace
['CIA'], self
.namespace
['NIA'])
702 # detect if CA/CA32 already in outputs (sra*, basically)
705 output_names
= create_args(info
.write_regs
)
706 for name
in output_names
:
712 print("carry already done?", bin(already_done
))
713 carry_en
= yield self
.dec2
.e
.do
.output_carry
715 yield from self
.handle_carry_(inputs
, results
, already_done
)
717 # detect if overflow was in return result
720 for name
, output
in zip(output_names
, results
):
721 if name
== 'overflow':
724 ov_en
= yield self
.dec2
.e
.do
.oe
.oe
725 ov_ok
= yield self
.dec2
.e
.do
.oe
.ok
726 print("internal overflow", overflow
, ov_en
, ov_ok
)
728 yield from self
.handle_overflow(inputs
, results
, overflow
)
730 rc_en
= yield self
.dec2
.e
.do
.rc
.data
732 self
.handle_comparison(results
)
734 # any modified return results?
736 for name
, output
in zip(output_names
, results
):
737 if name
== 'overflow': # ignore, done already (above)
739 if isinstance(output
, int):
740 output
= SelectableInt(output
, 256)
741 if name
in ['CA', 'CA32']:
743 print("writing %s to XER" % name
, output
)
744 self
.spr
['XER'][XER_bits
[name
]] = output
.value
746 print("NOT writing %s to XER" % name
, output
)
747 elif name
in info
.special_regs
:
748 print('writing special %s' % name
, output
, special_sprs
)
749 if name
in special_sprs
:
750 self
.spr
[name
] = output
752 self
.namespace
[name
].eq(output
)
754 print('msr written', hex(self
.msr
.value
))
756 regnum
= yield getattr(self
.decoder
, name
)
757 print('writing reg %d %s' % (regnum
, str(output
)))
759 output
= SelectableInt(output
.value
, 64)
760 self
.gpr
[regnum
] = output
762 print("end of call", self
.namespace
['CIA'], self
.namespace
['NIA'])
763 # UPDATE program counter
764 self
.pc
.update(self
.namespace
)
768 """Decorator factory.
770 this decorator will "inject" variables into the function's namespace,
771 from the *dictionary* in self.namespace. it therefore becomes possible
772 to make it look like a whole stack of variables which would otherwise
773 need "self." inserted in front of them (*and* for those variables to be
774 added to the instance) "appear" in the function.
776 "self.namespace['SI']" for example becomes accessible as just "SI" but
777 *only* inside the function, when decorated.
779 def variable_injector(func
):
781 def decorator(*args
, **kwargs
):
783 func_globals
= func
.__globals
__ # Python 2.6+
784 except AttributeError:
785 func_globals
= func
.func_globals
# Earlier versions.
787 context
= args
[0].namespace
# variables to be injected
788 saved_values
= func_globals
.copy() # Shallow copy of dict.
789 func_globals
.update(context
)
790 result
= func(*args
, **kwargs
)
791 print("globals after", func_globals
['CIA'], func_globals
['NIA'])
792 print("args[0]", args
[0].namespace
['CIA'],
793 args
[0].namespace
['NIA'])
794 args
[0].namespace
= func_globals
795 #exec (func.__code__, func_globals)
798 # func_globals = saved_values # Undo changes.
804 return variable_injector