1 from functools
import wraps
2 from soc
.decoder
.orderedset
import OrderedSet
3 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
5 from collections
import namedtuple
8 instruction_info
= namedtuple('instruction_info',
9 'func read_regs uninit_regs write_regs ' + \
10 'special_regs op_fields form asmregs')
13 def create_args(reglist
, extra
=None):
25 def __init__(self
, bytes_per_word
=8):
27 self
.bytes_per_word
= bytes_per_word
28 self
.word_log2
= math
.ceil(math
.log2(bytes_per_word
))
30 def _get_shifter_mask(self
, width
, remainder
):
31 shifter
= ((self
.bytes_per_word
- width
) - remainder
) * \
33 mask
= (1 << (width
* 8)) - 1
36 # TODO: Implement ld/st of lesser width
37 def ld(self
, address
, width
=8):
38 remainder
= address
& (self
.bytes_per_word
- 1)
39 address
= address
>> self
.word_log2
40 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
41 if address
in self
.mem
:
42 val
= self
.mem
[address
]
46 if width
!= self
.bytes_per_word
:
47 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
48 val
= val
& (mask
<< shifter
)
50 print("Read {:x} from addr {:x}".format(val
, address
))
53 def st(self
, address
, value
, width
=8):
54 remainder
= address
& (self
.bytes_per_word
- 1)
55 address
= address
>> self
.word_log2
56 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
57 print("Writing {:x} to addr {:x}".format(value
, address
))
58 if width
!= self
.bytes_per_word
:
59 if address
in self
.mem
:
60 val
= self
.mem
[address
]
63 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
64 val
&= ~
(mask
<< shifter
)
65 val |
= value
<< shifter
66 self
.mem
[address
] = val
68 self
.mem
[address
] = value
70 def __call__(self
, addr
, sz
):
71 val
= self
.ld(addr
.value
, sz
)
72 print ("memread", addr
, sz
, val
)
73 return SelectableInt(val
, sz
*8)
75 def memassign(self
, addr
, sz
, val
):
76 print ("memassign", addr
, sz
, val
)
77 self
.st(addr
.value
, val
.value
, sz
)
81 def __init__(self
, decoder
, regfile
):
85 self
[i
] = SelectableInt(regfile
[i
], 64)
87 def __call__(self
, ridx
):
90 def set_form(self
, form
):
94 #rnum = rnum.value # only SelectableInt allowed
95 print("GPR getzero", rnum
)
97 return SelectableInt(0, 64)
100 def _get_regnum(self
, attr
):
101 getform
= self
.sd
.sigforms
[self
.form
]
102 rnum
= getattr(getform
, attr
)
105 def ___getitem__(self
, attr
):
106 print("GPR getitem", attr
)
107 rnum
= self
._get
_regnum
(attr
)
108 return self
.regfile
[rnum
]
111 for i
in range(0, len(self
), 8):
114 s
.append("%08x" % self
[i
+j
].value
)
116 print("reg", "%2d" % i
, s
)
119 def __init__(self
, pc_init
=0):
120 self
.CIA
= SelectableInt(pc_init
, 64)
121 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
123 def update(self
, namespace
):
124 self
.CIA
= namespace
['NIA'].narrow(64)
125 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
126 namespace
['CIA'] = self
.CIA
127 namespace
['NIA'] = self
.NIA
131 # decoder2 - an instance of power_decoder2
132 # regfile - a list of initial values for the registers
133 def __init__(self
, decoder2
, regfile
):
134 self
.gpr
= GPR(decoder2
, regfile
)
138 # 4.4.4 III p971 SPR (same as GPR except for SPRs - best done as a dict
139 # FPR (same as GPR except for FP nums)
140 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
141 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
142 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
143 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
144 # 2.3.2 LR (actually SPR #8)
145 # 2.3.3 CTR (actually SPR #9)
146 # 2.3.4 TAR (actually SPR #815)
147 # 3.2.2 p45 XER (actually SPR #0)
148 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
150 # create CR then allow portions of it to be "selectable" (below)
151 self
._cr
= SelectableInt(0, 64) # underlying reg
152 self
.cr
= FieldSelectableInt(self
._cr
, list(range(32,64)))
154 # "undefined", just set to variable-bit-width int (use exts "max")
155 self
.undefined
= SelectableInt(0, 256) # TODO, not hard-code 256!
157 self
.namespace
= {'GPR': self
.gpr
,
159 'memassign': self
.memassign
,
163 'LR': self
.undefined
,
164 'CTR': self
.undefined
,
165 'undefined': self
.undefined
,
166 'mode_is_64bit': True,
169 # field-selectable versions of Condition Register TODO check bitranges?
172 bits
= tuple(range((7-i
)*4, (8-i
)*4))# errr... maybe?
173 _cr
= FieldSelectableInt(self
.cr
, bits
)
175 self
.namespace
["CR%d" % i
] = _cr
177 self
.decoder
= decoder2
179 def memassign(self
, ea
, sz
, val
):
180 self
.mem
.memassign(ea
, sz
, val
)
182 def prep_namespace(self
, formname
, op_fields
):
183 # TODO: get field names from form in decoder*1* (not decoder2)
184 # decoder2 is hand-created, and decoder1.sigform is auto-generated
186 # then "yield" fields only from op_fields rather than hard-coded
188 fields
= self
.decoder
.sigforms
[formname
]
189 for name
in op_fields
:
190 sig
= getattr(fields
, name
)
192 self
.namespace
[name
] = SelectableInt(val
, sig
.width
)
194 def call(self
, name
):
195 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
196 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
197 info
= self
.instrs
[name
]
198 yield from self
.prep_namespace(info
.form
, info
.op_fields
)
200 # preserve order of register names
201 input_names
= create_args(list(info
.read_regs
) + list(info
.uninit_regs
))
204 # main registers (RT, RA ...)
206 for name
in input_names
:
207 regnum
= yield getattr(self
.decoder
, name
)
209 self
.namespace
[regname
] = regnum
210 print('reading reg %d' % regnum
)
211 inputs
.append(self
.gpr(regnum
))
213 # "special" registers
214 for special
in info
.special_regs
:
215 inputs
.append(self
.namespace
[special
])
218 results
= info
.func(self
, *inputs
)
221 # any modified return results?
223 output_names
= create_args(info
.write_regs
)
224 for name
, output
in zip(output_names
, results
):
225 if name
in info
.special_regs
:
226 print('writing special %s' % name
, output
)
227 self
.namespace
[name
].eq(output
)
229 regnum
= yield getattr(self
.decoder
, name
)
230 print('writing reg %d' % regnum
)
232 output
= SelectableInt(output
.value
, 64)
233 self
.gpr
[regnum
] = output
235 # update program counter
236 self
.pc
.update(self
.namespace
)
240 """ Decorator factory. """
241 def variable_injector(func
):
243 def decorator(*args
, **kwargs
):
245 func_globals
= func
.__globals
__ # Python 2.6+
246 except AttributeError:
247 func_globals
= func
.func_globals
# Earlier versions.
249 context
= args
[0].namespace
250 saved_values
= func_globals
.copy() # Shallow copy of dict.
251 func_globals
.update(context
)
252 result
= func(*args
, **kwargs
)
253 args
[0].namespace
= func_globals
254 #exec (func.__code__, func_globals)
257 # func_globals = saved_values # Undo changes.
263 return variable_injector