src/soc/decoder/isa/caller.py

   1 from functools import wraps
   2 from soc.decoder.orderedset import OrderedSet
   3 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
   4                                         selectconcat)
   5 from collections import namedtuple
   6 import math
   7
   8 instruction_info = namedtuple('instruction_info',
   9                               'func read_regs uninit_regs write_regs op_fields form asmregs')
  10
  11
  12 def create_args(reglist, extra=None):
  13     args = OrderedSet()
  14     for reg in reglist:
  15         args.add(reg)
  16     args = list(args)
  17     if extra:
  18         args = [extra] + args
  19     return args
  20
  21
  22 class Mem:
  23
  24     def __init__(self, bytes_per_word=8):
  25         self.mem = {}
  26         self.bytes_per_word = bytes_per_word
  27         self.word_log2 = math.ceil(math.log2(bytes_per_word))
  28
  29     def _get_shifter_mask(self, width, remainder):
  30         shifter = ((self.bytes_per_word - width) - remainder) * \
  31             8  # bits per byte
  32         mask = (1 << (width * 8)) - 1
  33         return shifter, mask
  34
  35     # TODO: Implement ld/st of lesser width
  36     def ld(self, address, width=8):
  37         remainder = address & (self.bytes_per_word - 1)
  38         address = address >> self.word_log2
  39         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  40         if address in self.mem:
  41             val = self.mem[address]
  42         else:
  43             val = 0
  44
  45         if width != self.bytes_per_word:
  46             shifter, mask = self._get_shifter_mask(width, remainder)
  47             val = val & (mask << shifter)
  48             val >>= shifter
  49         print("Read {:x} from addr {:x}".format(val, address))
  50         return val
  51
  52     def st(self, address, value, width=8):
  53         remainder = address & (self.bytes_per_word - 1)
  54         address = address >> self.word_log2
  55         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  56         print("Writing {:x} to addr {:x}".format(value, address))
  57         if width != self.bytes_per_word:
  58             if address in self.mem:
  59                 val = self.mem[address]
  60             else:
  61                 val = 0
  62             shifter, mask = self._get_shifter_mask(width, remainder)
  63             val &= ~(mask << shifter)
  64             val |= value << shifter
  65             self.mem[address] = val
  66         else:
  67             self.mem[address] = value
  68
  69     def __call__(self, addr, sz):
  70         val = self.ld(addr.value, sz)
  71         print ("memread", addr, sz, val)
  72         return SelectableInt(val, sz*8)
  73
  74     def memassign(self, addr, sz, val):
  75         print ("memassign", addr, sz, val)
  76         self.st(addr.value, val.value, sz)
  77
  78
  79 class GPR(dict):
  80     def __init__(self, decoder, regfile):
  81         dict.__init__(self)
  82         self.sd = decoder
  83         for i in range(32):
  84             self[i] = SelectableInt(regfile[i], 64)
  85
  86     def __call__(self, ridx):
  87         return self[ridx]
  88
  89     def set_form(self, form):
  90         self.form = form
  91
  92     def getz(self, rnum):
  93         #rnum = rnum.value # only SelectableInt allowed
  94         print("GPR getzero", rnum)
  95         if rnum == 0:
  96             return SelectableInt(0, 64)
  97         return self[rnum]
  98
  99     def _get_regnum(self, attr):
 100         getform = self.sd.sigforms[self.form]
 101         rnum = getattr(getform, attr)
 102         return rnum
 103
 104     def ___getitem__(self, attr):
 105         print("GPR getitem", attr)
 106         rnum = self._get_regnum(attr)
 107         return self.regfile[rnum]
 108
 109     def dump(self):
 110         for i in range(0, len(self), 8):
 111             s = []
 112             for j in range(8):
 113                 s.append("%08x" % self[i+j].value)
 114             s = ' '.join(s)
 115             print("reg", "%2d" % i, s)
 116
 117 class PC:
 118     def __init__(self, pc_init=0):
 119         self.CIA = SelectableInt(pc_init, 64)
 120         self.NIA = self.CIA + SelectableInt(4, 64)
 121
 122     def update(self, namespace):
 123         self.CIA = self.NIA
 124         self.NIA = self.CIA + SelectableInt(4, 64)
 125         namespace['CIA'] = self.CIA
 126         namespace['NIA'] = self.NIA
 127
 128
 129 class ISACaller:
 130     # decoder2 - an instance of power_decoder2
 131     # regfile - a list of initial values for the registers
 132     def __init__(self, decoder2, regfile):
 133         self.gpr = GPR(decoder2, regfile)
 134         self.mem = Mem()
 135         self.pc = PC()
 136         # TODO, needed here:
 137         # 4.4.4 III p971 SPR (same as GPR except for SPRs - best done as a dict
 138         # FPR (same as GPR except for FP nums)
 139         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
 140         #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
 141         # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
 142         #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
 143         # 2.3.2 LR   (actually SPR #8)
 144         # 2.3.3 CTR  (actually SPR #9)
 145         # 2.3.4 TAR  (actually SPR #815)
 146         # 3.2.2 p45 XER  (actually SPR #0)
 147         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 148
 149         # create CR then allow portions of it to be "selectable" (below)
 150         self.cr = SelectableInt(0, 32)
 151
 152         self.namespace = {'GPR': self.gpr,
 153                           'MEM': self.mem,
 154                           'memassign': self.memassign,
 155                           'NIA': self.pc.NIA,
 156                           'CIA': self.pc.CIA,
 157                           'CR': self.cr,
 158                           }
 159
 160         # field-selectable versions of Condition Register TODO check bitranges?
 161         self.crl = []
 162         for i in range(8):
 163             bits = tuple(range(i*4, (i+1)*4))# errr... maybe?
 164             _cr = FieldSelectableInt(self.cr, bits)
 165             self.crl.append(_cr)
 166             self.namespace["CR%d" % i] = _cr
 167
 168         self.decoder = decoder2
 169
 170     def memassign(self, ea, sz, val):
 171         self.mem.memassign(ea, sz, val)
 172
 173     def prep_namespace(self, formname, op_fields):
 174         # TODO: get field names from form in decoder*1* (not decoder2)
 175         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 176         # from spec
 177         # then "yield" fields only from op_fields rather than hard-coded
 178         # list, here.
 179         fields = self.decoder.sigforms[formname]
 180         for name in fields._fields:
 181             if name not in ["RA", "RB", "RT"]:
 182                 sig = getattr(fields, name)
 183                 val = yield sig
 184                 self.namespace[name] = SelectableInt(val, sig.width)
 185
 186     def call(self, name):
 187         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 188         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 189         info = self.instrs[name]
 190         yield from self.prep_namespace(info.form, info.op_fields)
 191
 192         input_names = create_args(info.read_regs | info.uninit_regs)
 193         print(input_names)
 194
 195         inputs = []
 196         for name in input_names:
 197             regnum = yield getattr(self.decoder, name)
 198             regname = "_" + name
 199             self.namespace[regname] = regnum
 200             print('reading reg %d' % regnum)
 201             inputs.append(self.gpr(regnum))
 202         print(inputs)
 203         results = info.func(self, *inputs)
 204         print(results)
 205
 206         if info.write_regs:
 207             output_names = create_args(info.write_regs)
 208             for name, output in zip(output_names, results):
 209                 regnum = yield getattr(self.decoder, name)
 210                 print('writing reg %d' % regnum)
 211                 if output.bits > 64:
 212                     output = SelectableInt(output.value, 64)
 213                 self.gpr[regnum] = output
 214         self.pc.update(self.namespace)
 215
 216
 217 def inject():
 218     """ Decorator factory. """
 219     def variable_injector(func):
 220         @wraps(func)
 221         def decorator(*args, **kwargs):
 222             try:
 223                 func_globals = func.__globals__  # Python 2.6+
 224             except AttributeError:
 225                 func_globals = func.func_globals  # Earlier versions.
 226
 227             context = args[0].namespace
 228             saved_values = func_globals.copy()  # Shallow copy of dict.
 229             func_globals.update(context)
 230
 231             result = func(*args, **kwargs)
 232             #exec (func.__code__, func_globals)
 233
 234             #finally:
 235             #    func_globals = saved_values  # Undo changes.
 236
 237             return result
 238
 239         return decorator
 240
 241     return variable_injector
 242