Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
[soc.git] / src / soc / decoder / isa / caller.py
1 """core of the python-based POWER9 simulator
2
3 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
4 not speed, it is for both learning and educational purposes, as well as
5 a method of verifying the HDL.
6 """
7
8 from functools import wraps
9 from soc.decoder.orderedset import OrderedSet
10 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
11 selectconcat)
12 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
13 insns, InternalOp)
14 from soc.decoder.helpers import exts, trunc_div, trunc_rem
15 from soc.consts import PI, MSR
16
17 from collections import namedtuple
18 import math
19 import sys
20
21 instruction_info = namedtuple('instruction_info',
22 'func read_regs uninit_regs write_regs ' + \
23 'special_regs op_fields form asmregs')
24
25 special_sprs = {
26 'LR': 8,
27 'CTR': 9,
28 'TAR': 815,
29 'XER': 1,
30 'VRSAVE': 256}
31
32
33 def swap_order(x, nbytes):
34 x = x.to_bytes(nbytes, byteorder='little')
35 x = int.from_bytes(x, byteorder='big', signed=False)
36 return x
37
38
39 def create_args(reglist, extra=None):
40 args = OrderedSet()
41 for reg in reglist:
42 args.add(reg)
43 args = list(args)
44 if extra:
45 args = [extra] + args
46 return args
47
48
49 class Mem:
50
51 def __init__(self, row_bytes=8, initial_mem=None):
52 self.mem = {}
53 self.bytes_per_word = row_bytes
54 self.word_log2 = math.ceil(math.log2(row_bytes))
55 print ("Sim-Mem", initial_mem, self.bytes_per_word, self.word_log2)
56 if not initial_mem:
57 return
58
59 # different types of memory data structures recognised (for convenience)
60 if isinstance(initial_mem, list):
61 initial_mem = (0, initial_mem)
62 if isinstance(initial_mem, tuple):
63 startaddr, mem = initial_mem
64 initial_mem = {}
65 for i, val in enumerate(mem):
66 initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
67
68 for addr, (val, width) in initial_mem.items():
69 #val = swap_order(val, width)
70 self.st(addr, val, width, swap=False)
71
72 def _get_shifter_mask(self, wid, remainder):
73 shifter = ((self.bytes_per_word - wid) - remainder) * \
74 8 # bits per byte
75 # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
76 # BE/LE mode?
77 shifter = remainder * 8
78 mask = (1 << (wid * 8)) - 1
79 print ("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
80 return shifter, mask
81
82 # TODO: Implement ld/st of lesser width
83 def ld(self, address, width=8, swap=True, check_in_mem=False):
84 print("ld from addr 0x{:x} width {:d}".format(address, width))
85 remainder = address & (self.bytes_per_word - 1)
86 address = address >> self.word_log2
87 assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
88 if address in self.mem:
89 val = self.mem[address]
90 elif check_in_mem:
91 return None
92 else:
93 val = 0
94 print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val))
95
96 if width != self.bytes_per_word:
97 shifter, mask = self._get_shifter_mask(width, remainder)
98 print ("masking", hex(val), hex(mask<<shifter), shifter)
99 val = val & (mask << shifter)
100 val >>= shifter
101 if swap:
102 val = swap_order(val, width)
103 print("Read 0x{:x} from addr 0x{:x}".format(val, address))
104 return val
105
106 def st(self, addr, v, width=8, swap=True):
107 staddr = addr
108 remainder = addr & (self.bytes_per_word - 1)
109 addr = addr >> self.word_log2
110 print("Writing 0x{:x} to ST 0x{:x} memaddr 0x{:x}/{:x}".format(v,
111 staddr, addr, remainder, swap))
112 assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
113 if swap:
114 v = swap_order(v, width)
115 if width != self.bytes_per_word:
116 if addr in self.mem:
117 val = self.mem[addr]
118 else:
119 val = 0
120 shifter, mask = self._get_shifter_mask(width, remainder)
121 val &= ~(mask << shifter)
122 val |= v << shifter
123 self.mem[addr] = val
124 else:
125 self.mem[addr] = v
126 print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
127
128 def __call__(self, addr, sz):
129 val = self.ld(addr.value, sz)
130 print ("memread", addr, sz, val)
131 return SelectableInt(val, sz*8)
132
133 def memassign(self, addr, sz, val):
134 print ("memassign", addr, sz, val)
135 self.st(addr.value, val.value, sz)
136
137
138 class GPR(dict):
139 def __init__(self, decoder, regfile):
140 dict.__init__(self)
141 self.sd = decoder
142 for i in range(32):
143 self[i] = SelectableInt(regfile[i], 64)
144
145 def __call__(self, ridx):
146 return self[ridx]
147
148 def set_form(self, form):
149 self.form = form
150
151 def getz(self, rnum):
152 #rnum = rnum.value # only SelectableInt allowed
153 print("GPR getzero", rnum)
154 if rnum == 0:
155 return SelectableInt(0, 64)
156 return self[rnum]
157
158 def _get_regnum(self, attr):
159 getform = self.sd.sigforms[self.form]
160 rnum = getattr(getform, attr)
161 return rnum
162
163 def ___getitem__(self, attr):
164 print("GPR getitem", attr)
165 rnum = self._get_regnum(attr)
166 return self.regfile[rnum]
167
168 def dump(self):
169 for i in range(0, len(self), 8):
170 s = []
171 for j in range(8):
172 s.append("%08x" % self[i+j].value)
173 s = ' '.join(s)
174 print("reg", "%2d" % i, s)
175
176 class PC:
177 def __init__(self, pc_init=0):
178 self.CIA = SelectableInt(pc_init, 64)
179 self.NIA = self.CIA + SelectableInt(4, 64)
180
181 def update(self, namespace):
182 self.CIA = namespace['NIA'].narrow(64)
183 self.NIA = self.CIA + SelectableInt(4, 64)
184 namespace['CIA'] = self.CIA
185 namespace['NIA'] = self.NIA
186
187
188 class SPR(dict):
189 def __init__(self, dec2, initial_sprs={}):
190 self.sd = dec2
191 dict.__init__(self)
192 for key, v in initial_sprs.items():
193 if isinstance(key, SelectableInt):
194 key = key.value
195 key = special_sprs.get(key, key)
196 if isinstance(key, int):
197 info = spr_dict[key]
198 else:
199 info = spr_byname[key]
200 if not isinstance(v, SelectableInt):
201 v = SelectableInt(v, info.length)
202 self[key] = v
203
204 def __getitem__(self, key):
205 print ("get spr", key)
206 print ("dict", self.items())
207 # if key in special_sprs get the special spr, otherwise return key
208 if isinstance(key, SelectableInt):
209 key = key.value
210 if isinstance(key, int):
211 key = spr_dict[key].SPR
212 key = special_sprs.get(key, key)
213 if key in self:
214 res = dict.__getitem__(self, key)
215 else:
216 if isinstance(key, int):
217 info = spr_dict[key]
218 else:
219 info = spr_byname[key]
220 dict.__setitem__(self, key, SelectableInt(0, info.length))
221 res = dict.__getitem__(self, key)
222 print ("spr returning", key, res)
223 return res
224
225 def __setitem__(self, key, value):
226 if isinstance(key, SelectableInt):
227 key = key.value
228 if isinstance(key, int):
229 key = spr_dict[key].SPR
230 print ("spr key", key)
231 key = special_sprs.get(key, key)
232 print ("setting spr", key, value)
233 dict.__setitem__(self, key, value)
234
235 def __call__(self, ridx):
236 return self[ridx]
237
238
239 class ISACaller:
240 # decoder2 - an instance of power_decoder2
241 # regfile - a list of initial values for the registers
242 # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
243 # respect_pc - tracks the program counter. requires initial_insns
244 def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
245 initial_mem=None, initial_msr=0,
246 initial_insns=None, respect_pc=False,
247 disassembly=None,
248 initial_pc=0):
249
250 self.halted = False
251 self.respect_pc = respect_pc
252 if initial_sprs is None:
253 initial_sprs = {}
254 if initial_mem is None:
255 initial_mem = {}
256 if initial_insns is None:
257 initial_insns = {}
258 assert self.respect_pc == False, "instructions required to honor pc"
259
260 print ("ISACaller insns", respect_pc, initial_insns, disassembly)
261
262 # "fake program counter" mode (for unit testing)
263 self.fake_pc = 0
264 disasm_start = 0
265 if not respect_pc:
266 if isinstance(initial_mem, tuple):
267 self.fake_pc = initial_mem[0]
268 disasm_start = self.fake_pc
269 else:
270 disasm_start = initial_pc
271
272 # disassembly: we need this for now (not given from the decoder)
273 self.disassembly = {}
274 if disassembly:
275 for i, code in enumerate(disassembly):
276 self.disassembly[i*4 + disasm_start] = code
277
278 # set up registers, instruction memory, data memory, PC, SPRs, MSR
279 self.gpr = GPR(decoder2, regfile)
280 self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
281 self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
282 self.pc = PC()
283 self.spr = SPR(decoder2, initial_sprs)
284 self.msr = SelectableInt(initial_msr, 64) # underlying reg
285
286 # TODO, needed here:
287 # FPR (same as GPR except for FP nums)
288 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
289 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
290 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
291 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
292 # -- Done
293 # 2.3.2 LR (actually SPR #8) -- Done
294 # 2.3.3 CTR (actually SPR #9) -- Done
295 # 2.3.4 TAR (actually SPR #815)
296 # 3.2.2 p45 XER (actually SPR #1) -- Done
297 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
298
299 # create CR then allow portions of it to be "selectable" (below)
300 self._cr = SelectableInt(initial_cr, 64) # underlying reg
301 self.cr = FieldSelectableInt(self._cr, list(range(32,64)))
302
303 # "undefined", just set to variable-bit-width int (use exts "max")
304 self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
305
306 self.namespace = {}
307 self.namespace.update(self.spr)
308 self.namespace.update({'GPR': self.gpr,
309 'MEM': self.mem,
310 'SPR': self.spr,
311 'memassign': self.memassign,
312 'NIA': self.pc.NIA,
313 'CIA': self.pc.CIA,
314 'CR': self.cr,
315 'MSR': self.msr,
316 'undefined': self.undefined,
317 'mode_is_64bit': True,
318 'SO': XER_bits['SO']
319 })
320
321 # update pc to requested start point
322 self.set_pc(initial_pc)
323
324 # field-selectable versions of Condition Register TODO check bitranges?
325 self.crl = []
326 for i in range(8):
327 bits = tuple(range(i*4, (i+1)*4))# errr... maybe?
328 _cr = FieldSelectableInt(self.cr, bits)
329 self.crl.append(_cr)
330 self.namespace["CR%d" % i] = _cr
331
332 self.decoder = decoder2.dec
333 self.dec2 = decoder2
334
335 def TRAP(self, trap_addr=0x700, trap_bit=PI.TRAP):
336 print ("TRAP:", hex(trap_addr))
337 # store CIA(+4?) in SRR0, set NIA to 0x700
338 # store MSR in SRR1, set MSR to um errr something, have to check spec
339 self.spr['SRR0'] = self.pc.CIA
340 self.spr['SRR1'] = self.namespace['MSR']
341 self.trap_nia = SelectableInt(trap_addr, 64)
342 self.namespace['MSR'][63-trap_bit] = 1
343
344 def memassign(self, ea, sz, val):
345 self.mem.memassign(ea, sz, val)
346
347 def prep_namespace(self, formname, op_fields):
348 # TODO: get field names from form in decoder*1* (not decoder2)
349 # decoder2 is hand-created, and decoder1.sigform is auto-generated
350 # from spec
351 # then "yield" fields only from op_fields rather than hard-coded
352 # list, here.
353 fields = self.decoder.sigforms[formname]
354 for name in op_fields:
355 if name == 'spr':
356 sig = getattr(fields, name.upper())
357 else:
358 sig = getattr(fields, name)
359 val = yield sig
360 if name in ['BF', 'BFA']:
361 self.namespace[name] = val
362 else:
363 self.namespace[name] = SelectableInt(val, sig.width)
364
365 self.namespace['XER'] = self.spr['XER']
366 self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
367 self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
368
369 def handle_carry_(self, inputs, outputs, already_done):
370 inv_a = yield self.dec2.e.do.invert_a
371 if inv_a:
372 inputs[0] = ~inputs[0]
373
374 imm_ok = yield self.dec2.e.do.imm_data.ok
375 if imm_ok:
376 imm = yield self.dec2.e.do.imm_data.data
377 inputs.append(SelectableInt(imm, 64))
378 assert len(outputs) >= 1
379 print ("outputs", repr(outputs))
380 if isinstance(outputs, list) or isinstance(outputs, tuple):
381 output = outputs[0]
382 else:
383 output = outputs
384 gts = []
385 for x in inputs:
386 print ("gt input", x, output)
387 gt = (x > output)
388 gts.append(gt)
389 print(gts)
390 cy = 1 if any(gts) else 0
391 if not (1 & already_done):
392 self.spr['XER'][XER_bits['CA']] = cy
393
394 print ("inputs", inputs)
395 # 32 bit carry
396 gts = []
397 for x in inputs:
398 print ("input", x, output)
399 gt = (x[32:64] > output[32:64]) == SelectableInt(1, 1)
400 gts.append(gt)
401 cy32 = 1 if any(gts) else 0
402 if not (2 & already_done):
403 self.spr['XER'][XER_bits['CA32']] = cy32
404
405 def handle_overflow(self, inputs, outputs, div_overflow):
406 inv_a = yield self.dec2.e.do.invert_a
407 if inv_a:
408 inputs[0] = ~inputs[0]
409
410 imm_ok = yield self.dec2.e.do.imm_data.ok
411 if imm_ok:
412 imm = yield self.dec2.e.do.imm_data.data
413 inputs.append(SelectableInt(imm, 64))
414 assert len(outputs) >= 1
415 print ("handle_overflow", inputs, outputs, div_overflow)
416 if len(inputs) < 2 and div_overflow != 1:
417 return
418
419 # div overflow is different: it's returned by the pseudo-code
420 # because it's more complex than can be done by analysing the output
421 if div_overflow == 1:
422 ov, ov32 = 1, 1
423 # arithmetic overflow can be done by analysing the input and output
424 elif len(inputs) >= 2:
425 output = outputs[0]
426
427 # OV (64-bit)
428 input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
429 output_sgn = exts(output.value, output.bits) < 0
430 ov = 1 if input_sgn[0] == input_sgn[1] and \
431 output_sgn != input_sgn[0] else 0
432
433 # OV (32-bit)
434 input32_sgn = [exts(x.value, 32) < 0 for x in inputs]
435 output32_sgn = exts(output.value, 32) < 0
436 ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \
437 output32_sgn != input32_sgn[0] else 0
438
439 self.spr['XER'][XER_bits['OV']] = ov
440 self.spr['XER'][XER_bits['OV32']] = ov32
441 so = self.spr['XER'][XER_bits['SO']]
442 so = so | ov
443 self.spr['XER'][XER_bits['SO']] = so
444
445 def handle_comparison(self, outputs):
446 out = outputs[0]
447 out = exts(out.value, out.bits)
448 zero = SelectableInt(out == 0, 1)
449 positive = SelectableInt(out > 0, 1)
450 negative = SelectableInt(out < 0, 1)
451 SO = self.spr['XER'][XER_bits['SO']]
452 cr_field = selectconcat(negative, positive, zero, SO)
453 self.crl[0].eq(cr_field)
454
455 def set_pc(self, pc_val):
456 self.namespace['NIA'] = SelectableInt(pc_val, 64)
457 self.pc.update(self.namespace)
458
459 def setup_one(self):
460 """set up one instruction
461 """
462 if self.respect_pc:
463 pc = self.pc.CIA.value
464 else:
465 pc = self.fake_pc
466 self._pc = pc
467 ins = self.imem.ld(pc, 4, False, True)
468 if ins is None:
469 raise KeyError("no instruction at 0x%x" % pc)
470 print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
471 print ("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
472
473 yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
474 yield self.dec2.dec.bigendian.eq(0) # little / big?
475
476 def execute_one(self):
477 """execute one instruction
478 """
479 # get the disassembly code for this instruction
480 code = self.disassembly[self._pc]
481 print("sim-execute", hex(self._pc), code)
482 opname = code.split(' ')[0]
483 yield from self.call(opname)
484
485 if not self.respect_pc:
486 self.fake_pc += 4
487 print ("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value)
488
489 def get_assembly_name(self):
490 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
491 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
492 asmcode = yield self.dec2.dec.op.asmcode
493 asmop = insns.get(asmcode, None)
494
495 # sigh reconstruct the assembly instruction name
496 ov_en = yield self.dec2.e.do.oe.oe
497 ov_ok = yield self.dec2.e.do.oe.ok
498 if ov_en & ov_ok:
499 asmop += "."
500 lk = yield self.dec2.e.do.lk
501 if lk:
502 asmop += "l"
503 int_op = yield self.dec2.dec.op.internal_op
504 print ("int_op", int_op)
505 if int_op in [InternalOp.OP_B.value, InternalOp.OP_BC.value]:
506 AA = yield self.dec2.dec.fields.FormI.AA[0:-1]
507 print ("AA", AA)
508 if AA:
509 asmop += "a"
510 if int_op == InternalOp.OP_MFCR.value:
511 dec_insn = yield self.dec2.e.do.insn
512 if dec_insn & (1<<20) != 0: # sigh
513 asmop = 'mfocrf'
514 else:
515 asmop = 'mfcr'
516 # XXX TODO: for whatever weird reason this doesn't work
517 # https://bugs.libre-soc.org/show_bug.cgi?id=390
518 if int_op == InternalOp.OP_MTCRF.value:
519 dec_insn = yield self.dec2.e.do.insn
520 if dec_insn & (1<<20) != 0: # sigh
521 asmop = 'mtocrf'
522 else:
523 asmop = 'mtcrf'
524 return asmop
525
526 def call(self, name):
527 if self.halted:
528 print ("halted - not executing", name)
529 return
530
531 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
532 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
533 asmop = yield from self.get_assembly_name()
534 print ("call", name, asmop)
535
536 # check halted condition
537 if name == 'attn':
538 self.halted = True
539 return
540
541 # check illegal instruction
542 illegal = False
543 if name not in ['mtcrf', 'mtocrf']:
544 illegal = name != asmop
545
546 if illegal:
547 print ("name %s != %s - calling ILLEGAL trap" % (name, asmop))
548 self.TRAP(0x700, PI.ILLEG)
549 self.namespace['NIA'] = self.trap_nia
550 self.pc.update(self.namespace)
551 return
552
553 info = self.instrs[name]
554 yield from self.prep_namespace(info.form, info.op_fields)
555
556 # preserve order of register names
557 input_names = create_args(list(info.read_regs) +
558 list(info.uninit_regs))
559 print(input_names)
560
561 # main registers (RT, RA ...)
562 inputs = []
563 for name in input_names:
564 regnum = yield getattr(self.decoder, name)
565 regname = "_" + name
566 self.namespace[regname] = regnum
567 print('reading reg %d' % regnum)
568 inputs.append(self.gpr(regnum))
569
570 # "special" registers
571 for special in info.special_regs:
572 if special in special_sprs:
573 inputs.append(self.spr[special])
574 else:
575 inputs.append(self.namespace[special])
576
577 # clear trap (trap) NIA
578 self.trap_nia = None
579
580 print(inputs)
581 results = info.func(self, *inputs)
582 print(results)
583
584 # "inject" decorator takes namespace from function locals: we need to
585 # overwrite NIA being overwritten (sigh)
586 if self.trap_nia is not None:
587 self.namespace['NIA'] = self.trap_nia
588
589 print ("after func", self.namespace['CIA'], self.namespace['NIA'])
590
591 # detect if CA/CA32 already in outputs (sra*, basically)
592 already_done = 0
593 if info.write_regs:
594 output_names = create_args(info.write_regs)
595 for name in output_names:
596 if name == 'CA':
597 already_done |= 1
598 if name == 'CA32':
599 already_done |= 2
600
601 print ("carry already done?", bin(already_done))
602 carry_en = yield self.dec2.e.do.output_carry
603 if carry_en:
604 yield from self.handle_carry_(inputs, results, already_done)
605
606 # detect if overflow was in return result
607 overflow = None
608 if info.write_regs:
609 for name, output in zip(output_names, results):
610 if name == 'overflow':
611 overflow = output
612
613 ov_en = yield self.dec2.e.do.oe.oe
614 ov_ok = yield self.dec2.e.do.oe.ok
615 print ("internal overflow", overflow)
616 if ov_en & ov_ok:
617 yield from self.handle_overflow(inputs, results, overflow)
618
619 rc_en = yield self.dec2.e.do.rc.data
620 if rc_en:
621 self.handle_comparison(results)
622
623 # any modified return results?
624 if info.write_regs:
625 for name, output in zip(output_names, results):
626 if name == 'overflow': # ignore, done already (above)
627 continue
628 if isinstance(output, int):
629 output = SelectableInt(output, 256)
630 if name in ['CA', 'CA32']:
631 if carry_en:
632 print ("writing %s to XER" % name, output)
633 self.spr['XER'][XER_bits[name]] = output.value
634 else:
635 print ("NOT writing %s to XER" % name, output)
636 elif name in info.special_regs:
637 print('writing special %s' % name, output, special_sprs)
638 if name in special_sprs:
639 self.spr[name] = output
640 else:
641 self.namespace[name].eq(output)
642 if name == 'MSR':
643 print ('msr written', hex(self.msr.value))
644 else:
645 regnum = yield getattr(self.decoder, name)
646 print('writing reg %d %s' % (regnum, str(output)))
647 if output.bits > 64:
648 output = SelectableInt(output.value, 64)
649 self.gpr[regnum] = output
650
651 print ("end of call", self.namespace['CIA'], self.namespace['NIA'])
652 # UPDATE program counter
653 self.pc.update(self.namespace)
654
655
656 def inject():
657 """Decorator factory.
658
659 this decorator will "inject" variables into the function's namespace,
660 from the *dictionary* in self.namespace. it therefore becomes possible
661 to make it look like a whole stack of variables which would otherwise
662 need "self." inserted in front of them (*and* for those variables to be
663 added to the instance) "appear" in the function.
664
665 "self.namespace['SI']" for example becomes accessible as just "SI" but
666 *only* inside the function, when decorated.
667 """
668 def variable_injector(func):
669 @wraps(func)
670 def decorator(*args, **kwargs):
671 try:
672 func_globals = func.__globals__ # Python 2.6+
673 except AttributeError:
674 func_globals = func.func_globals # Earlier versions.
675
676 context = args[0].namespace # variables to be injected
677 saved_values = func_globals.copy() # Shallow copy of dict.
678 func_globals.update(context)
679 result = func(*args, **kwargs)
680 print ("globals after", func_globals['CIA'], func_globals['NIA'])
681 print ("args[0]", args[0].namespace['CIA'],
682 args[0].namespace['NIA'])
683 args[0].namespace = func_globals
684 #exec (func.__code__, func_globals)
685
686 #finally:
687 # func_globals = saved_values # Undo changes.
688
689 return result
690
691 return decorator
692
693 return variable_injector
694