comment ISACaller setup
[soc.git] / src / soc / decoder / isa / caller.py
1 """core of the python-based POWER9 simulator
2
3 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
4 not speed, it is for both learning and educational purposes, as well as
5 a method of verifying the HDL.
6 """
7
8 from functools import wraps
9 from soc.decoder.orderedset import OrderedSet
10 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
11 selectconcat)
12 from soc.decoder.power_enums import spr_dict, XER_bits
13 from soc.decoder.helpers import exts
14 from collections import namedtuple
15 import math
16
17 instruction_info = namedtuple('instruction_info',
18 'func read_regs uninit_regs write_regs ' + \
19 'special_regs op_fields form asmregs')
20
21 special_sprs = {
22 'LR': 8,
23 'CTR': 9,
24 'TAR': 815,
25 'XER': 1,
26 'VRSAVE': 256}
27
28
29 def swap_order(x, nbytes):
30 x = x.to_bytes(nbytes, byteorder='little')
31 x = int.from_bytes(x, byteorder='big', signed=False)
32 return x
33
34
35 def create_args(reglist, extra=None):
36 args = OrderedSet()
37 for reg in reglist:
38 args.add(reg)
39 args = list(args)
40 if extra:
41 args = [extra] + args
42 return args
43
44
45 class Mem:
46
47 def __init__(self, row_bytes=8, initial_mem=None):
48 self.mem = {}
49 self.bytes_per_word = row_bytes
50 self.word_log2 = math.ceil(math.log2(row_bytes))
51 print ("Sim-Mem", initial_mem, self.bytes_per_word, self.word_log2)
52 if not initial_mem:
53 return
54
55 # different types of memory data structures recognised (for convenience)
56 if isinstance(initial_mem, list):
57 initial_mem = (0, initial_mem)
58 if isinstance(initial_mem, tuple):
59 startaddr, mem = initial_mem
60 initial_mem = {}
61 for i, val in enumerate(mem):
62 initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
63
64 for addr, (val, width) in initial_mem.items():
65 #val = swap_order(val, width)
66 self.st(addr, val, width, swap=False)
67
68 def _get_shifter_mask(self, wid, remainder):
69 shifter = ((self.bytes_per_word - wid) - remainder) * \
70 8 # bits per byte
71 # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
72 # BE/LE mode?
73 shifter = remainder * 8
74 mask = (1 << (wid * 8)) - 1
75 print ("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
76 return shifter, mask
77
78 # TODO: Implement ld/st of lesser width
79 def ld(self, address, width=8, swap=True):
80 print("ld from addr 0x{:x} width {:d}".format(address, width))
81 remainder = address & (self.bytes_per_word - 1)
82 address = address >> self.word_log2
83 assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
84 if address in self.mem:
85 val = self.mem[address]
86 else:
87 val = 0
88 print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val))
89
90 if width != self.bytes_per_word:
91 shifter, mask = self._get_shifter_mask(width, remainder)
92 print ("masking", hex(val), hex(mask<<shifter), shifter)
93 val = val & (mask << shifter)
94 val >>= shifter
95 if swap:
96 val = swap_order(val, width)
97 print("Read 0x{:x} from addr 0x{:x}".format(val, address))
98 return val
99
100 def st(self, addr, v, width=8, swap=True):
101 staddr = addr
102 remainder = addr & (self.bytes_per_word - 1)
103 addr = addr >> self.word_log2
104 print("Writing 0x{:x} to ST 0x{:x} memaddr 0x{:x}/{:x}".format(v,
105 staddr, addr, remainder, swap))
106 assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
107 if swap:
108 v = swap_order(v, width)
109 if width != self.bytes_per_word:
110 if addr in self.mem:
111 val = self.mem[addr]
112 else:
113 val = 0
114 shifter, mask = self._get_shifter_mask(width, remainder)
115 val &= ~(mask << shifter)
116 val |= v << shifter
117 self.mem[addr] = val
118 else:
119 self.mem[addr] = v
120 print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
121
122 def __call__(self, addr, sz):
123 val = self.ld(addr.value, sz)
124 print ("memread", addr, sz, val)
125 return SelectableInt(val, sz*8)
126
127 def memassign(self, addr, sz, val):
128 print ("memassign", addr, sz, val)
129 self.st(addr.value, val.value, sz)
130
131
132 class GPR(dict):
133 def __init__(self, decoder, regfile):
134 dict.__init__(self)
135 self.sd = decoder
136 for i in range(32):
137 self[i] = SelectableInt(regfile[i], 64)
138
139 def __call__(self, ridx):
140 return self[ridx]
141
142 def set_form(self, form):
143 self.form = form
144
145 def getz(self, rnum):
146 #rnum = rnum.value # only SelectableInt allowed
147 print("GPR getzero", rnum)
148 if rnum == 0:
149 return SelectableInt(0, 64)
150 return self[rnum]
151
152 def _get_regnum(self, attr):
153 getform = self.sd.sigforms[self.form]
154 rnum = getattr(getform, attr)
155 return rnum
156
157 def ___getitem__(self, attr):
158 print("GPR getitem", attr)
159 rnum = self._get_regnum(attr)
160 return self.regfile[rnum]
161
162 def dump(self):
163 for i in range(0, len(self), 8):
164 s = []
165 for j in range(8):
166 s.append("%08x" % self[i+j].value)
167 s = ' '.join(s)
168 print("reg", "%2d" % i, s)
169
170 class PC:
171 def __init__(self, pc_init=0):
172 self.CIA = SelectableInt(pc_init, 64)
173 self.NIA = self.CIA + SelectableInt(4, 64)
174
175 def update(self, namespace):
176 self.CIA = namespace['NIA'].narrow(64)
177 self.NIA = self.CIA + SelectableInt(4, 64)
178 namespace['CIA'] = self.CIA
179 namespace['NIA'] = self.NIA
180
181
182 class SPR(dict):
183 def __init__(self, dec2, initial_sprs={}):
184 self.sd = dec2
185 dict.__init__(self)
186 self.update(initial_sprs)
187
188 def __getitem__(self, key):
189 # if key in special_sprs get the special spr, otherwise return key
190 if isinstance(key, SelectableInt):
191 key = key.value
192 key = special_sprs.get(key, key)
193 if key in self:
194 return dict.__getitem__(self, key)
195 else:
196 info = spr_dict[key]
197 dict.__setitem__(self, key, SelectableInt(0, info.length))
198 return dict.__getitem__(self, key)
199
200 def __setitem__(self, key, value):
201 if isinstance(key, SelectableInt):
202 key = key.value
203 key = special_sprs.get(key, key)
204 dict.__setitem__(self, key, value)
205
206 def __call__(self, ridx):
207 return self[ridx]
208
209
210 class ISACaller:
211 # decoder2 - an instance of power_decoder2
212 # regfile - a list of initial values for the registers
213 # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
214 # respect_pc - tracks the program counter. requires initial_insns
215 def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
216 initial_mem=None, initial_msr=0,
217 initial_insns=None, respect_pc=False,
218 disassembly=None):
219
220 self.respect_pc = respect_pc
221 if initial_sprs is None:
222 initial_sprs = {}
223 if initial_mem is None:
224 initial_mem = {}
225 if initial_insns is None:
226 initial_insns = {}
227 assert self.respect_pc == False, "instructions required to honor pc"
228
229
230 # "fake program counter" mode (for unit testing)
231 if not respect_pc:
232 if isinstance(initial_mem, tuple):
233 self.fake_pc = initial_mem[0]
234 else:
235 self.fake_pc = 0
236
237 # disassembly: we need this for now (not given from the decoder)
238 self.disassembly = {}
239 if disassembly:
240 for i, code in enumerate(disassembly):
241 self.disassembly[i*4 + self.fake_pc] = code
242
243 # set up registers, instruction memory, data memory, PC, SPRs, MSR
244 self.gpr = GPR(decoder2, regfile)
245 self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
246 self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
247 self.pc = PC()
248 self.spr = SPR(decoder2, initial_sprs)
249 self.msr = SelectableInt(initial_msr, 64) # underlying reg
250
251 # TODO, needed here:
252 # FPR (same as GPR except for FP nums)
253 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
254 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
255 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
256 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
257 # -- Done
258 # 2.3.2 LR (actually SPR #8) -- Done
259 # 2.3.3 CTR (actually SPR #9) -- Done
260 # 2.3.4 TAR (actually SPR #815)
261 # 3.2.2 p45 XER (actually SPR #1) -- Done
262 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
263
264 # create CR then allow portions of it to be "selectable" (below)
265 self._cr = SelectableInt(initial_cr, 64) # underlying reg
266 self.cr = FieldSelectableInt(self._cr, list(range(32,64)))
267
268 # "undefined", just set to variable-bit-width int (use exts "max")
269 self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
270
271 self.namespace = {'GPR': self.gpr,
272 'MEM': self.mem,
273 'SPR': self.spr,
274 'memassign': self.memassign,
275 'NIA': self.pc.NIA,
276 'CIA': self.pc.CIA,
277 'CR': self.cr,
278 'MSR': self.msr,
279 'undefined': self.undefined,
280 'mode_is_64bit': True,
281 'SO': XER_bits['SO']
282 }
283
284 # field-selectable versions of Condition Register TODO check bitranges?
285 self.crl = []
286 for i in range(8):
287 bits = tuple(range(i*4, (i+1)*4))# errr... maybe?
288 _cr = FieldSelectableInt(self.cr, bits)
289 self.crl.append(_cr)
290 self.namespace["CR%d" % i] = _cr
291
292 self.decoder = decoder2.dec
293 self.dec2 = decoder2
294
295 def TRAP(self, trap_addr=0x700):
296 print ("TRAP: TODO")
297 # store CIA(+4?) in SRR0, set NIA to 0x700
298 # store MSR in SRR1, set MSR to um errr something, have to check spec
299
300 def memassign(self, ea, sz, val):
301 self.mem.memassign(ea, sz, val)
302
303 def prep_namespace(self, formname, op_fields):
304 # TODO: get field names from form in decoder*1* (not decoder2)
305 # decoder2 is hand-created, and decoder1.sigform is auto-generated
306 # from spec
307 # then "yield" fields only from op_fields rather than hard-coded
308 # list, here.
309 fields = self.decoder.sigforms[formname]
310 for name in op_fields:
311 if name == 'spr':
312 sig = getattr(fields, name.upper())
313 else:
314 sig = getattr(fields, name)
315 val = yield sig
316 if name in ['BF', 'BFA']:
317 self.namespace[name] = val
318 else:
319 self.namespace[name] = SelectableInt(val, sig.width)
320
321 self.namespace['XER'] = self.spr['XER']
322 self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
323 self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
324
325 def handle_carry_(self, inputs, outputs, already_done):
326 inv_a = yield self.dec2.e.invert_a
327 if inv_a:
328 inputs[0] = ~inputs[0]
329
330 imm_ok = yield self.dec2.e.imm_data.ok
331 if imm_ok:
332 imm = yield self.dec2.e.imm_data.data
333 inputs.append(SelectableInt(imm, 64))
334 assert len(outputs) >= 1
335 output = outputs[0]
336 gts = [(x > output) for x in inputs]
337 print(gts)
338 cy = 1 if any(gts) else 0
339 if not (1 & already_done):
340 self.spr['XER'][XER_bits['CA']] = cy
341
342 print ("inputs", inputs)
343 # 32 bit carry
344 gts = [(x[32:64] > output[32:64]) == SelectableInt(1, 1)
345 for x in inputs]
346 cy32 = 1 if any(gts) else 0
347 if not (2 & already_done):
348 self.spr['XER'][XER_bits['CA32']] = cy32
349
350 def handle_overflow(self, inputs, outputs):
351 inv_a = yield self.dec2.e.invert_a
352 if inv_a:
353 inputs[0] = ~inputs[0]
354
355 imm_ok = yield self.dec2.e.imm_data.ok
356 if imm_ok:
357 imm = yield self.dec2.e.imm_data.data
358 inputs.append(SelectableInt(imm, 64))
359 assert len(outputs) >= 1
360 print ("handle_overflow", inputs, outputs)
361 if len(inputs) >= 2:
362 output = outputs[0]
363
364 # OV (64-bit)
365 input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
366 output_sgn = exts(output.value, output.bits) < 0
367 ov = 1 if input_sgn[0] == input_sgn[1] and \
368 output_sgn != input_sgn[0] else 0
369
370 # OV (32-bit)
371 input32_sgn = [exts(x.value, 32) < 0 for x in inputs]
372 output32_sgn = exts(output.value, 32) < 0
373 ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \
374 output32_sgn != input32_sgn[0] else 0
375
376 self.spr['XER'][XER_bits['OV']] = ov
377 self.spr['XER'][XER_bits['OV32']] = ov32
378 so = self.spr['XER'][XER_bits['SO']]
379 so = so | ov
380 self.spr['XER'][XER_bits['SO']] = so
381
382 def handle_comparison(self, outputs):
383 out = outputs[0]
384 out = exts(out.value, out.bits)
385 zero = SelectableInt(out == 0, 1)
386 positive = SelectableInt(out > 0, 1)
387 negative = SelectableInt(out < 0, 1)
388 SO = self.spr['XER'][XER_bits['SO']]
389 cr_field = selectconcat(negative, positive, zero, SO)
390 self.crl[0].eq(cr_field)
391
392 def set_pc(self, pc_val):
393 self.namespace['NIA'] = SelectableInt(pc_val, 64)
394 self.pc.update(self.namespace)
395
396 def execute_one(self):
397 if self.respect_pc:
398 pc = self.pc.CIA.value
399 else:
400 pc = self.fake_pc
401 self.fake_pc += 4
402 ins = yield self.imem.ld(pc, 4, False)
403 yield self.pdecode2.dec.raw_opcode_in.eq(ins)
404 yield self.pdecode2.dec.bigendian.eq(0) # little / big?
405 opname = code.split(' ')[0]
406 yield from call(opname)
407
408 def call(self, name):
409 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
410 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
411 info = self.instrs[name]
412 yield from self.prep_namespace(info.form, info.op_fields)
413
414 # preserve order of register names
415 input_names = create_args(list(info.read_regs) + list(info.uninit_regs))
416 print(input_names)
417
418 # main registers (RT, RA ...)
419 inputs = []
420 for name in input_names:
421 regnum = yield getattr(self.decoder, name)
422 regname = "_" + name
423 self.namespace[regname] = regnum
424 print('reading reg %d' % regnum)
425 inputs.append(self.gpr(regnum))
426
427 # "special" registers
428 for special in info.special_regs:
429 if special in special_sprs:
430 inputs.append(self.spr[special])
431 else:
432 inputs.append(self.namespace[special])
433
434 print(inputs)
435 results = info.func(self, *inputs)
436 print(results)
437
438 # detect if CA/CA32 already in outputs (sra*, basically)
439 already_done = 0
440 if info.write_regs:
441 output_names = create_args(info.write_regs)
442 for name in output_names:
443 if name == 'CA':
444 already_done |= 1
445 if name == 'CA32':
446 already_done |= 2
447
448 print ("carry already done?", bin(already_done))
449 carry_en = yield self.dec2.e.output_carry
450 if carry_en:
451 yield from self.handle_carry_(inputs, results, already_done)
452 ov_en = yield self.dec2.e.oe.oe
453 ov_ok = yield self.dec2.e.oe.ok
454 if ov_en & ov_ok:
455 yield from self.handle_overflow(inputs, results)
456 rc_en = yield self.dec2.e.rc.data
457 if rc_en:
458 self.handle_comparison(results)
459
460 # any modified return results?
461 if info.write_regs:
462 for name, output in zip(output_names, results):
463 if isinstance(output, int):
464 output = SelectableInt(output, 256)
465 if name in ['CA', 'CA32']:
466 if carry_en:
467 print ("writing %s to XER" % name, output)
468 self.spr['XER'][XER_bits[name]] = output.value
469 else:
470 print ("NOT writing %s to XER" % name, output)
471 elif name in info.special_regs:
472 print('writing special %s' % name, output, special_sprs)
473 if name in special_sprs:
474 self.spr[name] = output
475 else:
476 self.namespace[name].eq(output)
477 else:
478 regnum = yield getattr(self.decoder, name)
479 print('writing reg %d %s' % (regnum, str(output)))
480 if output.bits > 64:
481 output = SelectableInt(output.value, 64)
482 self.gpr[regnum] = output
483
484 # update program counter
485 self.pc.update(self.namespace)
486
487
488 def inject():
489 """Decorator factory.
490
491 this decorator will "inject" variables into the function's namespace,
492 from the *dictionary* in self.namespace. it therefore becomes possible
493 to make it look like a whole stack of variables which would otherwise
494 need "self." inserted in front of them (*and* for those variables to be
495 added to the instance) "appear" in the function.
496
497 "self.namespace['SI']" for example becomes accessible as just "SI" but
498 *only* inside the function, when decorated.
499 """
500 def variable_injector(func):
501 @wraps(func)
502 def decorator(*args, **kwargs):
503 try:
504 func_globals = func.__globals__ # Python 2.6+
505 except AttributeError:
506 func_globals = func.func_globals # Earlier versions.
507
508 context = args[0].namespace # variables to be injected
509 saved_values = func_globals.copy() # Shallow copy of dict.
510 func_globals.update(context)
511 result = func(*args, **kwargs)
512 args[0].namespace = func_globals
513 #exec (func.__code__, func_globals)
514
515 #finally:
516 # func_globals = saved_values # Undo changes.
517
518 return result
519
520 return decorator
521
522 return variable_injector
523