src/soc/decoder/isa/caller.py

   1 from functools import wraps
   2 from soc.decoder.orderedset import OrderedSet
   3 from soc.decoder.selectable_int import SelectableInt, selectconcat
   4 import math
   5
   6 def create_args(reglist, extra=None):
   7     args = OrderedSet()
   8     for reg in reglist:
   9         args.add(reg)
  10     args = list(args)
  11     if extra:
  12         args = [extra] + args
  13     return args
  14
  15 class Mem:
  16
  17     def __init__(self, bytes_per_word=8):
  18         self.mem = {}
  19         self.bytes_per_word = bytes_per_word
  20         self.word_log2 = math.ceil(math.log2(bytes_per_word))
  21
  22     def _get_shifter_mask(self, width, remainder):
  23         shifter = ((self.bytes_per_word - width) - remainder) * \
  24             8  # bits per byte
  25         mask = (1 << (width * 8)) - 1
  26         return shifter, mask
  27
  28     # TODO: Implement ld/st of lesser width
  29     def ld(self, address, width=8):
  30         remainder = address & (self.bytes_per_word - 1)
  31         address = address >> self.word_log2
  32         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  33         if address in self.mem:
  34             val = self.mem[address]
  35         else:
  36             val = 0
  37
  38         if width != self.bytes_per_word:
  39             shifter, mask = self._get_shifter_mask(width, remainder)
  40             val = val & (mask << shifter)
  41             val >>= shifter
  42         print("Read {:x} from addr {:x}".format(val, address))
  43         return val
  44
  45     def st(self, address, value, width=8):
  46         remainder = address & (self.bytes_per_word - 1)
  47         address = address >> self.word_log2
  48         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  49         print("Writing {:x} to addr {:x}".format(value, address))
  50         if width != self.bytes_per_word:
  51             if address in self.mem:
  52                 val = self.mem[address]
  53             else:
  54                 val = 0
  55             shifter, mask = self._get_shifter_mask(width, remainder)
  56             val &= ~(mask << shifter)
  57             val |= value << shifter
  58             self.mem[address] = val
  59         else:
  60             self.mem[address] = value
  61
  62     def __call__(self, addr, sz):
  63         val = self.ld(addr.value, sz)
  64         print ("memread", addr, sz, val)
  65         return SelectableInt(val, sz*8)
  66
  67     def memassign(self, addr, sz, val):
  68         print ("memassign", addr, sz, val)
  69         self.st(addr.value, val.value, sz)
  70
  71
  72 class GPR(dict):
  73     def __init__(self, decoder, regfile):
  74         dict.__init__(self)
  75         self.sd = decoder
  76         for i in range(32):
  77             self[i] = SelectableInt(regfile[i], 64)
  78
  79     def __call__(self, ridx):
  80         return self[ridx]
  81
  82     def set_form(self, form):
  83         self.form = form
  84
  85     def getz(self, rnum):
  86         #rnum = rnum.value # only SelectableInt allowed
  87         print("GPR getzero", rnum)
  88         if rnum == 0:
  89             return SelectableInt(0, 64)
  90         return self[rnum]
  91
  92     def _get_regnum(self, attr):
  93         getform = self.sd.sigforms[self.form]
  94         rnum = getattr(getform, attr)
  95         return rnum
  96
  97     def ___getitem__(self, attr):
  98         print("GPR getitem", attr)
  99         rnum = self._get_regnum(attr)
 100         return self.regfile[rnum]
 101
 102     def dump(self):
 103         for i in range(0, len(self), 8):
 104             s = []
 105             for j in range(8):
 106                 s.append("%08x" % self[i+j].value)
 107             s = ' '.join(s)
 108             print("reg", "%2d" % i, s)
 109
 110
 111 class ISACaller:
 112     # decoder2 - an instance of power_decoder2
 113     # regfile - a list of initial values for the registers
 114     def __init__(self, decoder2, regfile):
 115         self.gpr = GPR(decoder2, regfile)
 116         self.mem = Mem()
 117         self.namespace = {'GPR': self.gpr,
 118                           'MEM': self.mem,
 119                           'memassign': self.memassign
 120                           }
 121         self.decoder = decoder2
 122
 123     def memassign(self, ea, sz, val):
 124         self.mem.memassign(ea, sz, val)
 125
 126     def prep_namespace(self, formname, op_fields):
 127         # TODO: get field names from form in decoder*1* (not decoder2)
 128         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 129         # from spec
 130         # then "yield" fields only from op_fields rather than hard-coded
 131         # list, here.
 132         fields = self.decoder.sigforms[formname]
 133         for name in fields._fields:
 134             if name not in ["RA", "RB", "RT"]:
 135                 sig = getattr(fields, name)
 136                 val = yield sig
 137                 self.namespace[name] = SelectableInt(val, sig.width)
 138
 139     def call(self, name):
 140         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 141         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 142         fn, read_regs, uninit_regs, write_regs, op_fields, form, asmregs \
 143             = self.instrs[name]
 144         yield from self.prep_namespace(form, op_fields)
 145
 146         input_names = create_args(read_regs | uninit_regs)
 147         print(input_names)
 148
 149         inputs = []
 150         for name in input_names:
 151             regnum = yield getattr(self.decoder, name)
 152             regname = "_" + name
 153             self.namespace[regname] = regnum
 154             print('reading reg %d' % regnum)
 155             inputs.append(self.gpr(regnum))
 156         print(inputs)
 157         results = fn(self, *inputs)
 158         print(results)
 159
 160         if write_regs:
 161             output_names = create_args(write_regs)
 162             for name, output in zip(output_names, results):
 163                 regnum = yield getattr(self.decoder, name)
 164                 print('writing reg %d' % regnum)
 165                 if output.bits > 64:
 166                     output = SelectableInt(output.value, 64)
 167                 self.gpr[regnum] = output
 168
 169
 170 def inject():
 171     """ Decorator factory. """
 172     def variable_injector(func):
 173         @wraps(func)
 174         def decorator(*args, **kwargs):
 175             try:
 176                 func_globals = func.__globals__  # Python 2.6+
 177             except AttributeError:
 178                 func_globals = func.func_globals  # Earlier versions.
 179
 180             context = args[0].namespace
 181             saved_values = func_globals.copy()  # Shallow copy of dict.
 182             func_globals.update(context)
 183
 184             result = func(*args, **kwargs)
 185             #exec (func.__code__, func_globals)
 186
 187             #finally:
 188             #    func_globals = saved_values  # Undo changes.
 189
 190             return result
 191
 192         return decorator
 193
 194     return variable_injector
 195