src/soc/decoder/isa/caller.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Copyright (C) 2020 Michael Nolan
   4 # Funded by NLnet http://nlnet.nl
   5 """core of the python-based POWER9 simulator
   6
   7 this is part of a cycle-accurate POWER9 simulator.  its primary purpose is
   8 not speed, it is for both learning and educational purposes, as well as
   9 a method of verifying the HDL.
  10
  11 related bugs:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=424
  14 """
  15
  16 from nmigen.back.pysim import Settle
  17 from functools import wraps
  18 from copy import copy
  19 from soc.decoder.orderedset import OrderedSet
  20 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
  21                                         selectconcat)
  22 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
  23                                      insns, MicrOp, In1Sel, In2Sel, In3Sel,
  24                                      OutSel, CROutSel)
  25 from soc.decoder.helpers import exts, gtu, ltu, undefined
  26 from soc.consts import PIb, MSRb  # big-endian (PowerISA versions)
  27 from soc.decoder.power_svp64 import SVP64RM, decode_extra
  28
  29 from collections import namedtuple
  30 import math
  31 import sys
  32
  33 instruction_info = namedtuple('instruction_info',
  34                               'func read_regs uninit_regs write_regs ' +
  35                               'special_regs op_fields form asmregs')
  36
  37 special_sprs = {
  38     'LR': 8,
  39     'CTR': 9,
  40     'TAR': 815,
  41     'XER': 1,
  42     'VRSAVE': 256}
  43
  44
  45 def swap_order(x, nbytes):
  46     x = x.to_bytes(nbytes, byteorder='little')
  47     x = int.from_bytes(x, byteorder='big', signed=False)
  48     return x
  49
  50
  51 REG_SORT_ORDER = {
  52     # TODO (lkcl): adjust other registers that should be in a particular order
  53     # probably CA, CA32, and CR
  54     "RT": 0,
  55     "RA": 0,
  56     "RB": 0,
  57     "RS": 0,
  58     "CR": 0,
  59     "LR": 0,
  60     "CTR": 0,
  61     "TAR": 0,
  62     "CA": 0,
  63     "CA32": 0,
  64     "MSR": 0,
  65
  66     "overflow": 1,
  67 }
  68
  69
  70 def create_args(reglist, extra=None):
  71     retval = list(OrderedSet(reglist))
  72     retval.sort(key=lambda reg: REG_SORT_ORDER[reg])
  73     if extra is not None:
  74         return [extra] + retval
  75     return retval
  76
  77
  78 class Mem:
  79
  80     def __init__(self, row_bytes=8, initial_mem=None):
  81         self.mem = {}
  82         self.bytes_per_word = row_bytes
  83         self.word_log2 = math.ceil(math.log2(row_bytes))
  84         print("Sim-Mem", initial_mem, self.bytes_per_word, self.word_log2)
  85         if not initial_mem:
  86             return
  87
  88         # different types of memory data structures recognised (for convenience)
  89         if isinstance(initial_mem, list):
  90             initial_mem = (0, initial_mem)
  91         if isinstance(initial_mem, tuple):
  92             startaddr, mem = initial_mem
  93             initial_mem = {}
  94             for i, val in enumerate(mem):
  95                 initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
  96
  97         for addr, (val, width) in initial_mem.items():
  98             #val = swap_order(val, width)
  99             self.st(addr, val, width, swap=False)
 100
 101     def _get_shifter_mask(self, wid, remainder):
 102         shifter = ((self.bytes_per_word - wid) - remainder) * \
 103             8  # bits per byte
 104         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
 105         # BE/LE mode?
 106         shifter = remainder * 8
 107         mask = (1 << (wid * 8)) - 1
 108         print("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
 109         return shifter, mask
 110
 111     # TODO: Implement ld/st of lesser width
 112     def ld(self, address, width=8, swap=True, check_in_mem=False):
 113         print("ld from addr 0x{:x} width {:d}".format(address, width))
 114         remainder = address & (self.bytes_per_word - 1)
 115         address = address >> self.word_log2
 116         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
 117         if address in self.mem:
 118             val = self.mem[address]
 119         elif check_in_mem:
 120             return None
 121         else:
 122             val = 0
 123         print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val))
 124
 125         if width != self.bytes_per_word:
 126             shifter, mask = self._get_shifter_mask(width, remainder)
 127             print("masking", hex(val), hex(mask << shifter), shifter)
 128             val = val & (mask << shifter)
 129             val >>= shifter
 130         if swap:
 131             val = swap_order(val, width)
 132         print("Read 0x{:x} from addr 0x{:x}".format(val, address))
 133         return val
 134
 135     def st(self, addr, v, width=8, swap=True):
 136         staddr = addr
 137         remainder = addr & (self.bytes_per_word - 1)
 138         addr = addr >> self.word_log2
 139         print("Writing 0x{:x} to ST 0x{:x} "
 140               "memaddr 0x{:x}/{:x}".format(v, staddr, addr, remainder, swap))
 141         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
 142         if swap:
 143             v = swap_order(v, width)
 144         if width != self.bytes_per_word:
 145             if addr in self.mem:
 146                 val = self.mem[addr]
 147             else:
 148                 val = 0
 149             shifter, mask = self._get_shifter_mask(width, remainder)
 150             val &= ~(mask << shifter)
 151             val |= v << shifter
 152             self.mem[addr] = val
 153         else:
 154             self.mem[addr] = v
 155         print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
 156
 157     def __call__(self, addr, sz):
 158         val = self.ld(addr.value, sz, swap=False)
 159         print("memread", addr, sz, val)
 160         return SelectableInt(val, sz*8)
 161
 162     def memassign(self, addr, sz, val):
 163         print("memassign", addr, sz, val)
 164         self.st(addr.value, val.value, sz, swap=False)
 165
 166
 167 class GPR(dict):
 168     def __init__(self, decoder, isacaller, svstate, regfile):
 169         dict.__init__(self)
 170         self.sd = decoder
 171         self.isacaller = isacaller
 172         self.svstate = svstate
 173         for i in range(32):
 174             self[i] = SelectableInt(regfile[i], 64)
 175
 176     def __call__(self, ridx):
 177         return self[ridx]
 178
 179     def set_form(self, form):
 180         self.form = form
 181
 182     def getz(self, rnum):
 183         # rnum = rnum.value # only SelectableInt allowed
 184         print("GPR getzero", rnum)
 185         if rnum == 0:
 186             return SelectableInt(0, 64)
 187         return self[rnum]
 188
 189     def _get_regnum(self, attr):
 190         getform = self.sd.sigforms[self.form]
 191         rnum = getattr(getform, attr)
 192         return rnum
 193
 194     def ___getitem__(self, attr):
 195         """ XXX currently not used
 196         """
 197         rnum = self._get_regnum(attr)
 198         offs = self.svstate.srcstep
 199         print("GPR getitem", attr, rnum, "srcoffs", offs)
 200         return self.regfile[rnum]
 201
 202     def dump(self):
 203         for i in range(0, len(self), 8):
 204             s = []
 205             for j in range(8):
 206                 s.append("%08x" % self[i+j].value)
 207             s = ' '.join(s)
 208             print("reg", "%2d" % i, s)
 209
 210
 211 class PC:
 212     def __init__(self, pc_init=0):
 213         self.CIA = SelectableInt(pc_init, 64)
 214         self.NIA = self.CIA + SelectableInt(4, 64) # only true for v3.0B!
 215
 216     def update_nia(self, is_svp64):
 217         increment = 8 if is_svp64 else 4
 218         self.NIA = self.CIA + SelectableInt(increment, 64)
 219
 220     def update(self, namespace, is_svp64):
 221         """updates the program counter (PC) by 4 if v3.0B mode or 8 if SVP64
 222         """
 223         self.CIA = namespace['NIA'].narrow(64)
 224         self.update_nia(is_svp64)
 225         namespace['CIA'] = self.CIA
 226         namespace['NIA'] = self.NIA
 227
 228
 229 # Simple-V: see https://libre-soc.org/openpower/sv
 230 class SVP64State:
 231     def __init__(self, init=0):
 232         self.spr = SelectableInt(init, 32)
 233         # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
 234         self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7)))
 235         self.vl = FieldSelectableInt(self.spr, tuple(range(7,14)))
 236         self.srcstep = FieldSelectableInt(self.spr, tuple(range(14,21)))
 237         self.dststep = FieldSelectableInt(self.spr, tuple(range(21,28)))
 238         self.subvl = FieldSelectableInt(self.spr, tuple(range(28,30)))
 239         self.svstep = FieldSelectableInt(self.spr, tuple(range(30,32)))
 240
 241
 242 # SVP64 ReMap field
 243 class SVP64RMFields:
 244     def __init__(self, init=0):
 245         self.spr = SelectableInt(init, 24)
 246         # SVP64 RM fields: see https://libre-soc.org/openpower/sv/svp64/
 247         self.mmode = FieldSelectableInt(self.spr, [0])
 248         self.mask = FieldSelectableInt(self.spr, tuple(range(1,4)))
 249         self.elwidth = FieldSelectableInt(self.spr, tuple(range(4,6)))
 250         self.ewsrc = FieldSelectableInt(self.spr, tuple(range(6,8)))
 251         self.subvl = FieldSelectableInt(self.spr, tuple(range(8,10)))
 252         self.extra = FieldSelectableInt(self.spr, tuple(range(10,19)))
 253         self.mode = FieldSelectableInt(self.spr, tuple(range(19,24)))
 254
 255
 256 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
 257 class SVP64PrefixFields:
 258     def __init__(self):
 259         self.insn = SelectableInt(0, 32)
 260         # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap
 261         self.major = FieldSelectableInt(self.insn, tuple(range(0,6)))
 262         self.pid = FieldSelectableInt(self.insn, (7, 9)) # must be 0b11
 263         rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM (ReMap)
 264         self.rm = FieldSelectableInt(self.insn, rmfields)
 265
 266
 267 SV64P_MAJOR_SIZE = len(SVP64PrefixFields().major.br)
 268 SV64P_PID_SIZE = len(SVP64PrefixFields().pid.br)
 269 SV64P_RM_SIZE = len(SVP64PrefixFields().rm.br)
 270
 271
 272 class SPR(dict):
 273     def __init__(self, dec2, initial_sprs={}):
 274         self.sd = dec2
 275         dict.__init__(self)
 276         for key, v in initial_sprs.items():
 277             if isinstance(key, SelectableInt):
 278                 key = key.value
 279             key = special_sprs.get(key, key)
 280             if isinstance(key, int):
 281                 info = spr_dict[key]
 282             else:
 283                 info = spr_byname[key]
 284             if not isinstance(v, SelectableInt):
 285                 v = SelectableInt(v, info.length)
 286             self[key] = v
 287
 288     def __getitem__(self, key):
 289         print("get spr", key)
 290         print("dict", self.items())
 291         # if key in special_sprs get the special spr, otherwise return key
 292         if isinstance(key, SelectableInt):
 293             key = key.value
 294         if isinstance(key, int):
 295             key = spr_dict[key].SPR
 296         key = special_sprs.get(key, key)
 297         if key == 'HSRR0':  # HACK!
 298             key = 'SRR0'
 299         if key == 'HSRR1':  # HACK!
 300             key = 'SRR1'
 301         if key in self:
 302             res = dict.__getitem__(self, key)
 303         else:
 304             if isinstance(key, int):
 305                 info = spr_dict[key]
 306             else:
 307                 info = spr_byname[key]
 308             dict.__setitem__(self, key, SelectableInt(0, info.length))
 309             res = dict.__getitem__(self, key)
 310         print("spr returning", key, res)
 311         return res
 312
 313     def __setitem__(self, key, value):
 314         if isinstance(key, SelectableInt):
 315             key = key.value
 316         if isinstance(key, int):
 317             key = spr_dict[key].SPR
 318             print("spr key", key)
 319         key = special_sprs.get(key, key)
 320         if key == 'HSRR0':  # HACK!
 321             self.__setitem__('SRR0', value)
 322         if key == 'HSRR1':  # HACK!
 323             self.__setitem__('SRR1', value)
 324         print("setting spr", key, value)
 325         dict.__setitem__(self, key, value)
 326
 327     def __call__(self, ridx):
 328         return self[ridx]
 329
 330 def get_pdecode_idx_in(dec2, name):
 331     op = dec2.dec.op
 332     in1_sel = yield op.in1_sel
 333     in2_sel = yield op.in2_sel
 334     in3_sel = yield op.in3_sel
 335     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
 336     in1 = yield dec2.e.read_reg1.data
 337     in2 = yield dec2.e.read_reg2.data
 338     in3 = yield dec2.e.read_reg3.data
 339     in1_isvec = yield dec2.in1_isvec
 340     in2_isvec = yield dec2.in2_isvec
 341     in3_isvec = yield dec2.in3_isvec
 342     print ("get_pdecode_idx", in1_sel, In1Sel.RA.value, in1, in1_isvec)
 343     # identify which regnames map to in1/2/3
 344     if name == 'RA':
 345         if (in1_sel == In1Sel.RA.value or
 346             (in1_sel == In1Sel.RA_OR_ZERO.value and in1 != 0)):
 347             return in1, in1_isvec
 348         if in1_sel == In1Sel.RA_OR_ZERO.value:
 349             return in1, in1_isvec
 350     elif name == 'RB':
 351         if in2_sel == In2Sel.RB.value:
 352             return in2, in2_isvec
 353         if in3_sel == In3Sel.RB.value:
 354             return in3, in3_isvec
 355     # XXX TODO, RC doesn't exist yet!
 356     elif name == 'RC':
 357         assert False, "RC does not exist yet"
 358     elif name == 'RS':
 359         if in1_sel == In1Sel.RS.value:
 360             return in1, in1_isvec
 361         if in2_sel == In2Sel.RS.value:
 362             return in2, in2_isvec
 363         if in3_sel == In3Sel.RS.value:
 364             return in3, in3_isvec
 365     return None, False
 366
 367
 368 def get_pdecode_cr_out(dec2, name):
 369     op = dec2.dec.op
 370     out_sel = yield op.cr_out
 371     out_bitfield = yield dec2.dec_cr_out.cr_bitfield.data
 372     sv_cr_out = yield op.sv_cr_out
 373     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
 374     out = yield dec2.e.write_cr.data
 375     o_isvec = yield dec2.o_isvec
 376     print ("get_pdecode_cr_out", out_sel, CROutSel.CR0.value, out, o_isvec)
 377     print ("    sv_cr_out", sv_cr_out)
 378     print ("    cr_bf", out_bitfield)
 379     # identify which regnames map to out / o2
 380     if name == 'CR0':
 381         if out_sel == CROutSel.CR0.value:
 382             return out, o_isvec
 383     print ("get_pdecode_idx_out not found", name)
 384     return None, False
 385
 386
 387 def get_pdecode_idx_out(dec2, name):
 388     op = dec2.dec.op
 389     out_sel = yield op.out_sel
 390     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
 391     out = yield dec2.e.write_reg.data
 392     o_isvec = yield dec2.o_isvec
 393     print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
 394     # identify which regnames map to out / o2
 395     if name == 'RA':
 396         if out_sel == OutSel.RA.value:
 397             return out, o_isvec
 398     elif name == 'RT':
 399         if out_sel == OutSel.RT.value:
 400             return out, o_isvec
 401     print ("get_pdecode_idx_out not found", name)
 402     return None, False
 403
 404
 405 # XXX TODO
 406 def get_pdecode_idx_out2(dec2, name):
 407     op = dec2.dec.op
 408     print ("TODO: get_pdecode_idx_out2", name)
 409     return None, False
 410
 411
 412 class ISACaller:
 413     # decoder2 - an instance of power_decoder2
 414     # regfile - a list of initial values for the registers
 415     # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
 416     # respect_pc - tracks the program counter.  requires initial_insns
 417     def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
 418                  initial_mem=None, initial_msr=0,
 419                  initial_svstate=0,
 420                  initial_insns=None, respect_pc=False,
 421                  disassembly=None,
 422                  initial_pc=0,
 423                  bigendian=False):
 424
 425         self.bigendian = bigendian
 426         self.halted = False
 427         self.is_svp64_mode = False
 428         self.respect_pc = respect_pc
 429         if initial_sprs is None:
 430             initial_sprs = {}
 431         if initial_mem is None:
 432             initial_mem = {}
 433         if initial_insns is None:
 434             initial_insns = {}
 435             assert self.respect_pc == False, "instructions required to honor pc"
 436
 437         print("ISACaller insns", respect_pc, initial_insns, disassembly)
 438         print("ISACaller initial_msr", initial_msr)
 439
 440         # "fake program counter" mode (for unit testing)
 441         self.fake_pc = 0
 442         disasm_start = 0
 443         if not respect_pc:
 444             if isinstance(initial_mem, tuple):
 445                 self.fake_pc = initial_mem[0]
 446                 disasm_start = self.fake_pc
 447         else:
 448             disasm_start = initial_pc
 449
 450         # disassembly: we need this for now (not given from the decoder)
 451         self.disassembly = {}
 452         if disassembly:
 453             for i, code in enumerate(disassembly):
 454                 self.disassembly[i*4 + disasm_start] = code
 455
 456         # set up registers, instruction memory, data memory, PC, SPRs, MSR
 457         self.svp64rm = SVP64RM()
 458         if isinstance(initial_svstate, int):
 459             initial_svstate = SVP64State(initial_svstate)
 460         self.svstate = initial_svstate
 461         self.gpr = GPR(decoder2, self, self.svstate, regfile)
 462         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
 463         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
 464         self.pc = PC()
 465         self.spr = SPR(decoder2, initial_sprs)
 466         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
 467
 468         # TODO, needed here:
 469         # FPR (same as GPR except for FP nums)
 470         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
 471         #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
 472         # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
 473         #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
 474         #         -- Done
 475         # 2.3.2 LR   (actually SPR #8) -- Done
 476         # 2.3.3 CTR  (actually SPR #9) -- Done
 477         # 2.3.4 TAR  (actually SPR #815)
 478         # 3.2.2 p45 XER  (actually SPR #1) -- Done
 479         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 480
 481         # create CR then allow portions of it to be "selectable" (below)
 482         #rev_cr = int('{:016b}'.format(initial_cr)[::-1], 2)
 483         self.cr = SelectableInt(initial_cr, 64)  # underlying reg
 484         #self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))
 485
 486         # "undefined", just set to variable-bit-width int (use exts "max")
 487         #self.undefined = SelectableInt(0, 256)  # TODO, not hard-code 256!
 488
 489         self.namespace = {}
 490         self.namespace.update(self.spr)
 491         self.namespace.update({'GPR': self.gpr,
 492                                'MEM': self.mem,
 493                                'SPR': self.spr,
 494                                'memassign': self.memassign,
 495                                'NIA': self.pc.NIA,
 496                                'CIA': self.pc.CIA,
 497                                'CR': self.cr,
 498                                'MSR': self.msr,
 499                                'undefined': undefined,
 500                                'mode_is_64bit': True,
 501                                'SO': XER_bits['SO']
 502                                })
 503
 504         # update pc to requested start point
 505         self.set_pc(initial_pc)
 506
 507         # field-selectable versions of Condition Register TODO check bitranges?
 508         self.crl = []
 509         for i in range(8):
 510             bits = tuple(range(i*4+32, (i+1)*4+32))  # errr... maybe?
 511             _cr = FieldSelectableInt(self.cr, bits)
 512             self.crl.append(_cr)
 513             self.namespace["CR%d" % i] = _cr
 514
 515         self.decoder = decoder2.dec
 516         self.dec2 = decoder2
 517
 518     def TRAP(self, trap_addr=0x700, trap_bit=PIb.TRAP):
 519         print("TRAP:", hex(trap_addr), hex(self.namespace['MSR'].value))
 520         # store CIA(+4?) in SRR0, set NIA to 0x700
 521         # store MSR in SRR1, set MSR to um errr something, have to check spec
 522         self.spr['SRR0'].value = self.pc.CIA.value
 523         self.spr['SRR1'].value = self.namespace['MSR'].value
 524         self.trap_nia = SelectableInt(trap_addr, 64)
 525         self.spr['SRR1'][trap_bit] = 1  # change *copy* of MSR in SRR1
 526
 527         # set exception bits.  TODO: this should, based on the address
 528         # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
 529         # bits appropriately.  however it turns out that *for now* in all
 530         # cases (all trap_addrs) the exact same thing is needed.
 531         self.msr[MSRb.IR] = 0
 532         self.msr[MSRb.DR] = 0
 533         self.msr[MSRb.FE0] = 0
 534         self.msr[MSRb.FE1] = 0
 535         self.msr[MSRb.EE] = 0
 536         self.msr[MSRb.RI] = 0
 537         self.msr[MSRb.SF] = 1
 538         self.msr[MSRb.TM] = 0
 539         self.msr[MSRb.VEC] = 0
 540         self.msr[MSRb.VSX] = 0
 541         self.msr[MSRb.PR] = 0
 542         self.msr[MSRb.FP] = 0
 543         self.msr[MSRb.PMM] = 0
 544         self.msr[MSRb.TEs] = 0
 545         self.msr[MSRb.TEe] = 0
 546         self.msr[MSRb.UND] = 0
 547         self.msr[MSRb.LE] = 1
 548
 549     def memassign(self, ea, sz, val):
 550         self.mem.memassign(ea, sz, val)
 551
 552     def prep_namespace(self, formname, op_fields):
 553         # TODO: get field names from form in decoder*1* (not decoder2)
 554         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 555         # from spec
 556         # then "yield" fields only from op_fields rather than hard-coded
 557         # list, here.
 558         fields = self.decoder.sigforms[formname]
 559         for name in op_fields:
 560             if name == 'spr':
 561                 sig = getattr(fields, name.upper())
 562             else:
 563                 sig = getattr(fields, name)
 564             val = yield sig
 565             # these are all opcode fields involved in index-selection of CR,
 566             # and need to do "standard" arithmetic.  CR[BA+32] for example
 567             # would, if using SelectableInt, only be 5-bit.
 568             if name in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT', 'BI']:
 569                 self.namespace[name] = val
 570             else:
 571                 self.namespace[name] = SelectableInt(val, sig.width)
 572
 573         self.namespace['XER'] = self.spr['XER']
 574         self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
 575         self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
 576
 577     def handle_carry_(self, inputs, outputs, already_done):
 578         inv_a = yield self.dec2.e.do.invert_in
 579         if inv_a:
 580             inputs[0] = ~inputs[0]
 581
 582         imm_ok = yield self.dec2.e.do.imm_data.ok
 583         if imm_ok:
 584             imm = yield self.dec2.e.do.imm_data.data
 585             inputs.append(SelectableInt(imm, 64))
 586         assert len(outputs) >= 1
 587         print("outputs", repr(outputs))
 588         if isinstance(outputs, list) or isinstance(outputs, tuple):
 589             output = outputs[0]
 590         else:
 591             output = outputs
 592         gts = []
 593         for x in inputs:
 594             print("gt input", x, output)
 595             gt = (gtu(x, output))
 596             gts.append(gt)
 597         print(gts)
 598         cy = 1 if any(gts) else 0
 599         print("CA", cy, gts)
 600         if not (1 & already_done):
 601             self.spr['XER'][XER_bits['CA']] = cy
 602
 603         print("inputs", already_done, inputs)
 604         # 32 bit carry
 605         # ARGH... different for OP_ADD... *sigh*...
 606         op = yield self.dec2.e.do.insn_type
 607         if op == MicrOp.OP_ADD.value:
 608             res32 = (output.value & (1 << 32)) != 0
 609             a32 = (inputs[0].value & (1 << 32)) != 0
 610             if len(inputs) >= 2:
 611                 b32 = (inputs[1].value & (1 << 32)) != 0
 612             else:
 613                 b32 = False
 614             cy32 = res32 ^ a32 ^ b32
 615             print("CA32 ADD", cy32)
 616         else:
 617             gts = []
 618             for x in inputs:
 619                 print("input", x, output)
 620                 print("     x[32:64]", x, x[32:64])
 621                 print("     o[32:64]", output, output[32:64])
 622                 gt = (gtu(x[32:64], output[32:64])) == SelectableInt(1, 1)
 623                 gts.append(gt)
 624             cy32 = 1 if any(gts) else 0
 625             print("CA32", cy32, gts)
 626         if not (2 & already_done):
 627             self.spr['XER'][XER_bits['CA32']] = cy32
 628
 629     def handle_overflow(self, inputs, outputs, div_overflow):
 630         if hasattr(self.dec2.e.do, "invert_in"):
 631             inv_a = yield self.dec2.e.do.invert_in
 632             if inv_a:
 633                 inputs[0] = ~inputs[0]
 634
 635         imm_ok = yield self.dec2.e.do.imm_data.ok
 636         if imm_ok:
 637             imm = yield self.dec2.e.do.imm_data.data
 638             inputs.append(SelectableInt(imm, 64))
 639         assert len(outputs) >= 1
 640         print("handle_overflow", inputs, outputs, div_overflow)
 641         if len(inputs) < 2 and div_overflow is None:
 642             return
 643
 644         # div overflow is different: it's returned by the pseudo-code
 645         # because it's more complex than can be done by analysing the output
 646         if div_overflow is not None:
 647             ov, ov32 = div_overflow, div_overflow
 648         # arithmetic overflow can be done by analysing the input and output
 649         elif len(inputs) >= 2:
 650             output = outputs[0]
 651
 652             # OV (64-bit)
 653             input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
 654             output_sgn = exts(output.value, output.bits) < 0
 655             ov = 1 if input_sgn[0] == input_sgn[1] and \
 656                 output_sgn != input_sgn[0] else 0
 657
 658             # OV (32-bit)
 659             input32_sgn = [exts(x.value, 32) < 0 for x in inputs]
 660             output32_sgn = exts(output.value, 32) < 0
 661             ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \
 662                 output32_sgn != input32_sgn[0] else 0
 663
 664         self.spr['XER'][XER_bits['OV']] = ov
 665         self.spr['XER'][XER_bits['OV32']] = ov32
 666         so = self.spr['XER'][XER_bits['SO']]
 667         so = so | ov
 668         self.spr['XER'][XER_bits['SO']] = so
 669
 670     def handle_comparison(self, outputs, cr_idx=0):
 671         out = outputs[0]
 672         assert isinstance(out, SelectableInt), \
 673             "out zero not a SelectableInt %s" % repr(outputs)
 674         print("handle_comparison", out.bits, hex(out.value))
 675         # TODO - XXX *processor* in 32-bit mode
 676         # https://bugs.libre-soc.org/show_bug.cgi?id=424
 677         # if is_32bit:
 678         #    o32 = exts(out.value, 32)
 679         #    print ("handle_comparison exts 32 bit", hex(o32))
 680         out = exts(out.value, out.bits)
 681         print("handle_comparison exts", hex(out))
 682         zero = SelectableInt(out == 0, 1)
 683         positive = SelectableInt(out > 0, 1)
 684         negative = SelectableInt(out < 0, 1)
 685         SO = self.spr['XER'][XER_bits['SO']]
 686         print("handle_comparison SO", SO)
 687         cr_field = selectconcat(negative, positive, zero, SO)
 688         self.crl[cr_idx].eq(cr_field)
 689
 690     def set_pc(self, pc_val):
 691         self.namespace['NIA'] = SelectableInt(pc_val, 64)
 692         self.pc.update(self.namespace, self.is_svp64_mode)
 693
 694     def setup_one(self):
 695         """set up one instruction
 696         """
 697         if self.respect_pc:
 698             pc = self.pc.CIA.value
 699         else:
 700             pc = self.fake_pc
 701         self._pc = pc
 702         ins = self.imem.ld(pc, 4, False, True)
 703         if ins is None:
 704             raise KeyError("no instruction at 0x%x" % pc)
 705         print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
 706         print("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
 707
 708         yield self.dec2.sv_rm.eq(0)
 709         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
 710         yield self.dec2.dec.bigendian.eq(self.bigendian)
 711         yield self.dec2.state.msr.eq(self.msr.value)
 712         yield self.dec2.state.pc.eq(pc)
 713         yield self.dec2.state.svstate.eq(self.svstate.spr.value)
 714
 715         # SVP64.  first, check if the opcode is EXT001, and SVP64 id bits set
 716         yield Settle()
 717         opcode = yield self.dec2.dec.opcode_in
 718         pfx = SVP64PrefixFields() # TODO should probably use SVP64PrefixDecoder
 719         pfx.insn.value = opcode
 720         major = pfx.major.asint(msb0=True) # MSB0 inversion
 721         print ("prefix test: opcode:", major, bin(major),
 722                 pfx.insn[7] == 0b1, pfx.insn[9] == 0b1)
 723         self.is_svp64_mode = ((major == 0b000001) and
 724                               pfx.insn[7].value == 0b1 and
 725                               pfx.insn[9].value == 0b1)
 726         self.pc.update_nia(self.is_svp64_mode)
 727         if not self.is_svp64_mode:
 728             return
 729
 730         # in SVP64 mode.  decode/print out svp64 prefix, get v3.0B instruction
 731         print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
 732         print ("    svstate.vl", self.svstate.vl.asint(msb0=True))
 733         print ("    svstate.mvl", self.svstate.maxvl.asint(msb0=True))
 734         sv_rm = pfx.rm.asint(msb0=True)
 735         ins = self.imem.ld(pc+4, 4, False, True)
 736         print("     svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
 737         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix
 738         yield self.dec2.sv_rm.eq(sv_rm)                        # svp64 prefix
 739         yield Settle()
 740
 741     def execute_one(self):
 742         """execute one instruction
 743         """
 744         # get the disassembly code for this instruction
 745         if self.is_svp64_mode:
 746             code = self.disassembly[self._pc+4]
 747             print("    svp64 sim-execute", hex(self._pc), code)
 748         else:
 749             code = self.disassembly[self._pc]
 750             print("sim-execute", hex(self._pc), code)
 751         opname = code.split(' ')[0]
 752         yield from self.call(opname)
 753
 754         # don't use this except in special circumstances
 755         if not self.respect_pc:
 756             self.fake_pc += 4
 757
 758         print("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value)
 759
 760     def get_assembly_name(self):
 761         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 762         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 763         dec_insn = yield self.dec2.e.do.insn
 764         asmcode = yield self.dec2.dec.op.asmcode
 765         print("get assembly name asmcode", asmcode, hex(dec_insn))
 766         asmop = insns.get(asmcode, None)
 767         int_op = yield self.dec2.dec.op.internal_op
 768
 769         # sigh reconstruct the assembly instruction name
 770         if hasattr(self.dec2.e.do, "oe"):
 771             ov_en = yield self.dec2.e.do.oe.oe
 772             ov_ok = yield self.dec2.e.do.oe.ok
 773         else:
 774             ov_en = False
 775             ov_ok = False
 776         if hasattr(self.dec2.e.do, "rc"):
 777             rc_en = yield self.dec2.e.do.rc.rc
 778             rc_ok = yield self.dec2.e.do.rc.ok
 779         else:
 780             rc_en = False
 781             rc_ok = False
 782         # grrrr have to special-case MUL op (see DecodeOE)
 783         print("ov %d en %d rc %d en %d op %d" %
 784               (ov_ok, ov_en, rc_ok, rc_en, int_op))
 785         if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]:
 786             print("mul op")
 787             if rc_en & rc_ok:
 788                 asmop += "."
 789         else:
 790             if not asmop.endswith("."):  # don't add "." to "andis."
 791                 if rc_en & rc_ok:
 792                     asmop += "."
 793         if hasattr(self.dec2.e.do, "lk"):
 794             lk = yield self.dec2.e.do.lk
 795             if lk:
 796                 asmop += "l"
 797         print("int_op", int_op)
 798         if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]:
 799             AA = yield self.dec2.dec.fields.FormI.AA[0:-1]
 800             print("AA", AA)
 801             if AA:
 802                 asmop += "a"
 803         spr_msb = yield from self.get_spr_msb()
 804         if int_op == MicrOp.OP_MFCR.value:
 805             if spr_msb:
 806                 asmop = 'mfocrf'
 807             else:
 808                 asmop = 'mfcr'
 809         # XXX TODO: for whatever weird reason this doesn't work
 810         # https://bugs.libre-soc.org/show_bug.cgi?id=390
 811         if int_op == MicrOp.OP_MTCRF.value:
 812             if spr_msb:
 813                 asmop = 'mtocrf'
 814             else:
 815                 asmop = 'mtcrf'
 816         return asmop
 817
 818     def get_spr_msb(self):
 819         dec_insn = yield self.dec2.e.do.insn
 820         return dec_insn & (1 << 20) != 0  # sigh - XFF.spr[-1]?
 821
 822     def call(self, name):
 823         """call(opcode) - the primary execution point for instructions
 824         """
 825         name = name.strip()  # remove spaces if not already done so
 826         if self.halted:
 827             print("halted - not executing", name)
 828             return
 829
 830         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 831         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 832         asmop = yield from self.get_assembly_name()
 833         print("call", name, asmop)
 834
 835         # check privileged
 836         int_op = yield self.dec2.dec.op.internal_op
 837         spr_msb = yield from self.get_spr_msb()
 838
 839         instr_is_privileged = False
 840         if int_op in [MicrOp.OP_ATTN.value,
 841                       MicrOp.OP_MFMSR.value,
 842                       MicrOp.OP_MTMSR.value,
 843                       MicrOp.OP_MTMSRD.value,
 844                       # TODO: OP_TLBIE
 845                       MicrOp.OP_RFID.value]:
 846             instr_is_privileged = True
 847         if int_op in [MicrOp.OP_MFSPR.value,
 848                       MicrOp.OP_MTSPR.value] and spr_msb:
 849             instr_is_privileged = True
 850
 851         print("is priv", instr_is_privileged, hex(self.msr.value),
 852               self.msr[MSRb.PR])
 853         # check MSR priv bit and whether op is privileged: if so, throw trap
 854         if instr_is_privileged and self.msr[MSRb.PR] == 1:
 855             self.TRAP(0x700, PIb.PRIV)
 856             self.namespace['NIA'] = self.trap_nia
 857             self.pc.update(self.namespace, self.is_svp64_mode)
 858             return
 859
 860         # check halted condition
 861         if name == 'attn':
 862             self.halted = True
 863             return
 864
 865         # check illegal instruction
 866         illegal = False
 867         if name not in ['mtcrf', 'mtocrf']:
 868             illegal = name != asmop
 869
 870         if illegal:
 871             print("illegal", name, asmop)
 872             self.TRAP(0x700, PIb.ILLEG)
 873             self.namespace['NIA'] = self.trap_nia
 874             self.pc.update(self.namespace, self.is_svp64_mode)
 875             print("name %s != %s - calling ILLEGAL trap, PC: %x" %
 876                   (name, asmop, self.pc.CIA.value))
 877             return
 878
 879         info = self.instrs[name]
 880         yield from self.prep_namespace(info.form, info.op_fields)
 881
 882         # preserve order of register names
 883         input_names = create_args(list(info.read_regs) +
 884                                   list(info.uninit_regs))
 885         print(input_names)
 886
 887         # get SVP64 entry for the current instruction
 888         sv_rm = self.svp64rm.instrs.get(name)
 889         if sv_rm is not None:
 890             dest_cr, src_cr, src_byname, dest_byname = decode_extra(sv_rm)
 891         else:
 892             dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
 893         print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
 894
 895         # get SVSTATE srcstep.  TODO: dststep (twin predication)
 896         srcstep = self.svstate.srcstep.asint(msb0=True)
 897         vl = self.svstate.vl.asint(msb0=True)
 898         mvl = self.svstate.maxvl.asint(msb0=True)
 899
 900         # VL=0 in SVP64 mode means "do nothing: skip instruction"
 901         if self.is_svp64_mode and vl == 0:
 902             self.pc.update(self.namespace, self.is_svp64_mode)
 903             print("end of call", self.namespace['CIA'], self.namespace['NIA'])
 904             return
 905
 906         # main input registers (RT, RA ...)
 907         inputs = []
 908         for name in input_names:
 909             # using PowerDecoder2, first, find the decoder index.
 910             # (mapping name RA RB RC RS to in1, in2, in3)
 911             regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)
 912             if regnum is None:
 913                 # doing this is not part of svp64, it's because output
 914                 # registers, to be modified, need to be in the namespace.
 915                 regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
 916             # here's where we go "vector".  TODO: zero-testing (RA_IS_ZERO)
 917             # XXX already done by PowerDecoder2, now
 918             #if is_vec:
 919             #   regnum += srcstep # TODO, elwidth overrides
 920
 921             # in case getting the register number is needed, _RA, _RB
 922             regname = "_" + name
 923             self.namespace[regname] = regnum
 924             print('reading reg %s %d' % (name, regnum), is_vec)
 925             reg_val = self.gpr(regnum)
 926             inputs.append(reg_val)
 927
 928         # "special" registers
 929         for special in info.special_regs:
 930             if special in special_sprs:
 931                 inputs.append(self.spr[special])
 932             else:
 933                 inputs.append(self.namespace[special])
 934
 935         # clear trap (trap) NIA
 936         self.trap_nia = None
 937
 938         print(inputs)
 939         results = info.func(self, *inputs)
 940         print(results)
 941
 942         # "inject" decorator takes namespace from function locals: we need to
 943         # overwrite NIA being overwritten (sigh)
 944         if self.trap_nia is not None:
 945             self.namespace['NIA'] = self.trap_nia
 946
 947         print("after func", self.namespace['CIA'], self.namespace['NIA'])
 948
 949         # detect if CA/CA32 already in outputs (sra*, basically)
 950         already_done = 0
 951         if info.write_regs:
 952             output_names = create_args(info.write_regs)
 953             for name in output_names:
 954                 if name == 'CA':
 955                     already_done |= 1
 956                 if name == 'CA32':
 957                     already_done |= 2
 958
 959         print("carry already done?", bin(already_done))
 960         if hasattr(self.dec2.e.do, "output_carry"):
 961             carry_en = yield self.dec2.e.do.output_carry
 962         else:
 963             carry_en = False
 964         if carry_en:
 965             yield from self.handle_carry_(inputs, results, already_done)
 966
 967         # detect if overflow was in return result
 968         overflow = None
 969         if info.write_regs:
 970             for name, output in zip(output_names, results):
 971                 if name == 'overflow':
 972                     overflow = output
 973
 974         if hasattr(self.dec2.e.do, "oe"):
 975             ov_en = yield self.dec2.e.do.oe.oe
 976             ov_ok = yield self.dec2.e.do.oe.ok
 977         else:
 978             ov_en = False
 979             ov_ok = False
 980         print("internal overflow", overflow, ov_en, ov_ok)
 981         if ov_en & ov_ok:
 982             yield from self.handle_overflow(inputs, results, overflow)
 983
 984         if hasattr(self.dec2.e.do, "rc"):
 985             rc_en = yield self.dec2.e.do.rc.rc
 986         else:
 987             rc_en = False
 988         if rc_en:
 989             regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
 990             regnum = 0 # TODO fix
 991             self.handle_comparison(results, regnum)
 992
 993         # svp64 loop can end early if the dest is scalar
 994         svp64_dest_vector = False
 995
 996         # any modified return results?
 997         if info.write_regs:
 998             for name, output in zip(output_names, results):
 999                 if name == 'overflow':  # ignore, done already (above)
1000                     continue
1001                 if isinstance(output, int):
1002                     output = SelectableInt(output, 256)
1003                 if name in ['CA', 'CA32']:
1004                     if carry_en:
1005                         print("writing %s to XER" % name, output)
1006                         self.spr['XER'][XER_bits[name]] = output.value
1007                     else:
1008                         print("NOT writing %s to XER" % name, output)
1009                 elif name in info.special_regs:
1010                     print('writing special %s' % name, output, special_sprs)
1011                     if name in special_sprs:
1012                         self.spr[name] = output
1013                     else:
1014                         self.namespace[name].eq(output)
1015                     if name == 'MSR':
1016                         print('msr written', hex(self.msr.value))
1017                 else:
1018                     regnum, is_vec = yield from get_pdecode_idx_out(self.dec2,
1019                                                 name)
1020                     if regnum is None:
1021                         # temporary hack for not having 2nd output
1022                         regnum = yield getattr(self.decoder, name)
1023                         is_vec = False
1024                     # here's where we go "vector".
1025                     if is_vec:
1026                         # XXX already done by PowerDecoder2
1027                         # regnum += srcstep # TODO, elwidth overrides
1028                         svp64_dest_vector = True
1029                     print('writing reg %d %s' % (regnum, str(output)), is_vec)
1030                     if output.bits > 64:
1031                         output = SelectableInt(output.value, 64)
1032                     self.gpr[regnum] = output
1033
1034         # check if it is the SVSTATE.src/dest step that needs incrementing
1035         # this is our Sub-Program-Counter loop from 0 to VL-1
1036         if self.is_svp64_mode:
1037             # XXX twin predication TODO
1038             vl = self.svstate.vl.asint(msb0=True)
1039             mvl = self.svstate.maxvl.asint(msb0=True)
1040             srcstep = self.svstate.srcstep.asint(msb0=True)
1041             print ("    svstate.vl", vl)
1042             print ("    svstate.mvl", mvl)
1043             print ("    svstate.srcstep", srcstep)
1044             # check if srcstep needs incrementing by one, stop PC advancing
1045             if svp64_dest_vector and srcstep != vl-1:
1046                 self.svstate.srcstep += SelectableInt(1, 7)
1047                 self.pc.NIA.value = self.pc.CIA.value
1048                 self.namespace['NIA'] = self.pc.NIA
1049                 print("end of sub-pc call", self.namespace['CIA'],
1050                                      self.namespace['NIA'])
1051                 return # DO NOT allow PC to update whilst Sub-PC loop running
1052             # reset to zero
1053             self.svstate.srcstep[0:7] = 0
1054             print ("    svstate.srcstep loop end (PC to update)")
1055             self.pc.update_nia(self.is_svp64_mode)
1056             self.namespace['NIA'] = self.pc.NIA
1057
1058         # UPDATE program counter
1059         self.pc.update(self.namespace, self.is_svp64_mode)
1060         print("end of call", self.namespace['CIA'], self.namespace['NIA'])
1061
1062
1063 def inject():
1064     """Decorator factory.
1065
1066     this decorator will "inject" variables into the function's namespace,
1067     from the *dictionary* in self.namespace.  it therefore becomes possible
1068     to make it look like a whole stack of variables which would otherwise
1069     need "self." inserted in front of them (*and* for those variables to be
1070     added to the instance) "appear" in the function.
1071
1072     "self.namespace['SI']" for example becomes accessible as just "SI" but
1073     *only* inside the function, when decorated.
1074     """
1075     def variable_injector(func):
1076         @wraps(func)
1077         def decorator(*args, **kwargs):
1078             try:
1079                 func_globals = func.__globals__  # Python 2.6+
1080             except AttributeError:
1081                 func_globals = func.func_globals  # Earlier versions.
1082
1083             context = args[0].namespace  # variables to be injected
1084             saved_values = func_globals.copy()  # Shallow copy of dict.
1085             func_globals.update(context)
1086             result = func(*args, **kwargs)
1087             print("globals after", func_globals['CIA'], func_globals['NIA'])
1088             print("args[0]", args[0].namespace['CIA'],
1089                   args[0].namespace['NIA'])
1090             args[0].namespace = func_globals
1091             #exec (func.__code__, func_globals)
1092
1093             # finally:
1094             #    func_globals = saved_values  # Undo changes.
1095
1096             return result
1097
1098         return decorator
1099
1100     return variable_injector