1 """core of the python-based POWER9 simulator
3 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
4 not speed, it is for both learning and educational purposes, as well as
5 a method of verifying the HDL.
8 from functools
import wraps
9 from soc
.decoder
.orderedset
import OrderedSet
10 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
12 from soc
.decoder
.power_enums
import (spr_dict
, spr_byname
, XER_bits
,
14 from soc
.decoder
.helpers
import exts
, trunc_div
, trunc_rem
15 from collections
import namedtuple
19 instruction_info
= namedtuple('instruction_info',
20 'func read_regs uninit_regs write_regs ' + \
21 'special_regs op_fields form asmregs')
31 def swap_order(x
, nbytes
):
32 x
= x
.to_bytes(nbytes
, byteorder
='little')
33 x
= int.from_bytes(x
, byteorder
='big', signed
=False)
37 def create_args(reglist
, extra
=None):
49 def __init__(self
, row_bytes
=8, initial_mem
=None):
51 self
.bytes_per_word
= row_bytes
52 self
.word_log2
= math
.ceil(math
.log2(row_bytes
))
53 print ("Sim-Mem", initial_mem
, self
.bytes_per_word
, self
.word_log2
)
57 # different types of memory data structures recognised (for convenience)
58 if isinstance(initial_mem
, list):
59 initial_mem
= (0, initial_mem
)
60 if isinstance(initial_mem
, tuple):
61 startaddr
, mem
= initial_mem
63 for i
, val
in enumerate(mem
):
64 initial_mem
[startaddr
+ row_bytes
*i
] = (val
, row_bytes
)
66 for addr
, (val
, width
) in initial_mem
.items():
67 #val = swap_order(val, width)
68 self
.st(addr
, val
, width
, swap
=False)
70 def _get_shifter_mask(self
, wid
, remainder
):
71 shifter
= ((self
.bytes_per_word
- wid
) - remainder
) * \
73 # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
75 shifter
= remainder
* 8
76 mask
= (1 << (wid
* 8)) - 1
77 print ("width,rem,shift,mask", wid
, remainder
, hex(shifter
), hex(mask
))
80 # TODO: Implement ld/st of lesser width
81 def ld(self
, address
, width
=8, swap
=True, check_in_mem
=False):
82 print("ld from addr 0x{:x} width {:d}".format(address
, width
))
83 remainder
= address
& (self
.bytes_per_word
- 1)
84 address
= address
>> self
.word_log2
85 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
86 if address
in self
.mem
:
87 val
= self
.mem
[address
]
92 print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address
, remainder
, val
))
94 if width
!= self
.bytes_per_word
:
95 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
96 print ("masking", hex(val
), hex(mask
<<shifter
), shifter
)
97 val
= val
& (mask
<< shifter
)
100 val
= swap_order(val
, width
)
101 print("Read 0x{:x} from addr 0x{:x}".format(val
, address
))
104 def st(self
, addr
, v
, width
=8, swap
=True):
106 remainder
= addr
& (self
.bytes_per_word
- 1)
107 addr
= addr
>> self
.word_log2
108 print("Writing 0x{:x} to ST 0x{:x} memaddr 0x{:x}/{:x}".format(v
,
109 staddr
, addr
, remainder
, swap
))
110 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
112 v
= swap_order(v
, width
)
113 if width
!= self
.bytes_per_word
:
118 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
119 val
&= ~
(mask
<< shifter
)
124 print("mem @ 0x{:x}: 0x{:x}".format(addr
, self
.mem
[addr
]))
126 def __call__(self
, addr
, sz
):
127 val
= self
.ld(addr
.value
, sz
)
128 print ("memread", addr
, sz
, val
)
129 return SelectableInt(val
, sz
*8)
131 def memassign(self
, addr
, sz
, val
):
132 print ("memassign", addr
, sz
, val
)
133 self
.st(addr
.value
, val
.value
, sz
)
137 def __init__(self
, decoder
, regfile
):
141 self
[i
] = SelectableInt(regfile
[i
], 64)
143 def __call__(self
, ridx
):
146 def set_form(self
, form
):
149 def getz(self
, rnum
):
150 #rnum = rnum.value # only SelectableInt allowed
151 print("GPR getzero", rnum
)
153 return SelectableInt(0, 64)
156 def _get_regnum(self
, attr
):
157 getform
= self
.sd
.sigforms
[self
.form
]
158 rnum
= getattr(getform
, attr
)
161 def ___getitem__(self
, attr
):
162 print("GPR getitem", attr
)
163 rnum
= self
._get
_regnum
(attr
)
164 return self
.regfile
[rnum
]
167 for i
in range(0, len(self
), 8):
170 s
.append("%08x" % self
[i
+j
].value
)
172 print("reg", "%2d" % i
, s
)
175 def __init__(self
, pc_init
=0):
176 self
.CIA
= SelectableInt(pc_init
, 64)
177 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
179 def update(self
, namespace
):
180 self
.CIA
= namespace
['NIA'].narrow(64)
181 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
182 namespace
['CIA'] = self
.CIA
183 namespace
['NIA'] = self
.NIA
187 def __init__(self
, dec2
, initial_sprs
={}):
190 for key
, v
in initial_sprs
.items():
191 if isinstance(key
, SelectableInt
):
193 key
= special_sprs
.get(key
, key
)
194 if isinstance(key
, int):
197 info
= spr_byname
[key
]
198 if not isinstance(v
, SelectableInt
):
199 v
= SelectableInt(v
, info
.length
)
202 def __getitem__(self
, key
):
203 # if key in special_sprs get the special spr, otherwise return key
204 if isinstance(key
, SelectableInt
):
206 key
= special_sprs
.get(key
, key
)
208 return dict.__getitem
__(self
, key
)
211 dict.__setitem
__(self
, key
, SelectableInt(0, info
.length
))
212 return dict.__getitem
__(self
, key
)
214 def __setitem__(self
, key
, value
):
215 if isinstance(key
, SelectableInt
):
217 key
= special_sprs
.get(key
, key
)
218 dict.__setitem
__(self
, key
, value
)
220 def __call__(self
, ridx
):
225 # decoder2 - an instance of power_decoder2
226 # regfile - a list of initial values for the registers
227 # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
228 # respect_pc - tracks the program counter. requires initial_insns
229 def __init__(self
, decoder2
, regfile
, initial_sprs
=None, initial_cr
=0,
230 initial_mem
=None, initial_msr
=0,
231 initial_insns
=None, respect_pc
=False,
234 self
.respect_pc
= respect_pc
235 if initial_sprs
is None:
237 if initial_mem
is None:
239 if initial_insns
is None:
241 assert self
.respect_pc
== False, "instructions required to honor pc"
243 print ("ISACaller insns", respect_pc
, initial_insns
, disassembly
)
245 # "fake program counter" mode (for unit testing)
248 if isinstance(initial_mem
, tuple):
249 self
.fake_pc
= initial_mem
[0]
251 # disassembly: we need this for now (not given from the decoder)
252 self
.disassembly
= {}
254 for i
, code
in enumerate(disassembly
):
255 self
.disassembly
[i
*4 + self
.fake_pc
] = code
257 # set up registers, instruction memory, data memory, PC, SPRs, MSR
258 self
.gpr
= GPR(decoder2
, regfile
)
259 self
.mem
= Mem(row_bytes
=8, initial_mem
=initial_mem
)
260 self
.imem
= Mem(row_bytes
=4, initial_mem
=initial_insns
)
262 self
.spr
= SPR(decoder2
, initial_sprs
)
263 self
.msr
= SelectableInt(initial_msr
, 64) # underlying reg
266 # FPR (same as GPR except for FP nums)
267 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
268 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
269 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
270 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
272 # 2.3.2 LR (actually SPR #8) -- Done
273 # 2.3.3 CTR (actually SPR #9) -- Done
274 # 2.3.4 TAR (actually SPR #815)
275 # 3.2.2 p45 XER (actually SPR #1) -- Done
276 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
278 # create CR then allow portions of it to be "selectable" (below)
279 self
._cr
= SelectableInt(initial_cr
, 64) # underlying reg
280 self
.cr
= FieldSelectableInt(self
._cr
, list(range(32,64)))
282 # "undefined", just set to variable-bit-width int (use exts "max")
283 self
.undefined
= SelectableInt(0, 256) # TODO, not hard-code 256!
286 self
.namespace
.update(self
.spr
)
287 self
.namespace
.update({'GPR': self
.gpr
,
290 'memassign': self
.memassign
,
295 'undefined': self
.undefined
,
296 'mode_is_64bit': True,
301 # field-selectable versions of Condition Register TODO check bitranges?
304 bits
= tuple(range(i
*4, (i
+1)*4))# errr... maybe?
305 _cr
= FieldSelectableInt(self
.cr
, bits
)
307 self
.namespace
["CR%d" % i
] = _cr
309 self
.decoder
= decoder2
.dec
312 def TRAP(self
, trap_addr
=0x700):
314 #self.namespace['NIA'] = trap_addr
315 #self.SRR0 = self.namespace['CIA'] + 4
316 #self.SRR1 = self.namespace['MSR']
317 #self.namespace['MSR'][45] = 1
318 # store CIA(+4?) in SRR0, set NIA to 0x700
319 # store MSR in SRR1, set MSR to um errr something, have to check spec
321 def memassign(self
, ea
, sz
, val
):
322 self
.mem
.memassign(ea
, sz
, val
)
324 def prep_namespace(self
, formname
, op_fields
):
325 # TODO: get field names from form in decoder*1* (not decoder2)
326 # decoder2 is hand-created, and decoder1.sigform is auto-generated
328 # then "yield" fields only from op_fields rather than hard-coded
330 fields
= self
.decoder
.sigforms
[formname
]
331 for name
in op_fields
:
333 sig
= getattr(fields
, name
.upper())
335 sig
= getattr(fields
, name
)
337 if name
in ['BF', 'BFA']:
338 self
.namespace
[name
] = val
340 self
.namespace
[name
] = SelectableInt(val
, sig
.width
)
342 self
.namespace
['XER'] = self
.spr
['XER']
343 self
.namespace
['CA'] = self
.spr
['XER'][XER_bits
['CA']].value
344 self
.namespace
['CA32'] = self
.spr
['XER'][XER_bits
['CA32']].value
346 def handle_carry_(self
, inputs
, outputs
, already_done
):
347 inv_a
= yield self
.dec2
.e
.invert_a
349 inputs
[0] = ~inputs
[0]
351 imm_ok
= yield self
.dec2
.e
.imm_data
.ok
353 imm
= yield self
.dec2
.e
.imm_data
.data
354 inputs
.append(SelectableInt(imm
, 64))
355 assert len(outputs
) >= 1
356 print ("outputs", repr(outputs
))
357 if isinstance(outputs
, list) or isinstance(outputs
, tuple):
363 print ("gt input", x
, output
)
367 cy
= 1 if any(gts
) else 0
368 if not (1 & already_done
):
369 self
.spr
['XER'][XER_bits
['CA']] = cy
371 print ("inputs", inputs
)
375 print ("input", x
, output
)
376 gt
= (x
[32:64] > output
[32:64]) == SelectableInt(1, 1)
378 cy32
= 1 if any(gts
) else 0
379 if not (2 & already_done
):
380 self
.spr
['XER'][XER_bits
['CA32']] = cy32
382 def handle_overflow(self
, inputs
, outputs
, div_overflow
):
383 inv_a
= yield self
.dec2
.e
.invert_a
385 inputs
[0] = ~inputs
[0]
387 imm_ok
= yield self
.dec2
.e
.imm_data
.ok
389 imm
= yield self
.dec2
.e
.imm_data
.data
390 inputs
.append(SelectableInt(imm
, 64))
391 assert len(outputs
) >= 1
392 print ("handle_overflow", inputs
, outputs
, div_overflow
)
393 if len(inputs
) < 2 and div_overflow
!= 1:
396 # div overflow is different: it's returned by the pseudo-code
397 # because it's more complex than can be done by analysing the output
398 if div_overflow
== 1:
400 # arithmetic overflow can be done by analysing the input and output
401 elif len(inputs
) >= 2:
405 input_sgn
= [exts(x
.value
, x
.bits
) < 0 for x
in inputs
]
406 output_sgn
= exts(output
.value
, output
.bits
) < 0
407 ov
= 1 if input_sgn
[0] == input_sgn
[1] and \
408 output_sgn
!= input_sgn
[0] else 0
411 input32_sgn
= [exts(x
.value
, 32) < 0 for x
in inputs
]
412 output32_sgn
= exts(output
.value
, 32) < 0
413 ov32
= 1 if input32_sgn
[0] == input32_sgn
[1] and \
414 output32_sgn
!= input32_sgn
[0] else 0
416 self
.spr
['XER'][XER_bits
['OV']] = ov
417 self
.spr
['XER'][XER_bits
['OV32']] = ov32
418 so
= self
.spr
['XER'][XER_bits
['SO']]
420 self
.spr
['XER'][XER_bits
['SO']] = so
422 def handle_comparison(self
, outputs
):
424 out
= exts(out
.value
, out
.bits
)
425 zero
= SelectableInt(out
== 0, 1)
426 positive
= SelectableInt(out
> 0, 1)
427 negative
= SelectableInt(out
< 0, 1)
428 SO
= self
.spr
['XER'][XER_bits
['SO']]
429 cr_field
= selectconcat(negative
, positive
, zero
, SO
)
430 self
.crl
[0].eq(cr_field
)
432 def set_pc(self
, pc_val
):
433 self
.namespace
['NIA'] = SelectableInt(pc_val
, 64)
434 self
.pc
.update(self
.namespace
)
437 """set up one instruction
440 pc
= self
.pc
.CIA
.value
444 ins
= self
.imem
.ld(pc
, 4, False, True)
446 raise KeyError("no instruction at 0x%x" % pc
)
447 print("setup: 0x%x 0x%x %s" % (pc
, ins
& 0xffffffff, bin(ins
)))
448 print ("NIA, CIA", self
.pc
.CIA
.value
, self
.pc
.NIA
.value
)
450 yield self
.dec2
.dec
.raw_opcode_in
.eq(ins
& 0xffffffff)
451 yield self
.dec2
.dec
.bigendian
.eq(0) # little / big?
453 def execute_one(self
):
454 """execute one instruction
456 # get the disassembly code for this instruction
457 code
= self
.disassembly
[self
._pc
]
458 print("sim-execute", hex(self
._pc
), code
)
459 opname
= code
.split(' ')[0]
460 yield from self
.call(opname
)
462 if not self
.respect_pc
:
464 print ("NIA, CIA", self
.pc
.CIA
.value
, self
.pc
.NIA
.value
)
466 def get_assembly_name(self
):
467 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
468 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
469 asmcode
= yield self
.dec2
.dec
.op
.asmcode
470 asmop
= insns
.get(asmcode
, None)
472 # sigh reconstruct the assembly instruction name
473 ov_en
= yield self
.dec2
.e
.oe
.oe
474 ov_ok
= yield self
.dec2
.e
.oe
.ok
477 lk
= yield self
.dec2
.e
.lk
480 int_op
= yield self
.dec2
.dec
.op
.internal_op
481 print ("int_op", int_op
)
482 if int_op
in [InternalOp
.OP_B
.value
, InternalOp
.OP_BC
.value
]:
483 AA
= yield self
.dec2
.dec
.fields
.FormI
.AA
[0:-1]
487 if int_op
== InternalOp
.OP_MFCR
.value
:
488 dec_insn
= yield self
.dec2
.e
.insn
489 if dec_insn
& (1<<20) != 0: # sigh
493 # XXX TODO: for whatever weird reason this doesn't work
494 # https://bugs.libre-soc.org/show_bug.cgi?id=390
495 if int_op
== InternalOp
.OP_MTCRF
.value
:
496 dec_insn
= yield self
.dec2
.e
.insn
497 if dec_insn
& (1<<20) != 0: # sigh
503 def call(self
, name
):
504 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
505 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
506 asmop
= yield from self
.get_assembly_name()
507 print ("call", name
, asmop
)
508 if name
not in ['mtcrf', 'mtocrf']:
509 assert name
== asmop
, "name %s != %s" % (name
, asmop
)
511 info
= self
.instrs
[name
]
512 yield from self
.prep_namespace(info
.form
, info
.op_fields
)
514 # preserve order of register names
515 input_names
= create_args(list(info
.read_regs
) + list(info
.uninit_regs
))
518 # main registers (RT, RA ...)
520 for name
in input_names
:
521 regnum
= yield getattr(self
.decoder
, name
)
523 self
.namespace
[regname
] = regnum
524 print('reading reg %d' % regnum
)
525 inputs
.append(self
.gpr(regnum
))
527 # "special" registers
528 for special
in info
.special_regs
:
529 if special
in special_sprs
:
530 inputs
.append(self
.spr
[special
])
532 inputs
.append(self
.namespace
[special
])
535 results
= info
.func(self
, *inputs
)
538 # detect if CA/CA32 already in outputs (sra*, basically)
541 output_names
= create_args(info
.write_regs
)
542 for name
in output_names
:
548 print ("carry already done?", bin(already_done
))
549 carry_en
= yield self
.dec2
.e
.output_carry
551 yield from self
.handle_carry_(inputs
, results
, already_done
)
553 # detect if overflow was in return result
556 for name
, output
in zip(output_names
, results
):
557 if name
== 'overflow':
560 ov_en
= yield self
.dec2
.e
.oe
.oe
561 ov_ok
= yield self
.dec2
.e
.oe
.ok
562 print ("internal overflow", overflow
)
564 yield from self
.handle_overflow(inputs
, results
, overflow
)
566 rc_en
= yield self
.dec2
.e
.rc
.data
568 self
.handle_comparison(results
)
570 # any modified return results?
572 for name
, output
in zip(output_names
, results
):
573 if name
== 'overflow': # ignore, done already (above)
575 if isinstance(output
, int):
576 output
= SelectableInt(output
, 256)
577 if name
in ['CA', 'CA32']:
579 print ("writing %s to XER" % name
, output
)
580 self
.spr
['XER'][XER_bits
[name
]] = output
.value
582 print ("NOT writing %s to XER" % name
, output
)
583 elif name
in info
.special_regs
:
584 print('writing special %s' % name
, output
, special_sprs
)
585 if name
in special_sprs
:
586 self
.spr
[name
] = output
588 self
.namespace
[name
].eq(output
)
590 print ('msr written', hex(self
.msr
.value
))
592 regnum
= yield getattr(self
.decoder
, name
)
593 print('writing reg %d %s' % (regnum
, str(output
)))
595 output
= SelectableInt(output
.value
, 64)
596 self
.gpr
[regnum
] = output
598 # update program counter
599 self
.pc
.update(self
.namespace
)
603 """Decorator factory.
605 this decorator will "inject" variables into the function's namespace,
606 from the *dictionary* in self.namespace. it therefore becomes possible
607 to make it look like a whole stack of variables which would otherwise
608 need "self." inserted in front of them (*and* for those variables to be
609 added to the instance) "appear" in the function.
611 "self.namespace['SI']" for example becomes accessible as just "SI" but
612 *only* inside the function, when decorated.
614 def variable_injector(func
):
616 def decorator(*args
, **kwargs
):
618 func_globals
= func
.__globals
__ # Python 2.6+
619 except AttributeError:
620 func_globals
= func
.func_globals
# Earlier versions.
622 context
= args
[0].namespace
# variables to be injected
623 saved_values
= func_globals
.copy() # Shallow copy of dict.
624 func_globals
.update(context
)
625 result
= func(*args
, **kwargs
)
626 args
[0].namespace
= func_globals
627 #exec (func.__code__, func_globals)
630 # func_globals = saved_values # Undo changes.
636 return variable_injector