src/soc/decoder/isa/caller.py

   1 from functools import wraps
   2 from soc.decoder.orderedset import OrderedSet
   3 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
   4                                         selectconcat)
   5 from collections import namedtuple
   6 import math
   7
   8 instruction_info = namedtuple('instruction_info',
   9                               'func read_regs uninit_regs write_regs ' + \
  10                               'special_regs op_fields form asmregs')
  11
  12
  13 def create_args(reglist, extra=None):
  14     args = OrderedSet()
  15     for reg in reglist:
  16         args.add(reg)
  17     args = list(args)
  18     if extra:
  19         args = [extra] + args
  20     return args
  21
  22
  23 class Mem:
  24
  25     def __init__(self, bytes_per_word=8):
  26         self.mem = {}
  27         self.bytes_per_word = bytes_per_word
  28         self.word_log2 = math.ceil(math.log2(bytes_per_word))
  29
  30     def _get_shifter_mask(self, width, remainder):
  31         shifter = ((self.bytes_per_word - width) - remainder) * \
  32             8  # bits per byte
  33         mask = (1 << (width * 8)) - 1
  34         return shifter, mask
  35
  36     # TODO: Implement ld/st of lesser width
  37     def ld(self, address, width=8):
  38         remainder = address & (self.bytes_per_word - 1)
  39         address = address >> self.word_log2
  40         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  41         if address in self.mem:
  42             val = self.mem[address]
  43         else:
  44             val = 0
  45
  46         if width != self.bytes_per_word:
  47             shifter, mask = self._get_shifter_mask(width, remainder)
  48             val = val & (mask << shifter)
  49             val >>= shifter
  50         print("Read {:x} from addr {:x}".format(val, address))
  51         return val
  52
  53     def st(self, address, value, width=8):
  54         remainder = address & (self.bytes_per_word - 1)
  55         address = address >> self.word_log2
  56         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  57         print("Writing {:x} to addr {:x}".format(value, address))
  58         if width != self.bytes_per_word:
  59             if address in self.mem:
  60                 val = self.mem[address]
  61             else:
  62                 val = 0
  63             shifter, mask = self._get_shifter_mask(width, remainder)
  64             val &= ~(mask << shifter)
  65             val |= value << shifter
  66             self.mem[address] = val
  67         else:
  68             self.mem[address] = value
  69
  70     def __call__(self, addr, sz):
  71         val = self.ld(addr.value, sz)
  72         print ("memread", addr, sz, val)
  73         return SelectableInt(val, sz*8)
  74
  75     def memassign(self, addr, sz, val):
  76         print ("memassign", addr, sz, val)
  77         self.st(addr.value, val.value, sz)
  78
  79
  80 class GPR(dict):
  81     def __init__(self, decoder, regfile):
  82         dict.__init__(self)
  83         self.sd = decoder
  84         for i in range(32):
  85             self[i] = SelectableInt(regfile[i], 64)
  86
  87     def __call__(self, ridx):
  88         return self[ridx]
  89
  90     def set_form(self, form):
  91         self.form = form
  92
  93     def getz(self, rnum):
  94         #rnum = rnum.value # only SelectableInt allowed
  95         print("GPR getzero", rnum)
  96         if rnum == 0:
  97             return SelectableInt(0, 64)
  98         return self[rnum]
  99
 100     def _get_regnum(self, attr):
 101         getform = self.sd.sigforms[self.form]
 102         rnum = getattr(getform, attr)
 103         return rnum
 104
 105     def ___getitem__(self, attr):
 106         print("GPR getitem", attr)
 107         rnum = self._get_regnum(attr)
 108         return self.regfile[rnum]
 109
 110     def dump(self):
 111         for i in range(0, len(self), 8):
 112             s = []
 113             for j in range(8):
 114                 s.append("%08x" % self[i+j].value)
 115             s = ' '.join(s)
 116             print("reg", "%2d" % i, s)
 117
 118 class PC:
 119     def __init__(self, pc_init=0):
 120         self.CIA = SelectableInt(pc_init, 64)
 121         self.NIA = self.CIA + SelectableInt(4, 64)
 122
 123     def update(self, namespace):
 124         self.CIA = self.NIA
 125         self.NIA = self.CIA + SelectableInt(4, 64)
 126         namespace['CIA'] = self.CIA
 127         namespace['NIA'] = self.NIA
 128
 129
 130 class ISACaller:
 131     # decoder2 - an instance of power_decoder2
 132     # regfile - a list of initial values for the registers
 133     def __init__(self, decoder2, regfile):
 134         self.gpr = GPR(decoder2, regfile)
 135         self.mem = Mem()
 136         self.pc = PC()
 137         # TODO, needed here:
 138         # 4.4.4 III p971 SPR (same as GPR except for SPRs - best done as a dict
 139         # FPR (same as GPR except for FP nums)
 140         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
 141         #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
 142         # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
 143         #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
 144         # 2.3.2 LR   (actually SPR #8)
 145         # 2.3.3 CTR  (actually SPR #9)
 146         # 2.3.4 TAR  (actually SPR #815)
 147         # 3.2.2 p45 XER  (actually SPR #0)
 148         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 149
 150         # create CR then allow portions of it to be "selectable" (below)
 151         self.cr = SelectableInt(0, 32)
 152
 153         self.namespace = {'GPR': self.gpr,
 154                           'MEM': self.mem,
 155                           'memassign': self.memassign,
 156                           'NIA': self.pc.NIA,
 157                           'CIA': self.pc.CIA,
 158                           'CR': self.cr,
 159                           }
 160
 161         # field-selectable versions of Condition Register TODO check bitranges?
 162         self.crl = []
 163         for i in range(8):
 164             bits = tuple(range(i*4, (i+1)*4))# errr... maybe?
 165             _cr = FieldSelectableInt(self.cr, bits)
 166             self.crl.append(_cr)
 167             self.namespace["CR%d" % i] = _cr
 168
 169         self.decoder = decoder2
 170
 171     def memassign(self, ea, sz, val):
 172         self.mem.memassign(ea, sz, val)
 173
 174     def prep_namespace(self, formname, op_fields):
 175         # TODO: get field names from form in decoder*1* (not decoder2)
 176         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 177         # from spec
 178         # then "yield" fields only from op_fields rather than hard-coded
 179         # list, here.
 180         fields = self.decoder.sigforms[formname]
 181         for name in op_fields:
 182             sig = getattr(fields, name)
 183             val = yield sig
 184             self.namespace[name] = SelectableInt(val, sig.width)
 185
 186     def call(self, name):
 187         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 188         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 189         info = self.instrs[name]
 190         yield from self.prep_namespace(info.form, info.op_fields)
 191
 192         input_names = create_args(info.read_regs | info.uninit_regs |
 193                                   info.special_regs)
 194         print(input_names)
 195
 196         inputs = []
 197         for name in input_names:
 198             regnum = yield getattr(self.decoder, name)
 199             regname = "_" + name
 200             self.namespace[regname] = regnum
 201             print('reading reg %d' % regnum)
 202             inputs.append(self.gpr(regnum))
 203         print(inputs)
 204         results = info.func(self, *inputs)
 205         print(results)
 206
 207         if info.write_regs:
 208             output_names = create_args(info.write_regs)
 209             for name, output in zip(output_names, results):
 210                 regnum = yield getattr(self.decoder, name)
 211                 print('writing reg %d' % regnum)
 212                 if output.bits > 64:
 213                     output = SelectableInt(output.value, 64)
 214                 self.gpr[regnum] = output
 215         self.pc.update(self.namespace)
 216
 217
 218 def inject():
 219     """ Decorator factory. """
 220     def variable_injector(func):
 221         @wraps(func)
 222         def decorator(*args, **kwargs):
 223             try:
 224                 func_globals = func.__globals__  # Python 2.6+
 225             except AttributeError:
 226                 func_globals = func.func_globals  # Earlier versions.
 227
 228             context = args[0].namespace
 229             saved_values = func_globals.copy()  # Shallow copy of dict.
 230             func_globals.update(context)
 231
 232             result = func(*args, **kwargs)
 233             #exec (func.__code__, func_globals)
 234
 235             #finally:
 236             #    func_globals = saved_values  # Undo changes.
 237
 238             return result
 239
 240         return decorator
 241
 242     return variable_injector
 243