src/soc/decoder/isa/caller.py

   1 from functools import wraps
   2 from soc.decoder.orderedset import OrderedSet
   3 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
   4                                         selectconcat)
   5 from collections import namedtuple
   6 import math
   7
   8 instruction_info = namedtuple('instruction_info',
   9                               'func read_regs uninit_regs write_regs ' + \
  10                               'special_regs op_fields form asmregs')
  11
  12 special_sprs = {
  13     'LR': 8,
  14     'CTR': 9,
  15     'TAR': 815,
  16     'XER': 0,
  17     'VRSAVE': 256}
  18
  19
  20 def create_args(reglist, extra=None):
  21     args = OrderedSet()
  22     for reg in reglist:
  23         args.add(reg)
  24     args = list(args)
  25     if extra:
  26         args = [extra] + args
  27     return args
  28
  29
  30 class Mem:
  31
  32     def __init__(self, bytes_per_word=8):
  33         self.mem = {}
  34         self.bytes_per_word = bytes_per_word
  35         self.word_log2 = math.ceil(math.log2(bytes_per_word))
  36
  37     def _get_shifter_mask(self, width, remainder):
  38         shifter = ((self.bytes_per_word - width) - remainder) * \
  39             8  # bits per byte
  40         mask = (1 << (width * 8)) - 1
  41         return shifter, mask
  42
  43     # TODO: Implement ld/st of lesser width
  44     def ld(self, address, width=8):
  45         remainder = address & (self.bytes_per_word - 1)
  46         address = address >> self.word_log2
  47         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  48         if address in self.mem:
  49             val = self.mem[address]
  50         else:
  51             val = 0
  52
  53         if width != self.bytes_per_word:
  54             shifter, mask = self._get_shifter_mask(width, remainder)
  55             val = val & (mask << shifter)
  56             val >>= shifter
  57         print("Read {:x} from addr {:x}".format(val, address))
  58         return val
  59
  60     def st(self, address, value, width=8):
  61         remainder = address & (self.bytes_per_word - 1)
  62         address = address >> self.word_log2
  63         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  64         print("Writing {:x} to addr {:x}".format(value, address))
  65         if width != self.bytes_per_word:
  66             if address in self.mem:
  67                 val = self.mem[address]
  68             else:
  69                 val = 0
  70             shifter, mask = self._get_shifter_mask(width, remainder)
  71             val &= ~(mask << shifter)
  72             val |= value << shifter
  73             self.mem[address] = val
  74         else:
  75             self.mem[address] = value
  76
  77     def __call__(self, addr, sz):
  78         val = self.ld(addr.value, sz)
  79         print ("memread", addr, sz, val)
  80         return SelectableInt(val, sz*8)
  81
  82     def memassign(self, addr, sz, val):
  83         print ("memassign", addr, sz, val)
  84         self.st(addr.value, val.value, sz)
  85
  86
  87 class GPR(dict):
  88     def __init__(self, decoder, regfile):
  89         dict.__init__(self)
  90         self.sd = decoder
  91         for i in range(32):
  92             self[i] = SelectableInt(regfile[i], 64)
  93
  94     def __call__(self, ridx):
  95         return self[ridx]
  96
  97     def set_form(self, form):
  98         self.form = form
  99
 100     def getz(self, rnum):
 101         #rnum = rnum.value # only SelectableInt allowed
 102         print("GPR getzero", rnum)
 103         if rnum == 0:
 104             return SelectableInt(0, 64)
 105         return self[rnum]
 106
 107     def _get_regnum(self, attr):
 108         getform = self.sd.sigforms[self.form]
 109         rnum = getattr(getform, attr)
 110         return rnum
 111
 112     def ___getitem__(self, attr):
 113         print("GPR getitem", attr)
 114         rnum = self._get_regnum(attr)
 115         return self.regfile[rnum]
 116
 117     def dump(self):
 118         for i in range(0, len(self), 8):
 119             s = []
 120             for j in range(8):
 121                 s.append("%08x" % self[i+j].value)
 122             s = ' '.join(s)
 123             print("reg", "%2d" % i, s)
 124
 125 class PC:
 126     def __init__(self, pc_init=0):
 127         self.CIA = SelectableInt(pc_init, 64)
 128         self.NIA = self.CIA + SelectableInt(4, 64)
 129
 130     def update(self, namespace):
 131         self.CIA = namespace['NIA'].narrow(64)
 132         self.NIA = self.CIA + SelectableInt(4, 64)
 133         namespace['CIA'] = self.CIA
 134         namespace['NIA'] = self.NIA
 135
 136
 137 class SPR(dict):
 138     def __init__(self, dec2):
 139         self.sd = dec2
 140         dict.__init__(self)
 141
 142     def __getitem__(self, key):
 143         # if key in special_sprs get the special spr, otherwise return key
 144         if isinstance(key, SelectableInt):
 145             key = key.value
 146         key = special_sprs.get(key, key)
 147         if key in self:
 148             return dict.__getitem__(self, key)
 149         else:
 150             import pdb; pdb.set_trace()
 151             return SelectableInt(0, 64)
 152
 153     def __setitem__(self, key, value):
 154         if isinstance(key, SelectableInt):
 155             key = key.value
 156         key = special_sprs.get(key, key)
 157         dict.__setitem__(self, key, value)
 158
 159     def __call__(self, ridx):
 160         return self[ridx]
 161
 162
 163
 164 class ISACaller:
 165     # decoder2 - an instance of power_decoder2
 166     # regfile - a list of initial values for the registers
 167     def __init__(self, decoder2, regfile):
 168         self.gpr = GPR(decoder2, regfile)
 169         self.mem = Mem()
 170         self.pc = PC()
 171         self.spr = SPR(decoder2)
 172         # TODO, needed here:
 173         # FPR (same as GPR except for FP nums)
 174         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
 175         #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
 176         # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
 177         #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
 178         # 2.3.2 LR   (actually SPR #8)
 179         # 2.3.3 CTR  (actually SPR #9)
 180         # 2.3.4 TAR  (actually SPR #815)
 181         # 3.2.2 p45 XER  (actually SPR #0)
 182         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 183
 184         # create CR then allow portions of it to be "selectable" (below)
 185         self._cr = SelectableInt(0, 64) # underlying reg
 186         self.cr = FieldSelectableInt(self._cr, list(range(32,64)))
 187
 188         # "undefined", just set to variable-bit-width int (use exts "max")
 189         self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
 190
 191         self.namespace = {'GPR': self.gpr,
 192                           'MEM': self.mem,
 193                           'SPR': self.spr,
 194                           'memassign': self.memassign,
 195                           'NIA': self.pc.NIA,
 196                           'CIA': self.pc.CIA,
 197                           'CR': self.cr,
 198                           'undefined': self.undefined,
 199                           'mode_is_64bit': True,
 200                           }
 201
 202         # field-selectable versions of Condition Register TODO check bitranges?
 203         self.crl = []
 204         for i in range(8):
 205             bits = tuple(range((7-i)*4, (8-i)*4))# errr... maybe?
 206             _cr = FieldSelectableInt(self.cr, bits)
 207             self.crl.append(_cr)
 208             self.namespace["CR%d" % i] = _cr
 209
 210         self.decoder = decoder2
 211
 212     def memassign(self, ea, sz, val):
 213         self.mem.memassign(ea, sz, val)
 214
 215     def prep_namespace(self, formname, op_fields):
 216         # TODO: get field names from form in decoder*1* (not decoder2)
 217         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 218         # from spec
 219         # then "yield" fields only from op_fields rather than hard-coded
 220         # list, here.
 221         fields = self.decoder.sigforms[formname]
 222         for name in op_fields:
 223             if name == 'spr':
 224                 sig = getattr(fields, name.upper())
 225             else:
 226                 sig = getattr(fields, name)
 227             val = yield sig
 228             self.namespace[name] = SelectableInt(val, sig.width)
 229
 230     def call(self, name):
 231         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 232         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 233         info = self.instrs[name]
 234         yield from self.prep_namespace(info.form, info.op_fields)
 235
 236         # preserve order of register names
 237         input_names = create_args(list(info.read_regs) + list(info.uninit_regs))
 238         print(input_names)
 239
 240         # main registers (RT, RA ...)
 241         inputs = []
 242         for name in input_names:
 243             regnum = yield getattr(self.decoder, name)
 244             regname = "_" + name
 245             self.namespace[regname] = regnum
 246             print('reading reg %d' % regnum)
 247             inputs.append(self.gpr(regnum))
 248
 249         # "special" registers
 250         for special in info.special_regs:
 251             if special in special_sprs:
 252                 inputs.append(self.spr[special])
 253             else:
 254                 inputs.append(self.namespace[special])
 255
 256         print(inputs)
 257         results = info.func(self, *inputs)
 258         print(results)
 259
 260         # any modified return results?
 261         if info.write_regs:
 262             output_names = create_args(info.write_regs)
 263             for name, output in zip(output_names, results):
 264                 if name in info.special_regs:
 265                     print('writing special %s' % name, output)
 266                     if name in special_sprs:
 267                         self.spr[name] = output
 268                     else:
 269                         self.namespace[name].eq(output)
 270                 else:
 271                     regnum = yield getattr(self.decoder, name)
 272                     print('writing reg %d' % regnum)
 273                     if output.bits > 64:
 274                         output = SelectableInt(output.value, 64)
 275                     self.gpr[regnum] = output
 276
 277         # update program counter
 278         self.pc.update(self.namespace)
 279
 280
 281 def inject():
 282     """ Decorator factory. """
 283     def variable_injector(func):
 284         @wraps(func)
 285         def decorator(*args, **kwargs):
 286             try:
 287                 func_globals = func.__globals__  # Python 2.6+
 288             except AttributeError:
 289                 func_globals = func.func_globals  # Earlier versions.
 290
 291             context = args[0].namespace
 292             saved_values = func_globals.copy()  # Shallow copy of dict.
 293             func_globals.update(context)
 294             result = func(*args, **kwargs)
 295             args[0].namespace = func_globals
 296             #exec (func.__code__, func_globals)
 297
 298             #finally:
 299             #    func_globals = saved_values  # Undo changes.
 300
 301             return result
 302
 303         return decorator
 304
 305     return variable_injector
 306