src/soc/decoder/isa/caller.py

   1 from functools import wraps
   2 from soc.decoder.orderedset import OrderedSet
   3 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
   4                                         selectconcat)
   5 from soc.decoder.power_enums import spr_dict, XER_bits
   6 from soc.decoder.helpers import exts
   7 from collections import namedtuple
   8 import math
   9
  10 instruction_info = namedtuple('instruction_info',
  11                               'func read_regs uninit_regs write_regs ' + \
  12                               'special_regs op_fields form asmregs')
  13
  14 special_sprs = {
  15     'LR': 8,
  16     'CTR': 9,
  17     'TAR': 815,
  18     'XER': 1,
  19     'VRSAVE': 256}
  20
  21
  22 def create_args(reglist, extra=None):
  23     args = OrderedSet()
  24     for reg in reglist:
  25         args.add(reg)
  26     args = list(args)
  27     if extra:
  28         args = [extra] + args
  29     return args
  30
  31
  32 class Mem:
  33
  34     def __init__(self, bytes_per_word=8, initial_mem=None):
  35         self.mem = {}
  36         self.bytes_per_word = bytes_per_word
  37         self.word_log2 = math.ceil(math.log2(bytes_per_word))
  38         if not initial_mem:
  39             return
  40         print ("Sim-Mem", initial_mem, self.bytes_per_word)
  41         for addr, (val, width) in initial_mem.items():
  42             self.st(addr, val, width)
  43
  44     def _get_shifter_mask(self, wid, remainder):
  45         shifter = ((self.bytes_per_word - wid) - remainder) * \
  46             8  # bits per byte
  47         mask = (1 << (wid * 8)) - 1
  48         print ("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
  49         return shifter, mask
  50
  51     # TODO: Implement ld/st of lesser width
  52     def ld(self, address, width=8):
  53         print("ld from addr 0x{:x} width {:d}".format(address, width))
  54         remainder = address & (self.bytes_per_word - 1)
  55         address = address >> self.word_log2
  56         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  57         if address in self.mem:
  58             val = self.mem[address]
  59         else:
  60             val = 0
  61         print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val))
  62
  63         if width != self.bytes_per_word:
  64             shifter, mask = self._get_shifter_mask(width, remainder)
  65             print ("masking", hex(val), hex(mask<<shifter), shifter)
  66             val = val & (mask << shifter)
  67             val >>= shifter
  68         print("Read 0x{:x} from addr 0x{:x}".format(val, address))
  69         return val
  70
  71     def st(self, addr, v, width=8):
  72         remainder = addr & (self.bytes_per_word - 1)
  73         addr = addr >> self.word_log2
  74         print("Writing 0x{:x} to addr 0x{:x}/{:x}".format(v, addr, remainder))
  75         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  76         if width != self.bytes_per_word:
  77             if addr in self.mem:
  78                 val = self.mem[addr]
  79             else:
  80                 val = 0
  81             shifter, mask = self._get_shifter_mask(width, remainder)
  82             val &= ~(mask << shifter)
  83             val |= v << shifter
  84             self.mem[addr] = val
  85         else:
  86             self.mem[addr] = v
  87         print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
  88
  89     def __call__(self, addr, sz):
  90         val = self.ld(addr.value, sz)
  91         print ("memread", addr, sz, val)
  92         return SelectableInt(val, sz*8)
  93
  94     def memassign(self, addr, sz, val):
  95         print ("memassign", addr, sz, val)
  96         self.st(addr.value, val.value, sz)
  97
  98
  99 class GPR(dict):
 100     def __init__(self, decoder, regfile):
 101         dict.__init__(self)
 102         self.sd = decoder
 103         for i in range(32):
 104             self[i] = SelectableInt(regfile[i], 64)
 105
 106     def __call__(self, ridx):
 107         return self[ridx]
 108
 109     def set_form(self, form):
 110         self.form = form
 111
 112     def getz(self, rnum):
 113         #rnum = rnum.value # only SelectableInt allowed
 114         print("GPR getzero", rnum)
 115         if rnum == 0:
 116             return SelectableInt(0, 64)
 117         return self[rnum]
 118
 119     def _get_regnum(self, attr):
 120         getform = self.sd.sigforms[self.form]
 121         rnum = getattr(getform, attr)
 122         return rnum
 123
 124     def ___getitem__(self, attr):
 125         print("GPR getitem", attr)
 126         rnum = self._get_regnum(attr)
 127         return self.regfile[rnum]
 128
 129     def dump(self):
 130         for i in range(0, len(self), 8):
 131             s = []
 132             for j in range(8):
 133                 s.append("%08x" % self[i+j].value)
 134             s = ' '.join(s)
 135             print("reg", "%2d" % i, s)
 136
 137 class PC:
 138     def __init__(self, pc_init=0):
 139         self.CIA = SelectableInt(pc_init, 64)
 140         self.NIA = self.CIA + SelectableInt(4, 64)
 141
 142     def update(self, namespace):
 143         self.CIA = namespace['NIA'].narrow(64)
 144         self.NIA = self.CIA + SelectableInt(4, 64)
 145         namespace['CIA'] = self.CIA
 146         namespace['NIA'] = self.NIA
 147
 148
 149 class SPR(dict):
 150     def __init__(self, dec2, initial_sprs={}):
 151         self.sd = dec2
 152         dict.__init__(self)
 153         self.update(initial_sprs)
 154
 155     def __getitem__(self, key):
 156         # if key in special_sprs get the special spr, otherwise return key
 157         if isinstance(key, SelectableInt):
 158             key = key.value
 159         key = special_sprs.get(key, key)
 160         if key in self:
 161             return dict.__getitem__(self, key)
 162         else:
 163             info = spr_dict[key]
 164             dict.__setitem__(self, key, SelectableInt(0, info.length))
 165             return dict.__getitem__(self, key)
 166
 167     def __setitem__(self, key, value):
 168         if isinstance(key, SelectableInt):
 169             key = key.value
 170         key = special_sprs.get(key, key)
 171         dict.__setitem__(self, key, value)
 172
 173     def __call__(self, ridx):
 174         return self[ridx]
 175
 176
 177
 178 class ISACaller:
 179     # decoder2 - an instance of power_decoder2
 180     # regfile - a list of initial values for the registers
 181     def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
 182                        initial_mem=None, initial_msr=0):
 183         if initial_sprs is None:
 184             initial_sprs = {}
 185         if initial_mem is None:
 186             initial_mem = {}
 187         self.gpr = GPR(decoder2, regfile)
 188         self.mem = Mem(initial_mem=initial_mem)
 189         self.pc = PC()
 190         self.spr = SPR(decoder2, initial_sprs)
 191         self.msr = SelectableInt(initial_msr, 64) # underlying reg
 192         # TODO, needed here:
 193         # FPR (same as GPR except for FP nums)
 194         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
 195         #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
 196         # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
 197         #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
 198         #         -- Done
 199         # 2.3.2 LR   (actually SPR #8) -- Done
 200         # 2.3.3 CTR  (actually SPR #9) -- Done
 201         # 2.3.4 TAR  (actually SPR #815)
 202         # 3.2.2 p45 XER  (actually SPR #1) -- Done
 203         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 204
 205         # create CR then allow portions of it to be "selectable" (below)
 206         self._cr = SelectableInt(initial_cr, 64) # underlying reg
 207         self.cr = FieldSelectableInt(self._cr, list(range(32,64)))
 208
 209         # "undefined", just set to variable-bit-width int (use exts "max")
 210         self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
 211
 212         self.namespace = {'GPR': self.gpr,
 213                           'MEM': self.mem,
 214                           'SPR': self.spr,
 215                           'memassign': self.memassign,
 216                           'NIA': self.pc.NIA,
 217                           'CIA': self.pc.CIA,
 218                           'CR': self.cr,
 219                           'MSR': self.msr,
 220                           'undefined': self.undefined,
 221                           'mode_is_64bit': True,
 222                           'SO': XER_bits['SO']
 223                           }
 224
 225         # field-selectable versions of Condition Register TODO check bitranges?
 226         self.crl = []
 227         for i in range(8):
 228             bits = tuple(range(i*4, (i+1)*4))# errr... maybe?
 229             _cr = FieldSelectableInt(self.cr, bits)
 230             self.crl.append(_cr)
 231             self.namespace["CR%d" % i] = _cr
 232
 233         self.decoder = decoder2.dec
 234         self.dec2 = decoder2
 235
 236     def memassign(self, ea, sz, val):
 237         self.mem.memassign(ea, sz, val)
 238
 239     def prep_namespace(self, formname, op_fields):
 240         # TODO: get field names from form in decoder*1* (not decoder2)
 241         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 242         # from spec
 243         # then "yield" fields only from op_fields rather than hard-coded
 244         # list, here.
 245         fields = self.decoder.sigforms[formname]
 246         for name in op_fields:
 247             if name == 'spr':
 248                 sig = getattr(fields, name.upper())
 249             else:
 250                 sig = getattr(fields, name)
 251             val = yield sig
 252             if name in ['BF', 'BFA']:
 253                 self.namespace[name] = val
 254             else:
 255                 self.namespace[name] = SelectableInt(val, sig.width)
 256
 257         self.namespace['XER'] = self.spr['XER']
 258         self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
 259
 260     def handle_carry_(self, inputs, outputs):
 261         inv_a = yield self.dec2.e.invert_a
 262         if inv_a:
 263             inputs[0] = ~inputs[0]
 264
 265         imm_ok = yield self.dec2.e.imm_data.ok
 266         if imm_ok:
 267             imm = yield self.dec2.e.imm_data.data
 268             inputs.append(SelectableInt(imm, 64))
 269         assert len(outputs) >= 1
 270         output = outputs[0]
 271         gts = [(x > output) for x in inputs]
 272         print(gts)
 273         cy = 1 if any(gts) else 0
 274         self.spr['XER'][XER_bits['CA']] = cy
 275
 276
 277         # 32 bit carry
 278         gts = [(x[32:64] > output[32:64]) == SelectableInt(1, 1)
 279                for x in inputs]
 280         cy32 = 1 if any(gts) else 0
 281         self.spr['XER'][XER_bits['CA32']] = cy32
 282
 283     def handle_overflow(self, inputs, outputs):
 284         inv_a = yield self.dec2.e.invert_a
 285         if inv_a:
 286             inputs[0] = ~inputs[0]
 287
 288         imm_ok = yield self.dec2.e.imm_data.ok
 289         if imm_ok:
 290             imm = yield self.dec2.e.imm_data.data
 291             inputs.append(SelectableInt(imm, 64))
 292         assert len(outputs) >= 1
 293         if len(inputs) >= 2:
 294             output = outputs[0]
 295             input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
 296             output_sgn = exts(output.value, output.bits) < 0
 297             ov = 1 if input_sgn[0] == input_sgn[1] and \
 298                 output_sgn != input_sgn[0] else 0
 299
 300             self.spr['XER'][XER_bits['OV']] = ov
 301             so = self.spr['XER'][XER_bits['SO']]
 302             so = so | ov
 303             self.spr['XER'][XER_bits['SO']] = so
 304
 305
 306
 307     def handle_comparison(self, outputs):
 308         out = outputs[0]
 309         out = exts(out.value, out.bits)
 310         zero = SelectableInt(out == 0, 1)
 311         positive = SelectableInt(out > 0, 1)
 312         negative = SelectableInt(out < 0, 1)
 313         SO = self.spr['XER'][XER_bits['SO']]
 314         cr_field = selectconcat(negative, positive, zero, SO)
 315         self.crl[0].eq(cr_field)
 316
 317     def set_pc(self, pc_val):
 318         self.namespace['NIA'] = SelectableInt(pc_val, 64)
 319         self.pc.update(self.namespace)
 320
 321
 322     def call(self, name):
 323         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 324         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 325         info = self.instrs[name]
 326         yield from self.prep_namespace(info.form, info.op_fields)
 327
 328         # preserve order of register names
 329         input_names = create_args(list(info.read_regs) + list(info.uninit_regs))
 330         print(input_names)
 331
 332         # main registers (RT, RA ...)
 333         inputs = []
 334         for name in input_names:
 335             regnum = yield getattr(self.decoder, name)
 336             regname = "_" + name
 337             self.namespace[regname] = regnum
 338             print('reading reg %d' % regnum)
 339             inputs.append(self.gpr(regnum))
 340
 341         # "special" registers
 342         for special in info.special_regs:
 343             if special in special_sprs:
 344                 inputs.append(self.spr[special])
 345             else:
 346                 inputs.append(self.namespace[special])
 347
 348         print(inputs)
 349         results = info.func(self, *inputs)
 350         print(results)
 351
 352         carry_en = yield self.dec2.e.output_carry
 353         if carry_en:
 354             yield from self.handle_carry_(inputs, results)
 355         ov_en = yield self.dec2.e.oe
 356         if ov_en:
 357             yield from self.handle_overflow(inputs, results)
 358         rc_en = yield self.dec2.e.rc.data
 359         if rc_en:
 360             self.handle_comparison(results)
 361
 362         # any modified return results?
 363         if info.write_regs:
 364             output_names = create_args(info.write_regs)
 365             for name, output in zip(output_names, results):
 366                 if isinstance(output, int):
 367                     output = SelectableInt(output, 256)
 368                 if name in info.special_regs:
 369                     print('writing special %s' % name, output)
 370                     if name in special_sprs:
 371                         self.spr[name] = output
 372                     else:
 373                         self.namespace[name].eq(output)
 374                 else:
 375                     regnum = yield getattr(self.decoder, name)
 376                     print('writing reg %d %s' % (regnum, str(output)))
 377                     if output.bits > 64:
 378                         output = SelectableInt(output.value, 64)
 379                     self.gpr[regnum] = output
 380
 381         # update program counter
 382         self.pc.update(self.namespace)
 383
 384
 385 def inject():
 386     """ Decorator factory. """
 387     def variable_injector(func):
 388         @wraps(func)
 389         def decorator(*args, **kwargs):
 390             try:
 391                 func_globals = func.__globals__  # Python 2.6+
 392             except AttributeError:
 393                 func_globals = func.func_globals  # Earlier versions.
 394
 395             context = args[0].namespace
 396             saved_values = func_globals.copy()  # Shallow copy of dict.
 397             func_globals.update(context)
 398             result = func(*args, **kwargs)
 399             args[0].namespace = func_globals
 400             #exec (func.__code__, func_globals)
 401
 402             #finally:
 403             #    func_globals = saved_values  # Undo changes.
 404
 405             return result
 406
 407         return decorator
 408
 409     return variable_injector
 410