src/soc/decoder/isa/caller.py

   1 from functools import wraps
   2 from soc.decoder.orderedset import OrderedSet
   3 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
   4                                         selectconcat)
   5 from soc.decoder.power_enums import spr_dict, XER_bits
   6 from soc.decoder.helpers import exts
   7 from collections import namedtuple
   8 import math
   9
  10 instruction_info = namedtuple('instruction_info',
  11                               'func read_regs uninit_regs write_regs ' + \
  12                               'special_regs op_fields form asmregs')
  13
  14 special_sprs = {
  15     'LR': 8,
  16     'CTR': 9,
  17     'TAR': 815,
  18     'XER': 1,
  19     'VRSAVE': 256}
  20
  21
  22 def create_args(reglist, extra=None):
  23     args = OrderedSet()
  24     for reg in reglist:
  25         args.add(reg)
  26     args = list(args)
  27     if extra:
  28         args = [extra] + args
  29     return args
  30
  31
  32 class Mem:
  33
  34     def __init__(self, bytes_per_word=8, initial_mem=None):
  35         self.mem = {}
  36         self.bytes_per_word = bytes_per_word
  37         self.word_log2 = math.ceil(math.log2(bytes_per_word))
  38         if not initial_mem:
  39             return
  40         print ("Mem", initial_mem)
  41         for addr, (val, width) in initial_mem.items():
  42             self.st(addr, val, width)
  43
  44     def _get_shifter_mask(self, wid, remainder):
  45         #shifter = ((self.bytes_per_word - wid) - remainder) * \
  46             #8  # bits per byte
  47         shifter = remainder * 8 # bits per byte
  48         mask = (1 << (wid * 8)) - 1
  49         print ("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
  50         return shifter, mask
  51
  52     # TODO: Implement ld/st of lesser width
  53     def ld(self, address, width=8):
  54         remainder = address & (self.bytes_per_word - 1)
  55         address = address >> self.word_log2
  56         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  57         if address in self.mem:
  58             val = self.mem[address]
  59         else:
  60             val = 0
  61
  62         if width != self.bytes_per_word:
  63             shifter, mask = self._get_shifter_mask(width, remainder)
  64             val = val & (mask << shifter)
  65             val >>= shifter
  66         print("Read 0x{:x} from addr 0x{:x}".format(val, address))
  67         return val
  68
  69     def st(self, addr, v, width=8):
  70         remainder = addr & (self.bytes_per_word - 1)
  71         addr = addr >> self.word_log2
  72         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  73         print("Writing 0x{:x} to addr 0x{:x}/{:x}".format(v, addr, remainder))
  74         if width != self.bytes_per_word:
  75             if addr in self.mem:
  76                 val = self.mem[addr]
  77             else:
  78                 val = 0
  79             shifter, mask = self._get_shifter_mask(width, remainder)
  80             val &= ~(mask << shifter)
  81             val |= v << shifter
  82             self.mem[addr] = val
  83         else:
  84             self.mem[addr] = v
  85         print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
  86
  87     def __call__(self, addr, sz):
  88         val = self.ld(addr.value, sz)
  89         print ("memread", addr, sz, val)
  90         return SelectableInt(val, sz*8)
  91
  92     def memassign(self, addr, sz, val):
  93         print ("memassign", addr, sz, val)
  94         self.st(addr.value, val.value, sz)
  95
  96
  97 class GPR(dict):
  98     def __init__(self, decoder, regfile):
  99         dict.__init__(self)
 100         self.sd = decoder
 101         for i in range(32):
 102             self[i] = SelectableInt(regfile[i], 64)
 103
 104     def __call__(self, ridx):
 105         return self[ridx]
 106
 107     def set_form(self, form):
 108         self.form = form
 109
 110     def getz(self, rnum):
 111         #rnum = rnum.value # only SelectableInt allowed
 112         print("GPR getzero", rnum)
 113         if rnum == 0:
 114             return SelectableInt(0, 64)
 115         return self[rnum]
 116
 117     def _get_regnum(self, attr):
 118         getform = self.sd.sigforms[self.form]
 119         rnum = getattr(getform, attr)
 120         return rnum
 121
 122     def ___getitem__(self, attr):
 123         print("GPR getitem", attr)
 124         rnum = self._get_regnum(attr)
 125         return self.regfile[rnum]
 126
 127     def dump(self):
 128         for i in range(0, len(self), 8):
 129             s = []
 130             for j in range(8):
 131                 s.append("%08x" % self[i+j].value)
 132             s = ' '.join(s)
 133             print("reg", "%2d" % i, s)
 134
 135 class PC:
 136     def __init__(self, pc_init=0):
 137         self.CIA = SelectableInt(pc_init, 64)
 138         self.NIA = self.CIA + SelectableInt(4, 64)
 139
 140     def update(self, namespace):
 141         self.CIA = namespace['NIA'].narrow(64)
 142         self.NIA = self.CIA + SelectableInt(4, 64)
 143         namespace['CIA'] = self.CIA
 144         namespace['NIA'] = self.NIA
 145
 146
 147 class SPR(dict):
 148     def __init__(self, dec2, initial_sprs={}):
 149         self.sd = dec2
 150         dict.__init__(self)
 151         self.update(initial_sprs)
 152
 153     def __getitem__(self, key):
 154         # if key in special_sprs get the special spr, otherwise return key
 155         if isinstance(key, SelectableInt):
 156             key = key.value
 157         key = special_sprs.get(key, key)
 158         if key in self:
 159             return dict.__getitem__(self, key)
 160         else:
 161             info = spr_dict[key]
 162             dict.__setitem__(self, key, SelectableInt(0, info.length))
 163             return dict.__getitem__(self, key)
 164
 165     def __setitem__(self, key, value):
 166         if isinstance(key, SelectableInt):
 167             key = key.value
 168         key = special_sprs.get(key, key)
 169         dict.__setitem__(self, key, value)
 170
 171     def __call__(self, ridx):
 172         return self[ridx]
 173
 174
 175
 176 class ISACaller:
 177     # decoder2 - an instance of power_decoder2
 178     # regfile - a list of initial values for the registers
 179     def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
 180                        initial_mem=None):
 181         if initial_sprs is None:
 182             initial_sprs = {}
 183         if initial_mem is None:
 184             initial_mem = {}
 185         self.gpr = GPR(decoder2, regfile)
 186         self.mem = Mem(initial_mem=initial_mem)
 187         self.pc = PC()
 188         self.spr = SPR(decoder2, initial_sprs)
 189         # TODO, needed here:
 190         # FPR (same as GPR except for FP nums)
 191         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
 192         #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
 193         # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
 194         #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
 195         #         -- Done
 196         # 2.3.2 LR   (actually SPR #8) -- Done
 197         # 2.3.3 CTR  (actually SPR #9) -- Done
 198         # 2.3.4 TAR  (actually SPR #815)
 199         # 3.2.2 p45 XER  (actually SPR #1) -- Done
 200         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 201
 202         # create CR then allow portions of it to be "selectable" (below)
 203         self._cr = SelectableInt(initial_cr, 64) # underlying reg
 204         self.cr = FieldSelectableInt(self._cr, list(range(32,64)))
 205
 206         # "undefined", just set to variable-bit-width int (use exts "max")
 207         self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
 208
 209         self.namespace = {'GPR': self.gpr,
 210                           'MEM': self.mem,
 211                           'SPR': self.spr,
 212                           'memassign': self.memassign,
 213                           'NIA': self.pc.NIA,
 214                           'CIA': self.pc.CIA,
 215                           'CR': self.cr,
 216                           'undefined': self.undefined,
 217                           'mode_is_64bit': True,
 218                           'SO': XER_bits['SO']
 219                           }
 220
 221         # field-selectable versions of Condition Register TODO check bitranges?
 222         self.crl = []
 223         for i in range(8):
 224             bits = tuple(range(i*4, (i+1)*4))# errr... maybe?
 225             _cr = FieldSelectableInt(self.cr, bits)
 226             self.crl.append(_cr)
 227             self.namespace["CR%d" % i] = _cr
 228
 229         self.decoder = decoder2.dec
 230         self.dec2 = decoder2
 231
 232     def memassign(self, ea, sz, val):
 233         self.mem.memassign(ea, sz, val)
 234
 235     def prep_namespace(self, formname, op_fields):
 236         # TODO: get field names from form in decoder*1* (not decoder2)
 237         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 238         # from spec
 239         # then "yield" fields only from op_fields rather than hard-coded
 240         # list, here.
 241         fields = self.decoder.sigforms[formname]
 242         for name in op_fields:
 243             if name == 'spr':
 244                 sig = getattr(fields, name.upper())
 245             else:
 246                 sig = getattr(fields, name)
 247             val = yield sig
 248             if name in ['BF', 'BFA']:
 249                 self.namespace[name] = val
 250             else:
 251                 self.namespace[name] = SelectableInt(val, sig.width)
 252
 253         self.namespace['XER'] = self.spr['XER']
 254         self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
 255
 256     def handle_carry_(self, inputs, outputs):
 257         inv_a = yield self.dec2.e.invert_a
 258         if inv_a:
 259             inputs[0] = ~inputs[0]
 260
 261         imm_ok = yield self.dec2.e.imm_data.ok
 262         if imm_ok:
 263             imm = yield self.dec2.e.imm_data.data
 264             inputs.append(SelectableInt(imm, 64))
 265         assert len(outputs) >= 1
 266         output = outputs[0]
 267         gts = [(x > output) for x in inputs]
 268         print(gts)
 269         cy = 1 if any(gts) else 0
 270         self.spr['XER'][XER_bits['CA']] = cy
 271
 272
 273         # 32 bit carry
 274         gts = [(x[32:64] > output[32:64]) == SelectableInt(1, 1)
 275                for x in inputs]
 276         cy32 = 1 if any(gts) else 0
 277         self.spr['XER'][XER_bits['CA32']] = cy32
 278
 279     def handle_overflow(self, inputs, outputs):
 280         inv_a = yield self.dec2.e.invert_a
 281         if inv_a:
 282             inputs[0] = ~inputs[0]
 283
 284         imm_ok = yield self.dec2.e.imm_data.ok
 285         if imm_ok:
 286             imm = yield self.dec2.e.imm_data.data
 287             inputs.append(SelectableInt(imm, 64))
 288         assert len(outputs) >= 1
 289         if len(inputs) >= 2:
 290             output = outputs[0]
 291             input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
 292             output_sgn = exts(output.value, output.bits) < 0
 293             ov = 1 if input_sgn[0] == input_sgn[1] and \
 294                 output_sgn != input_sgn[0] else 0
 295
 296             self.spr['XER'][XER_bits['OV']] = ov
 297             so = self.spr['XER'][XER_bits['SO']]
 298             so = so | ov
 299             self.spr['XER'][XER_bits['SO']] = so
 300
 301
 302
 303     def handle_comparison(self, outputs):
 304         out = outputs[0]
 305         out = exts(out.value, out.bits)
 306         zero = SelectableInt(out == 0, 1)
 307         positive = SelectableInt(out > 0, 1)
 308         negative = SelectableInt(out < 0, 1)
 309         SO = self.spr['XER'][XER_bits['SO']]
 310         cr_field = selectconcat(negative, positive, zero, SO)
 311         self.crl[0].eq(cr_field)
 312
 313     def set_pc(self, pc_val):
 314         self.namespace['NIA'] = SelectableInt(pc_val, 64)
 315         self.pc.update(self.namespace)
 316
 317
 318     def call(self, name):
 319         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 320         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 321         info = self.instrs[name]
 322         yield from self.prep_namespace(info.form, info.op_fields)
 323
 324         # preserve order of register names
 325         input_names = create_args(list(info.read_regs) + list(info.uninit_regs))
 326         print(input_names)
 327
 328         # main registers (RT, RA ...)
 329         inputs = []
 330         for name in input_names:
 331             regnum = yield getattr(self.decoder, name)
 332             regname = "_" + name
 333             self.namespace[regname] = regnum
 334             print('reading reg %d' % regnum)
 335             inputs.append(self.gpr(regnum))
 336
 337         # "special" registers
 338         for special in info.special_regs:
 339             if special in special_sprs:
 340                 inputs.append(self.spr[special])
 341             else:
 342                 inputs.append(self.namespace[special])
 343
 344         print(inputs)
 345         results = info.func(self, *inputs)
 346         print(results)
 347
 348         carry_en = yield self.dec2.e.output_carry
 349         if carry_en:
 350             yield from self.handle_carry_(inputs, results)
 351         ov_en = yield self.dec2.e.oe
 352         if ov_en:
 353             yield from self.handle_overflow(inputs, results)
 354         rc_en = yield self.dec2.e.rc.data
 355         if rc_en:
 356             self.handle_comparison(results)
 357
 358         # any modified return results?
 359         if info.write_regs:
 360             output_names = create_args(info.write_regs)
 361             for name, output in zip(output_names, results):
 362                 if isinstance(output, int):
 363                     output = SelectableInt(output, 256)
 364                 if name in info.special_regs:
 365                     print('writing special %s' % name, output)
 366                     if name in special_sprs:
 367                         self.spr[name] = output
 368                     else:
 369                         self.namespace[name].eq(output)
 370                 else:
 371                     regnum = yield getattr(self.decoder, name)
 372                     print('writing reg %d %s' % (regnum, str(output)))
 373                     if output.bits > 64:
 374                         output = SelectableInt(output.value, 64)
 375                     self.gpr[regnum] = output
 376
 377         # update program counter
 378         self.pc.update(self.namespace)
 379
 380
 381 def inject():
 382     """ Decorator factory. """
 383     def variable_injector(func):
 384         @wraps(func)
 385         def decorator(*args, **kwargs):
 386             try:
 387                 func_globals = func.__globals__  # Python 2.6+
 388             except AttributeError:
 389                 func_globals = func.func_globals  # Earlier versions.
 390
 391             context = args[0].namespace
 392             saved_values = func_globals.copy()  # Shallow copy of dict.
 393             func_globals.update(context)
 394             result = func(*args, **kwargs)
 395             args[0].namespace = func_globals
 396             #exec (func.__code__, func_globals)
 397
 398             #finally:
 399             #    func_globals = saved_values  # Undo changes.
 400
 401             return result
 402
 403         return decorator
 404
 405     return variable_injector
 406