Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / decoder / isa / comparefixed.patch
1 --- comparefixed.py.orig 2020-05-15 10:02:00.087668937 -0400
2 +++ comparefixed.py 2020-05-15 12:32:36.834556205 -0400
3 @@ -85,23 +85,22 @@
4 else:
5 in_range = le(src21lo, src1) & le(src1, src21hi) | le(src22lo, src1) & le(
6 src1, src22hi)
7 - CR[4 * BF + 32] = SelectableInt(value=0x0, bits=1)
8 - CR[4 * BF + 33] = in_range
9 - CR[4 * BF + 34] = SelectableInt(value=0x0, bits=1)
10 - CR[4 * BF + 35] = SelectableInt(value=0x0, bits=1)
11 + CR[4 * BF + 32] = SelectableInt(value=0x0, bits=1)
12 + CR[4 * BF + 33] = in_range
13 + CR[4 * BF + 34] = SelectableInt(value=0x0, bits=1)
14 + CR[4 * BF + 35] = SelectableInt(value=0x0, bits=1)
15 return (CR,)
16
17 @inject()
18 - def op_cmpeqb(self, RB, CR):
19 - src1 = GPR[RA]
20 - src1 = src1[56:64]
21 + def op_cmpeqb(self, RA, RB, CR):
22 + src1 = RA[56:64]
23 match = eq(src1, RB[0:8]) | eq(src1, RB[8:16]) | eq(src1, RB[16:24]) | eq(src1,
24 RB[24:32]) | eq(src1, RB[32:40]) | eq(src1, RB[40:48]) | eq(src1, RB[48:56]
25 ) | eq(src1, RB[56:64])
26 - CR[4 * BF + 32] = SelectableInt(value=0x0, bits=1)
27 - CR[4 * BF + 33] = match
28 - CR[4 * BF + 34] = SelectableInt(value=0x0, bits=1)
29 - CR[4 * BF + 35] = SelectableInt(value=0x0, bits=1)
30 + CR[4 * BF + 32] = SelectableInt(value=0x0, bits=1)
31 + CR[4 * BF + 33] = match
32 + CR[4 * BF + 34] = SelectableInt(value=0x0, bits=1)
33 + CR[4 * BF + 35] = SelectableInt(value=0x0, bits=1)
34 return (CR,)
35
36 comparefixed_instrs = {}
37 @@ -136,7 +135,7 @@
38 form='X',
39 asmregs=[['BF', 'L', 'RA', 'RB']])
40 comparefixed_instrs['cmpeqb'] = instruction_info(func=op_cmpeqb,
41 - read_regs=OrderedSet(['RB']),
42 + read_regs=OrderedSet(['RA', 'RB']),
43 uninit_regs=OrderedSet(), write_regs=OrderedSet(['CR']),
44 special_regs=OrderedSet(['CR']), op_fields=OrderedSet(['BF']),
45 form='X',