1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
16 #from nmigen.back.pysim import Settle
18 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
20 from soc
.decoder
.helpers
import exts
, gtu
, ltu
, undefined
21 from soc
.decoder
.isa
.mem
import Mem
22 from soc
.consts
import MSRb
# big-endian (PowerISA versions)
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift
, size
):
30 res
= SelectableInt(0, size
)
33 res
[size
-1-i
] = SelectableInt(1, 1)
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr
,shift
):
54 x
= addr
.value
>> shift
.value
55 return SelectableInt(x
, 16)
64 zero
= SelectableInt(0, 1)
65 return selectconcat(zero
, RTS2(data
), RTS1(data
))
72 return x
[4:56] # python numbering end+1
76 Next Level Size (PATS and RPDS in same bits btw)
79 return x
[59:64] # python numbering end+1
83 Root Page Directory Base
84 power isa docs says 4:55 investigate
86 return x
[8:56] # python numbering end+1
91 //Accessing 2nd double word of partition table (pate1)
92 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
94 // ====================================================
95 // -----------------------------------------------
96 // | /// | PATB | /// | PATS |
97 // -----------------------------------------------
99 // PATB[4:51] holds the base address of the Partition Table,
100 // right shifted by 12 bits.
101 // This is because the address of the Partition base is
102 // 4k aligned. Hence, the lower 12bits, which are always
103 // 0 are ommitted from the PTCR.
105 // Thus, The Partition Table Base is obtained by (PATB << 12)
107 // PATS represents the partition table size right-shifted by 12 bits.
108 // The minimal size of the partition table is 4k.
109 // Thus partition table size = (1 << PATS + 12).
112 // ====================================================
113 // 0 PATE0 63 PATE1 127
114 // |----------------------|----------------------|
116 // |----------------------|----------------------|
118 // |----------------------|----------------------|
120 // |----------------------|----------------------|
124 // |----------------------|----------------------|
126 // |----------------------|----------------------|
128 // The effective LPID forms the index into the Partition Table.
130 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
131 // corresponding to that partition.
133 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
136 // -----------------------------------------------
137 // |1|RTS1|/| RPDB | RTS2 | RPDS |
138 // -----------------------------------------------
139 // 0 1 2 3 4 55 56 58 59 63
141 // HR[0] : For Radix Page table, first bit should be 1.
142 // RTS1[1:2] : Gives one fragment of the Radix treesize
143 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
144 // RTS = (RTS1 << 3 + RTS2) + 31.
146 // RPDB[4:55] = Root Page Directory Base.
147 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
148 // Thus, Root page directory size = 1 << (RPDS + 3).
152 // -----------------------------------------------
153 // |///| PRTB | // | PRTS |
154 // -----------------------------------------------
155 // 0 3 4 51 52 58 59 63
157 // PRTB[4:51] = Process Table Base. This is aligned to size.
158 // PRTS[59: 63] = Process Table Size right shifted by 12.
159 // Minimal size of the process table is 4k.
160 // Process Table Size = (1 << PRTS + 12).
163 // Computing the size aligned Process Table Base:
164 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
165 // Thus, the lower 12+PRTS bits of table_base will
169 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
172 // ==========================
173 // 0 PRTE0 63 PRTE1 127
174 // |----------------------|----------------------|
176 // |----------------------|----------------------|
178 // |----------------------|----------------------|
180 // |----------------------|----------------------|
184 // |----------------------|----------------------|
186 // |----------------------|----------------------|
188 // The effective Process id (PID) forms the index into the Process Table.
190 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
191 // corresponding to that process
193 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
196 // -----------------------------------------------
197 // |/|RTS1|/| RPDB | RTS2 | RPDS |
198 // -----------------------------------------------
199 // 0 1 2 3 4 55 56 58 59 63
201 // RTS1[1:2] : Gives one fragment of the Radix treesize
202 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
203 // RTS = (RTS1 << 3 + RTS2) << 31,
204 // since minimal Radix Tree size is 4G.
206 // RPDB = Root Page Directory Base.
207 // RPDS = Root Page Directory Size right shifted by 3.
208 // Thus, Root page directory size = RPDS << 3.
212 // -----------------------------------------------
214 // -----------------------------------------------
216 // All bits are reserved.
223 0x10000: # PARTITION_TABLE_2 (not implemented yet)
224 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
227 0x30000: # RADIX_ROOT_PTE
228 # V = 1 L = 0 NLB = 0x400 NLS = 9
230 0x40000: # RADIX_SECOND_LEVEL
231 # V = 1 L = 1 SW = 0 RPN = 0
232 # R = 1 C = 1 ATT = 0 EAA 0x7
235 0x1000000: # PROCESS_TABLE_3
236 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
240 # this one has a 2nd level RADIX with a RPN of 0x5000
243 0x10000: # PARTITION_TABLE_2 (not implemented yet)
244 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
247 0x30000: # RADIX_ROOT_PTE
248 # V = 1 L = 0 NLB = 0x400 NLS = 9
250 0x40000: # RADIX_SECOND_LEVEL
251 # V = 1 L = 1 SW = 0 RPN = 0x5000
252 # R = 1 C = 1 ATT = 0 EAA 0x7
255 0x1000000: # PROCESS_TABLE_3
256 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
262 DCACHE GET 1000000 PROCESS_TABLE_3
263 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
264 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
265 DCACHE GET 10000 PARTITION_TABLE_2
266 translated done 1 err 0 badtree 0 addr 40000 pte 0
269 # see qemu/target/ppc/mmu-radix64.c for reference
271 def __init__(self
, mem
, caller
):
274 if caller
is not None:
277 self
.dsisr
= self
.caller
.spr
["DSISR"]
278 self
.dar
= self
.caller
.spr
["DAR"]
279 self
.pidr
= self
.caller
.spr
["PIDR"]
280 self
.prtbl
= self
.caller
.spr
["PRTBL"]
281 self
.msr
= self
.caller
.msr
283 # cached page table stuff
285 self
.pt0_valid
= False
287 self
.pt3_valid
= False
289 def __call__(self
, addr
, sz
):
290 val
= self
.ld(addr
.value
, sz
, swap
=False)
291 print("RADIX memread", addr
, sz
, val
)
292 return SelectableInt(val
, sz
*8)
294 def ld(self
, address
, width
=8, swap
=True, check_in_mem
=False,
296 print("RADIX: ld from addr 0x%x width %d" % (address
, width
))
298 priv
= ~
(self
.msr
[MSRb
.PR
].value
) # problem-state ==> privileged
303 addr
= SelectableInt(address
, 64)
304 pte
= self
._walk
_tree
(addr
, mode
, priv
)
307 print("error on load",pte
)
310 # use pte to load from phys address
311 return self
.mem
.ld(pte
.value
, width
, swap
, check_in_mem
)
313 # XXX set SPRs on error
316 def st(self
, address
, v
, width
=8, swap
=True):
317 print("RADIX: st to addr 0x%x width %d data %x" % (address
, width
, v
))
319 priv
= ~
(self
.msr
[MSRb
.PR
].value
) # problem-state ==> privileged
321 addr
= SelectableInt(address
, 64)
322 pte
= self
._walk
_tree
(addr
, mode
, priv
)
324 # use pte to store at phys address
325 return self
.mem
.st(pte
.value
, v
, width
, swap
)
327 # XXX set SPRs on error
329 def memassign(self
, addr
, sz
, val
):
330 print("memassign", addr
, sz
, val
)
331 self
.st(addr
.value
, val
.value
, sz
, swap
=False)
333 def _next_level(self
, addr
, check_in_mem
):
334 # implement read access to mmu mem here
336 # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
337 value
= self
.mem
.ld(addr
.value
, 8, False, check_in_mem
)
339 return "address lookup %x not found" % addr
.value
340 # assert(value is not None, "address lookup %x not found" % addr.value)
342 data
= SelectableInt(value
, 64) # convert to SelectableInt
343 print("addr", hex(addr
.value
))
344 print("value", hex(value
))
347 def _walk_tree(self
, addr
, mode
, priv
=1):
351 // vaddr |-----------------------------------------------------|
353 // |-----------|-----------------------------------------|
354 // | 0000000 | usefulBits = X bits (typically 52) |
355 // |-----------|-----------------------------------------|
356 // | |<--Cursize---->| |
360 // |-----------------------------------------------------|
363 // PDE |---------------------------| |
364 // |V|L|//| NLB |///|NLS| |
365 // |---------------------------| |
366 // PDE = Page Directory Entry |
367 // [0] = V = Valid Bit |
368 // [1] = L = Leaf bit. If 0, then |
369 // [4:55] = NLB = Next Level Base |
370 // right shifted by 8 |
371 // [59:63] = NLS = Next Level Size |
374 // | |--------------------------|
375 // | | usfulBits = X-Cursize |
376 // | |--------------------------|
377 // |---------------------><--NLS-->| |
381 // |--------------------------|
383 // If the next PDE obtained by |
384 // (NLB << 8 + 8 * index) is a |
385 // nonleaf, then repeat the above. |
387 // If the next PDE is a leaf, |
388 // then Leaf PDE structure is as |
393 // |------------------------------| |----------------|
394 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
395 // |------------------------------| |----------------|
396 // [0] = V = Valid Bit |
397 // [1] = L = Leaf Bit = 1 if leaf |
399 // [2] = Sw = Sw bit 0. |
400 // [7:51] = RPN = Real Page Number, V
401 // real_page = RPN << 12 -------------> Logical OR
402 // [52:54] = Sw Bits 1:3 |
403 // [55] = R = Reference |
404 // [56] = C = Change V
405 // [58:59] = Att = Physical Address
406 // 0b00 = Normal Memory
408 // 0b10 = Non Idenmpotent
409 // 0b11 = Tolerant I/O
410 // [60:63] = Encoded Access
416 pidr
= self
.caller
.spr
["PIDR"]
417 prtbl
= self
.caller
.spr
["PRTBL"]
421 print("last 8 bits ----------")
424 # get address of root entry
425 # need to fetch process table entry
426 # v.shift := unsigned('0' & r.prtbl(4 downto 0));
427 shift
= selectconcat(SelectableInt(0, 1), NLS(prtbl
))
428 addr_next
= self
._get
_prtable
_addr
(shift
, prtbl
, addr
, pidr
)
429 print("starting with prtable, addr_next", addr_next
)
431 assert(addr_next
.bits
== 64)
432 #only for first unit tests assert(addr_next.value == 0x1000000)
434 # read an entry from prtable, decode PTRE
435 data
= self
._next
_level
(addr_next
, check_in_mem
=False)
436 print("pr_table", data
)
437 pgtbl
= data
# this is cached in microwatt (as v.pgtbl3 / v.pgtbl0)
438 (rts
, mbits
, pgbase
) = self
._decode
_prte
(pgtbl
)
439 print("pgbase", pgbase
)
445 # mask_size := mbits(4 downto 0);
446 mask_size
= mbits
[0:5]
447 assert(mask_size
.bits
== 5)
448 print("before segment check ==========")
449 print("mask_size:", bin(mask_size
.value
))
450 print("mbits:", bin(mbits
.value
))
452 print("calling segment_check")
454 shift
= self
._segment
_check
(addr
, mask_size
, shift
)
455 print("shift", shift
)
457 if isinstance(addr
, str):
459 if isinstance(shift
, str):
468 addrsh
= addrshift(addr
, shift
)
469 print("addrsh",addrsh
)
471 print("calling _get_pgtable_addr")
472 print(mask
) #SelectableInt(value=0x9, bits=4)
473 print(pgbase
) #SelectableInt(value=0x40000, bits=56)
474 print(shift
) #SelectableInt(value=0x4, bits=16) #FIXME
475 addr_next
= self
._get
_pgtable
_addr
(mask
, pgbase
, addrsh
)
476 print("DONE addr_next", addr_next
)
478 print("nextlevel----------------------------")
480 data
= self
._next
_level
(addr_next
, check_in_mem
=False)
481 valid
= rpte_valid(data
)
482 leaf
= rpte_leaf(data
)
484 print(" valid, leaf", valid
, leaf
)
486 return "invalid" # TODO: return error
488 print ("is leaf, checking perms")
489 ok
= self
._check
_perms
(data
, priv
, mode
)
490 if ok
== True: # data was ok, found phys address, return it?
491 paddr
= self
._get
_pte
(addrsh
, addr
, data
)
492 print (" phys addr", hex(paddr
.value
))
494 return ok
# return the error code
496 newlookup
= self
._new
_lookup
(data
, shift
, old_shift
)
497 if isinstance(newlookup
, str):
499 old_shift
= shift
# store old_shift before updating shift
500 shift
, mask
, pgbase
= newlookup
501 print (" next level", shift
, mask
, pgbase
)
503 def _get_pgbase(self
, data
):
505 v.pgbase := data(55 downto 8) & x"00"; NLB?
507 zero8
= SelectableInt(0, 8)
508 return selectconcat(zero8
, data
[8:56], zero8
) # shift up 8
510 def _new_lookup(self
, data
, shift
, old_shift
):
512 mbits := unsigned('0' & data(4 downto 0));
513 if mbits < 5 or mbits > 16 or mbits > r.shift then
514 v.state := RADIX_FINISH;
515 v.badtree := '1'; -- throw error
517 v.shift := v.shift - mbits;
518 v.mask_size := mbits(4 downto 0);
519 v.pgbase := data(55 downto 8) & x"00"; NLB?
520 v.state := RADIX_LOOKUP; --> next level
523 mbits
= selectconcat(SelectableInt(0, 1), NLS(data
))
524 print("mbits=", mbits
)
525 if mbits
< 5 or mbits
> 16 or mbits
> old_shift
:
528 # reduce shift (has to be done at same bitwidth)
529 shift
= shift
- mbits
530 assert mbits
.bits
== 6
531 mask_size
= mbits
[2:6] # get 4 LSBs from 6-bit (using MSB0 numbering)
532 pgbase
= self
._get
_pgbase
(data
)
533 return shift
, mask_size
, pgbase
535 def _decode_prte(self
, data
):
537 -----------------------------------------------
538 |/|RTS1|/| RPDB | RTS2 | RPDS |
539 -----------------------------------------------
540 0 1 2 3 4 55 56 58 59 63
542 # note that SelectableInt does big-endian! so the indices
543 # below *directly* match the spec, unlike microwatt which
544 # has to turn them around (to LE)
545 rts
, mbits
= self
._get
_rts
_nls
(data
)
546 pgbase
= self
._get
_pgbase
(data
)
548 return (rts
, mbits
, pgbase
)
550 def _get_rts_nls(self
, data
):
551 # rts = shift = unsigned('0' & data(62 downto 61) & data(7 downto 5));
554 assert(rts
.bits
== 6) # variable rts : unsigned(5 downto 0);
557 # mbits := unsigned('0' & data(4 downto 0));
558 mbits
= selectconcat(SelectableInt(0, 1), NLS(data
))
559 assert(mbits
.bits
== 6) #variable mbits : unsigned(5 downto 0);
563 def _segment_check(self
, addr
, mask_size
, shift
):
564 """checks segment valid
565 mbits := '0' & r.mask_size;
566 v.shift := r.shift + (31 - 12) - mbits;
567 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
568 if r.addr(63) /= r.addr(62) or nonzero = '1' then
569 v.state := RADIX_FINISH;
571 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
572 v.state := RADIX_FINISH;
575 v.state := RADIX_LOOKUP;
577 # note that SelectableInt does big-endian! so the indices
578 # below *directly* match the spec, unlike microwatt which
579 # has to turn them around (to LE)
580 mbits
= selectconcat(SelectableInt(0,1), mask_size
)
581 mask
= genmask(shift
, 44)
582 nonzero
= addr
[2:33] & mask
[13:44] # mask 31 LSBs (BE numbered 13:44)
583 print ("RADIX _segment_check nonzero", bin(nonzero
.value
))
584 print ("RADIX _segment_check addr[0-1]", addr
[0].value
, addr
[1].value
)
585 if addr
[0] != addr
[1] or nonzero
!= 0:
587 limit
= shift
+ (31 - 12)
588 if mbits
.value
< 5 or mbits
.value
> 16 or mbits
.value
> limit
.value
:
590 new_shift
= SelectableInt(limit
.value
- mbits
.value
, shift
.bits
)
591 # TODO verify that returned result is correct
594 def _check_perms(self
, data
, priv
, mode
):
595 """check page permissions
597 // |------------------------------| |----------------|
598 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
599 // |------------------------------| |----------------|
600 // [0] = V = Valid Bit |
601 // [1] = L = Leaf Bit = 1 if leaf |
603 // [2] = Sw = Sw bit 0. |
604 // [7:51] = RPN = Real Page Number, V
605 // real_page = RPN << 12 -------------> Logical OR
606 // [52:54] = Sw Bits 1:3 |
607 // [55] = R = Reference |
608 // [56] = C = Change V
609 // [58:59] = Att = Physical Address
610 // 0b00 = Normal Memory
612 // 0b10 = Non Idenmpotent
613 // 0b11 = Tolerant I/O
614 // [60:63] = Encoded Access
618 -- check permissions and RC bits
620 if r.priv = '1' or data(3) = '0' then
621 if r.iside = '0' then
622 perm_ok := data(1) or (data(2) and not r.store);
624 -- no IAMR, so no KUEP support for now
625 -- deny execute permission if cache inhibited
626 perm_ok := data(0) and not data(5);
629 rc_ok := data(8) and (data(7) or not r.store);
630 if perm_ok = '1' and rc_ok = '1' then
631 v.state := RADIX_LOAD_TLB;
633 v.state := RADIX_FINISH;
634 v.perm_err := not perm_ok;
635 -- permission error takes precedence over RC error
636 v.rc_error := perm_ok;
639 # decode mode into something that matches microwatt equivalent code
640 instr_fetch
, store
= 0, 0
643 if mode
== 'EXECUTE':
646 # check permissions and RC bits
648 if priv
== 1 or data
[60] == 0:
650 perm_ok
= data
[62] |
(data
[61] & (store
== 0))
651 # no IAMR, so no KUEP support for now
652 # deny execute permission if cache inhibited
653 perm_ok
= data
[63] & ~data
[58]
654 rc_ok
= data
[55] & (data
[56] |
(store
== 0))
655 if perm_ok
== 1 and rc_ok
== 1:
658 return "perm_err" if perm_ok
== 0 else "rc_err"
660 def _get_prtable_addr(self
, shift
, prtbl
, addr
, pid
):
662 if r.addr(63) = '1' then
663 effpid := x"00000000";
667 x"00" & r.prtbl(55 downto 36) &
668 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
669 (effpid(31 downto 8) and finalmask(23 downto 0))) &
670 effpid(7 downto 0) & "0000";
672 print ("_get_prtable_addr", shift
, prtbl
, addr
, pid
)
673 finalmask
= genmask(shift
, 44)
674 finalmask24
= finalmask
[20:44]
675 if addr
[0].value
== 1:
676 effpid
= SelectableInt(0, 32)
678 effpid
= pid
#self.pid # TODO, check on this
679 zero8
= SelectableInt(0, 8)
680 zero4
= SelectableInt(0, 4)
681 res
= selectconcat(zero8
,
683 (prtbl
[28:52] & ~finalmask24
) |
#
684 (effpid
[0:24] & finalmask24
), #
690 def _get_pgtable_addr(self
, mask_size
, pgbase
, addrsh
):
692 x"00" & r.pgbase(55 downto 19) &
693 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
696 mask16
= genmask(mask_size
+5, 16)
697 zero8
= SelectableInt(0, 8)
698 zero3
= SelectableInt(0, 3)
699 res
= selectconcat(zero8
,
701 (pgbase
[45:61] & ~mask16
) |
#
707 def _get_pte(self
, shift
, addr
, pde
):
710 ((r.pde(55 downto 12) and not finalmask) or
711 (r.addr(55 downto 12) and finalmask))
712 & r.pde(11 downto 0);
715 finalmask
= genmask(shift
, 44)
716 zero8
= SelectableInt(0, 8)
717 rpn
= pde
[8:52] # RPN = Real Page Number
718 abits
= addr
[8:52] # non-masked address bits
719 print(" get_pte RPN", hex(rpn
.value
))
720 print(" abits", hex(abits
.value
))
721 print(" shift", shift
.value
)
722 print(" finalmask", bin(finalmask
.value
))
723 res
= selectconcat(zero8
,
724 (rpn
& ~finalmask
) |
#
725 (abits
& finalmask
), #
731 class TestRadixMMU(unittest
.TestCase
):
733 def test_genmask(self
):
734 shift
= SelectableInt(5, 6)
735 mask
= genmask(shift
, 43)
736 print (" mask", bin(mask
.value
))
738 self
.assertEqual(mask
.value
, 0b11111, "mask should be 5 1s")
741 inp
= SelectableInt(0x40000000000300ad, 64)
744 print("rtdb",rtdb
,bin(rtdb
.value
))
745 self
.assertEqual(rtdb
.value
,0x300,"rtdb should be 0x300")
747 result
= selectconcat(rtdb
,SelectableInt(0,8))
748 print("result",result
)
750 def test_get_pgtable_addr(self
):
754 dut
= RADIX(mem
, caller
)
757 pgbase
= SelectableInt(0,64)
758 addrsh
= SelectableInt(0,16)
759 ret
= dut
._get
_pgtable
_addr
(mask_size
, pgbase
, addrsh
)
761 self
.assertEqual(ret
, 0, "pgtbl_addr should be 0")
763 def test_walk_tree_1(self
):
766 # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
773 # set up dummy minimal ISACaller
774 spr
= {'DSISR': SelectableInt(0, 64),
775 'DAR': SelectableInt(0, 64),
776 'PIDR': SelectableInt(0, 64),
777 'PRTBL': SelectableInt(prtbl
, 64)
779 # set problem state == 0 (other unit tests, set to 1)
780 msr
= SelectableInt(0, 64)
782 class ISACaller
: pass
787 shift
= SelectableInt(5, 6)
788 mask
= genmask(shift
, 43)
789 print (" mask", bin(mask
.value
))
791 mem
= Mem(row_bytes
=8, initial_mem
=testmem
)
792 mem
= RADIX(mem
, caller
)
793 # -----------------------------------------------
794 # |/|RTS1|/| RPDB | RTS2 | RPDS |
795 # -----------------------------------------------
796 # |0|1 2|3|4 55|56 58|59 63|
797 data
= SelectableInt(0, 64)
800 data
[59:64] = 0b01101 # mask
802 (rts
, mbits
, pgbase
) = mem
._decode
_prte
(data
)
803 print (" rts", bin(rts
.value
), rts
.bits
)
804 print (" mbits", bin(mbits
.value
), mbits
.bits
)
805 print (" pgbase", hex(pgbase
.value
), pgbase
.bits
)
806 addr
= SelectableInt(0x1000, 64)
807 check
= mem
._segment
_check
(addr
, mbits
, shift
)
808 print (" segment check", check
)
810 print("walking tree")
811 addr
= SelectableInt(testaddr
,64)
816 result
= mem
._walk
_tree
(addr
, mode
)
817 print(" walking tree result", result
)
818 print("should be", testresult
)
819 self
.assertEqual(result
.value
, expected
,
820 "expected 0x%x got 0x%x" % (expected
,
823 def test_walk_tree_2(self
):
825 # test address slightly different
832 # set up dummy minimal ISACaller
833 spr
= {'DSISR': SelectableInt(0, 64),
834 'DAR': SelectableInt(0, 64),
835 'PIDR': SelectableInt(0, 64),
836 'PRTBL': SelectableInt(prtbl
, 64)
838 # set problem state == 0 (other unit tests, set to 1)
839 msr
= SelectableInt(0, 64)
841 class ISACaller
: pass
846 shift
= SelectableInt(5, 6)
847 mask
= genmask(shift
, 43)
848 print (" mask", bin(mask
.value
))
850 mem
= Mem(row_bytes
=8, initial_mem
=testmem2
)
851 mem
= RADIX(mem
, caller
)
852 # -----------------------------------------------
853 # |/|RTS1|/| RPDB | RTS2 | RPDS |
854 # -----------------------------------------------
855 # |0|1 2|3|4 55|56 58|59 63|
856 data
= SelectableInt(0, 64)
859 data
[59:64] = 0b01101 # mask
861 (rts
, mbits
, pgbase
) = mem
._decode
_prte
(data
)
862 print (" rts", bin(rts
.value
), rts
.bits
)
863 print (" mbits", bin(mbits
.value
), mbits
.bits
)
864 print (" pgbase", hex(pgbase
.value
), pgbase
.bits
)
865 addr
= SelectableInt(0x1000, 64)
866 check
= mem
._segment
_check
(addr
, mbits
, shift
)
867 print (" segment check", check
)
869 print("walking tree")
870 addr
= SelectableInt(testaddr
,64)
875 result
= mem
._walk
_tree
(addr
, mode
)
876 print(" walking tree result", result
)
877 print("should be", testresult
)
878 self
.assertEqual(result
.value
, expected
,
879 "expected 0x%x got 0x%x" % (expected
,
883 if __name__
== '__main__':