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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22
23 import math
24 import sys
25
26 # very quick, TODO move to SelectableInt utils later
27 def genmask(shift, size):
28 res = SelectableInt(0, size)
29 for i in range(size):
30 if i < shift:
31 res[size-1-i] = SelectableInt(1, 1)
32 return res
33
34 """
35 Get Root Page
36
37 //Accessing 2nd double word of partition table (pate1)
38 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
39 // PTCR Layout
40 // ====================================================
41 // -----------------------------------------------
42 // | /// | PATB | /// | PATS |
43 // -----------------------------------------------
44 // 0 4 51 52 58 59 63
45 // PATB[4:51] holds the base address of the Partition Table,
46 // right shifted by 12 bits.
47 // This is because the address of the Partition base is
48 // 4k aligned. Hence, the lower 12bits, which are always
49 // 0 are ommitted from the PTCR.
50 //
51 // Thus, The Partition Table Base is obtained by (PATB << 12)
52 //
53 // PATS represents the partition table size right-shifted by 12 bits.
54 // The minimal size of the partition table is 4k.
55 // Thus partition table size = (1 << PATS + 12).
56 //
57 // Partition Table
58 // ====================================================
59 // 0 PATE0 63 PATE1 127
60 // |----------------------|----------------------|
61 // | | |
62 // |----------------------|----------------------|
63 // | | |
64 // |----------------------|----------------------|
65 // | | | <-- effLPID
66 // |----------------------|----------------------|
67 // .
68 // .
69 // .
70 // |----------------------|----------------------|
71 // | | |
72 // |----------------------|----------------------|
73 //
74 // The effective LPID forms the index into the Partition Table.
75 //
76 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
77 // corresponding to that partition.
78 //
79 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
80 //
81 // PATE0 Layout
82 // -----------------------------------------------
83 // |1|RTS1|/| RPDB | RTS2 | RPDS |
84 // -----------------------------------------------
85 // 0 1 2 3 4 55 56 58 59 63
86 //
87 // HR[0] : For Radix Page table, first bit should be 1.
88 // RTS1[1:2] : Gives one fragment of the Radix treesize
89 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
90 // RTS = (RTS1 << 3 + RTS2) + 31.
91 //
92 // RPDB[4:55] = Root Page Directory Base.
93 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
94 // Thus, Root page directory size = 1 << (RPDS + 3).
95 // Note: RPDS >= 5.
96 //
97 // PATE1 Layout
98 // -----------------------------------------------
99 // |///| PRTB | // | PRTS |
100 // -----------------------------------------------
101 // 0 3 4 51 52 58 59 63
102 //
103 // PRTB[4:51] = Process Table Base. This is aligned to size.
104 // PRTS[59: 63] = Process Table Size right shifted by 12.
105 // Minimal size of the process table is 4k.
106 // Process Table Size = (1 << PRTS + 12).
107 // Note: PRTS <= 24.
108 //
109 // Computing the size aligned Process Table Base:
110 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
111 // Thus, the lower 12+PRTS bits of table_base will
112 // be zero.
113
114
115 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
116 //
117 // Process Table
118 // ==========================
119 // 0 PRTE0 63 PRTE1 127
120 // |----------------------|----------------------|
121 // | | |
122 // |----------------------|----------------------|
123 // | | |
124 // |----------------------|----------------------|
125 // | | | <-- effPID
126 // |----------------------|----------------------|
127 // .
128 // .
129 // .
130 // |----------------------|----------------------|
131 // | | |
132 // |----------------------|----------------------|
133 //
134 // The effective Process id (PID) forms the index into the Process Table.
135 //
136 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
137 // corresponding to that process
138 //
139 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
140 //
141 // PRTE0 Layout
142 // -----------------------------------------------
143 // |/|RTS1|/| RPDB | RTS2 | RPDS |
144 // -----------------------------------------------
145 // 0 1 2 3 4 55 56 58 59 63
146 //
147 // RTS1[1:2] : Gives one fragment of the Radix treesize
148 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
149 // RTS = (RTS1 << 3 + RTS2) << 31,
150 // since minimal Radix Tree size is 4G.
151 //
152 // RPDB = Root Page Directory Base.
153 // RPDS = Root Page Directory Size right shifted by 3.
154 // Thus, Root page directory size = RPDS << 3.
155 // Note: RPDS >= 5.
156 //
157 // PRTE1 Layout
158 // -----------------------------------------------
159 // | /// |
160 // -----------------------------------------------
161 // 0 63
162 // All bits are reserved.
163
164
165 """
166
167 # see qemu/target/ppc/mmu-radix64.c for reference
168 class RADIX:
169 def __init__(self, mem, caller):
170 self.mem = mem
171 self.caller = caller
172 #TODO move to lookup
173 self.dsisr = self.caller.spr["DSISR"]
174 self.dar = self.caller.spr["DAR"]
175 self.pidr = self.caller.spr["PIDR"]
176 self.prtbl = self.caller.spr["PRTBL"]
177
178 # cached page table stuff
179 self.pgtbl0 = 0
180 self.pt0_valid = False
181 self.pgtbl3 = 0
182 self.pt3_valid = False
183
184 def __call__(self, addr, sz):
185 val = self.ld(addr.value, sz, swap=False)
186 print("RADIX memread", addr, sz, val)
187 return SelectableInt(val, sz*8)
188
189 def ld(self, address, width=8, swap=True, check_in_mem=False):
190 print("RADIX: ld from addr 0x%x width %d" % (address, width))
191
192 shift = SelectableInt(0, 32)
193 pte = self._walk_tree(address,shift)
194 # use pte to caclculate phys address
195 return self.mem.ld(address, width, swap, check_in_mem)
196
197 # XXX set SPRs on error
198
199 # TODO implement
200 def st(self, addr, v, width=8, swap=True):
201 print("RADIX: st to addr 0x%x width %d data %x" % (addr, width, v))
202
203 shift = SelectableInt(0, 32)
204 pte = self._walk_tree(addr,shift)
205
206 # use pte to caclculate phys address (addr)
207 return self.mem.st(addr, v, width, swap)
208
209 # XXX set SPRs on error
210
211 def memassign(self, addr, sz, val):
212 print("memassign", addr, sz, val)
213 self.st(addr.value, val.value, sz, swap=False)
214
215 def _next_level(self):
216 return True
217 ## DSISR_R_BADCONFIG
218 ## read_entry
219 ## DSISR_NOPTE
220 ## Prepare for next iteration
221
222 def _walk_tree(self, addr, shift):
223 """walk tree
224
225 // vaddr 64 Bit
226 // vaddr |-----------------------------------------------------|
227 // | Unused | Used |
228 // |-----------|-----------------------------------------|
229 // | 0000000 | usefulBits = X bits (typically 52) |
230 // |-----------|-----------------------------------------|
231 // | |<--Cursize---->| |
232 // | | Index | |
233 // | | into Page | |
234 // | | Directory | |
235 // |-----------------------------------------------------|
236 // | |
237 // V |
238 // PDE |---------------------------| |
239 // |V|L|//| NLB |///|NLS| |
240 // |---------------------------| |
241 // PDE = Page Directory Entry |
242 // [0] = V = Valid Bit |
243 // [1] = L = Leaf bit. If 0, then |
244 // [4:55] = NLB = Next Level Base |
245 // right shifted by 8 |
246 // [59:63] = NLS = Next Level Size |
247 // | NLS >= 5 |
248 // | V
249 // | |--------------------------|
250 // | | usfulBits = X-Cursize |
251 // | |--------------------------|
252 // |---------------------><--NLS-->| |
253 // | Index | |
254 // | into | |
255 // | PDE | |
256 // |--------------------------|
257 // |
258 // If the next PDE obtained by |
259 // (NLB << 8 + 8 * index) is a |
260 // nonleaf, then repeat the above. |
261 // |
262 // If the next PDE is a leaf, |
263 // then Leaf PDE structure is as |
264 // follows |
265 // |
266 // |
267 // Leaf PDE |
268 // |------------------------------| |----------------|
269 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
270 // |------------------------------| |----------------|
271 // [0] = V = Valid Bit |
272 // [1] = L = Leaf Bit = 1 if leaf |
273 // PDE |
274 // [2] = Sw = Sw bit 0. |
275 // [7:51] = RPN = Real Page Number, V
276 // real_page = RPN << 12 -------------> Logical OR
277 // [52:54] = Sw Bits 1:3 |
278 // [55] = R = Reference |
279 // [56] = C = Change V
280 // [58:59] = Att = Physical Address
281 // 0b00 = Normal Memory
282 // 0b01 = SAO
283 // 0b10 = Non Idenmpotent
284 // 0b11 = Tolerant I/O
285 // [60:63] = Encoded Access
286 // Authority
287 //
288 """
289 # get sprs
290 print("_walk_tree")
291 pidr = self.caller.spr["PIDR"]
292 prtbl = self.caller.spr["PRTBL"]
293 print(pidr)
294 print(prtbl)
295 #prtable_addr = self._get_prtable_addr(shift, prtbl, addr, pidr)
296 #print("prtable_addr",prtable_addr)
297
298 # TODO read root entry from process table first
299
300 # walk tree starts on prtbl
301 while True:
302 ret = self._next_level()
303 if ret: return ret
304
305 def _decode_prte(self, data):
306 """PRTE0 Layout
307 -----------------------------------------------
308 |/|RTS1|/| RPDB | RTS2 | RPDS |
309 -----------------------------------------------
310 0 1 2 3 4 55 56 58 59 63
311 """
312 # note that SelectableInt does big-endian! so the indices
313 # below *directly* match the spec, unlike microwatt which
314 # has to turn them around (to LE)
315 zero = SelectableInt(0, 1)
316 rts = selectconcat(zero,
317 data[56:59], # RTS2
318 data[1:3], # RTS1
319 )
320 masksize = data[59:64] # RPDS
321 mbits = selectconcat(zero, masksize)
322 pgbase = selectconcat(data[8:56], # part of RPDB
323 SelectableInt(0, 16),)
324
325 return (rts, mbits, pgbase)
326
327 def _segment_check(self, addr, mbits, shift):
328 """checks segment valid
329 mbits := '0' & r.mask_size;
330 v.shift := r.shift + (31 - 12) - mbits;
331 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
332 if r.addr(63) /= r.addr(62) or nonzero = '1' then
333 v.state := RADIX_FINISH;
334 v.segerror := '1';
335 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
336 v.state := RADIX_FINISH;
337 v.badtree := '1';
338 else
339 v.state := RADIX_LOOKUP;
340 """
341 # note that SelectableInt does big-endian! so the indices
342 # below *directly* match the spec, unlike microwatt which
343 # has to turn them around (to LE)
344 mask = genmask(shift, 44)
345 nonzero = addr[1:32] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
346 print ("RADIX _segment_check nonzero", bin(nonzero.value))
347 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
348 if addr[0] != addr[1] or nonzero == 1:
349 return "segerror"
350 limit = shift + (31 - 12)
351 if mbits < 5 or mbits > 16 or mbits > limit:
352 return "badtree"
353 new_shift = shift + (31 - 12) - mbits
354 return new_shift
355
356 def _check_perms(self, data, priv, iside, store):
357 """check page permissions
358 // Leaf PDE |
359 // |------------------------------| |----------------|
360 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
361 // |------------------------------| |----------------|
362 // [0] = V = Valid Bit |
363 // [1] = L = Leaf Bit = 1 if leaf |
364 // PDE |
365 // [2] = Sw = Sw bit 0. |
366 // [7:51] = RPN = Real Page Number, V
367 // real_page = RPN << 12 -------------> Logical OR
368 // [52:54] = Sw Bits 1:3 |
369 // [55] = R = Reference |
370 // [56] = C = Change V
371 // [58:59] = Att = Physical Address
372 // 0b00 = Normal Memory
373 // 0b01 = SAO
374 // 0b10 = Non Idenmpotent
375 // 0b11 = Tolerant I/O
376 // [60:63] = Encoded Access
377 // Authority
378 //
379 -- test leaf bit
380 -- check permissions and RC bits
381 perm_ok := '0';
382 if r.priv = '1' or data(3) = '0' then
383 if r.iside = '0' then
384 perm_ok := data(1) or (data(2) and not r.store);
385 else
386 -- no IAMR, so no KUEP support for now
387 -- deny execute permission if cache inhibited
388 perm_ok := data(0) and not data(5);
389 end if;
390 end if;
391 rc_ok := data(8) and (data(7) or not r.store);
392 if perm_ok = '1' and rc_ok = '1' then
393 v.state := RADIX_LOAD_TLB;
394 else
395 v.state := RADIX_FINISH;
396 v.perm_err := not perm_ok;
397 -- permission error takes precedence over RC error
398 v.rc_error := perm_ok;
399 end if;
400 """
401 # check permissions and RC bits
402 perm_ok = 0
403 if priv == 1 or data[60] == 0:
404 if iside == 0:
405 perm_ok = data[62] | (data[61] & (store == 0))
406 # no IAMR, so no KUEP support for now
407 # deny execute permission if cache inhibited
408 perm_ok = data[63] & ~data[58]
409 rc_ok = data[55] & (data[56] | (store == 0))
410 if perm_ok == 1 and rc_ok == 1:
411 return True
412 return "perm_err" if perm_ok == 0 else "rc_err"
413
414 def _get_prtable_addr(self, shift, prtbl, addr, pid):
415 """
416 if r.addr(63) = '1' then
417 effpid := x"00000000";
418 else
419 effpid := r.pid;
420 end if;
421 x"00" & r.prtbl(55 downto 36) &
422 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
423 (effpid(31 downto 8) and finalmask(23 downto 0))) &
424 effpid(7 downto 0) & "0000";
425 """
426 finalmask = genmask(shift, 44)
427 finalmask24 = finalmask[20:44]
428 if addr[0].value == 1:
429 effpid = SelectableInt(0, 32)
430 else:
431 effpid = self.pid[32:64] # TODO, check on this
432 zero16 = SelectableInt(0, 16)
433 zero4 = SelectableInt(0, 4)
434 res = selectconcat(zero16,
435 prtbl[8:28], #
436 (prtbl[28:52] & ~finalmask24) | #
437 (effpid[0:24] & finalmask24), #
438 effpid[24:32],
439 zero4
440 )
441 return res
442
443 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
444 """
445 x"00" & r.pgbase(55 downto 19) &
446 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
447 "000";
448 """
449 mask16 = genmask(mask_size+5, 16)
450 zero8 = SelectableInt(0, 8)
451 zero3 = SelectableInt(0, 3)
452 res = selectconcat(zero8,
453 pgbase[8:45], #
454 (prtbl[45:61] & ~mask16) | #
455 (addrsh & mask16), #
456 zero3
457 )
458 return res
459
460 def _get_pte(self, shift, addr, pde):
461 """
462 x"00" &
463 ((r.pde(55 downto 12) and not finalmask) or
464 (r.addr(55 downto 12) and finalmask))
465 & r.pde(11 downto 0);
466 """
467 finalmask = genmask(shift, 44)
468 zero8 = SelectableInt(0, 8)
469 res = selectconcat(zero8,
470 (pde[8:52] & ~finalmask) | #
471 (addr[8:52] & finalmask), #
472 pde[52:64],
473 )
474 return res
475
476
477 # very quick test of maskgen function (TODO, move to util later)
478 if __name__ == '__main__':
479 # set up dummy minimal ISACaller
480 spr = {'DSISR': SelectableInt(0, 64),
481 'DAR': SelectableInt(0, 64),
482 'PIDR': SelectableInt(0, 64),
483 'PRTBL': SelectableInt(0, 64)
484 }
485 class ISACaller: pass
486 caller = ISACaller()
487 caller.spr = spr
488
489 shift = SelectableInt(5, 6)
490 mask = genmask(shift, 43)
491 print (" mask", bin(mask.value))
492
493 mem = Mem(row_bytes=8)
494 mem = RADIX(mem, caller)
495 # -----------------------------------------------
496 # |/|RTS1|/| RPDB | RTS2 | RPDS |
497 # -----------------------------------------------
498 # |0|1 2|3|4 55|56 58|59 63|
499 data = SelectableInt(0, 64)
500 data[1:3] = 0b01
501 data[56:59] = 0b11
502 data[59:64] = 0b01101 # mask
503 data[55] = 1
504 (rts, mbits, pgbase) = mem._decode_prte(data)
505 print (" rts", bin(rts.value), rts.bits)
506 print (" mbits", bin(mbits.value), mbits.bits)
507 print (" pgbase", hex(pgbase.value), pgbase.bits)
508 addr = SelectableInt(0x1000, 64)
509 check = mem._segment_check(addr, mbits, shift)
510 print (" segment check", check)