0e9c113185e53b053b1b6976948b26370e998d1f
[soc.git] / src / soc / decoder / isa / test_caller.py
1 from nmigen import Module, Signal
2 from nmigen.back.pysim import Simulator, Delay
3 from nmigen.test.utils import FHDLTestCase
4 import unittest
5 from soc.decoder.isa.caller import ISACaller
6 from soc.decoder.power_decoder import (create_pdecode)
7 from soc.decoder.power_decoder2 import (PowerDecode2)
8 from soc.simulator.program import Program
9 from soc.decoder.isa.caller import ISACaller, inject
10 from soc.decoder.selectable_int import SelectableInt
11 from soc.decoder.orderedset import OrderedSet
12 from soc.decoder.isa.all import ISA
13
14
15 class Register:
16 def __init__(self, num):
17 self.num = num
18
19
20 class DecoderTestCase(FHDLTestCase):
21
22 def run_tst(self, generator, initial_regs):
23 m = Module()
24 comb = m.d.comb
25 instruction = Signal(32)
26
27 pdecode = create_pdecode()
28 simulator = ISA(pdecode, initial_regs)
29
30 m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
31 comb += pdecode2.dec.raw_opcode_in.eq(instruction)
32 sim = Simulator(m)
33 gen = generator.generate_instructions()
34
35 def process():
36 for ins, code in zip(gen, generator.assembly.splitlines()):
37
38 print("0x{:X}".format(ins & 0xffffffff))
39 print(code)
40
41 # ask the decoder to decode this binary data (endian'd)
42 yield pdecode2.dec.bigendian.eq(0) # little / big?
43 yield instruction.eq(ins) # raw binary instr.
44 yield Delay(1e-6)
45 opname = code.split(' ')[0]
46 yield from simulator.call(opname)
47
48 sim.add_process(process)
49 with sim.write_vcd("simulator.vcd", "simulator.gtkw",
50 traces=[]):
51 sim.run()
52 return simulator
53
54 def test_add(self):
55 lst = ["add 1, 3, 2"]
56 initial_regs = [0] * 32
57 initial_regs[3] = 0x1234
58 initial_regs[2] = 0x4321
59 with Program(lst) as program:
60 sim = self.run_test_program(program, initial_regs)
61 self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
62
63 def test_addi(self):
64 lst = ["addi 3, 0, 0x1234",
65 "addi 2, 0, 0x4321",
66 "add 1, 3, 2"]
67 with Program(lst) as program:
68 sim = self.run_test_program(program)
69 print(sim.gpr(1))
70 self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
71
72 def test_load_store(self):
73 lst = ["addi 1, 0, 0x0010",
74 "addi 2, 0, 0x1234",
75 "stw 2, 0(1)",
76 "lwz 3, 0(1)"]
77 with Program(lst) as program:
78 sim = self.run_test_program(program)
79 print(sim.gpr(1))
80 self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
81
82 def test_addpcis(self):
83 lst = ["addpcis 1, 0x1",
84 "addpcis 2, 0x1",
85 "addpcis 3, 0x1"]
86 with Program(lst) as program:
87 sim = self.run_test_program(program)
88 self.assertEqual(sim.gpr(1), SelectableInt(0x10004, 64))
89 self.assertEqual(sim.gpr(2), SelectableInt(0x10008, 64))
90 self.assertEqual(sim.gpr(3), SelectableInt(0x1000c, 64))
91
92 def run_test_program(self, prog, initial_regs=[0] * 32):
93 simulator = self.run_tst(prog, initial_regs)
94 simulator.gpr.dump()
95 return simulator
96
97
98 if __name__ == "__main__":
99 unittest.main()