1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
3 from nmigen
.test
.utils
import FHDLTestCase
5 from soc
.decoder
.isa
.caller
import ISACaller
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
8 from soc
.simulator
.program
import Program
9 from soc
.decoder
.isa
.caller
import ISACaller
, inject
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.decoder
.orderedset
import OrderedSet
12 from soc
.decoder
.isa
.all
import ISA
16 def __init__(self
, num
):
20 class DecoderTestCase(FHDLTestCase
):
22 def run_tst(self
, generator
, initial_regs
):
25 instruction
= Signal(32)
27 pdecode
= create_pdecode()
29 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
30 simulator
= ISA(pdecode2
, initial_regs
)
31 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
33 gen
= generator
.generate_instructions()
36 instructions
= list(zip(gen
, generator
.assembly
.splitlines()))
38 index
= simulator
.pc
.CIA
.value
//4
39 while index
< len(instructions
):
40 ins
, code
= instructions
[index
]
42 print("0x{:X}".format(ins
& 0xffffffff))
45 # ask the decoder to decode this binary data (endian'd)
46 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
47 yield instruction
.eq(ins
) # raw binary instr.
49 opname
= code
.split(' ')[0]
50 yield from simulator
.call(opname
)
51 index
= simulator
.pc
.CIA
.value
//4
53 sim
.add_process(process
)
54 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
61 initial_regs
= [0] * 32
62 initial_regs
[3] = 0x1234
63 initial_regs
[2] = 0x4321
64 with
Program(lst
) as program
:
65 sim
= self
.run_tst_program(program
, initial_regs
)
66 self
.assertEqual(sim
.gpr(1), SelectableInt(0x5555, 64))
69 lst
= ["addi 3, 0, 0x1234",
72 with
Program(lst
) as program
:
73 sim
= self
.run_tst_program(program
)
75 self
.assertEqual(sim
.gpr(1), SelectableInt(0x5555, 64))
77 def test_load_store(self
):
78 lst
= ["addi 1, 0, 0x0010",
82 with
Program(lst
) as program
:
83 sim
= self
.run_tst_program(program
)
85 self
.assertEqual(sim
.gpr(3), SelectableInt(0x1234, 64))
87 def test_addpcis(self
):
88 lst
= ["addpcis 1, 0x1",
91 with
Program(lst
) as program
:
92 sim
= self
.run_tst_program(program
)
93 self
.assertEqual(sim
.gpr(1), SelectableInt(0x10004, 64))
94 self
.assertEqual(sim
.gpr(2), SelectableInt(0x10008, 64))
95 self
.assertEqual(sim
.gpr(3), SelectableInt(0x1000c, 64))
97 def test_branch(self
):
98 lst
= ["ba 0xc", # branch to line 4
99 "addi 1, 0, 0x1234", # Should never execute
100 "ba 0x1000", # exit the program
101 "addi 2, 0, 0x1234", # line 4
102 "ba 0x8"] # branch to line 3
103 with
Program(lst
) as program
:
104 sim
= self
.run_tst_program(program
)
105 self
.assertEqual(sim
.pc
.CIA
, SelectableInt(0x1000, 64))
106 self
.assertEqual(sim
.gpr(1), SelectableInt(0x0, 64))
107 self
.assertEqual(sim
.gpr(2), SelectableInt(0x1234, 64))
109 def test_branch_link(self
):
115 with
Program(lst
) as program
:
116 sim
= self
.run_tst_program(program
)
117 self
.assertEqual(sim
.spr
['LR'], SelectableInt(0x4, 64))
119 def test_branch_ctr(self
):
120 lst
= ["addi 1, 0, 0x10", # target of jump
121 "mtspr 9, 1", # mtctr 1
122 "bcctr 20, 0, 0", # bctr
123 "addi 2, 0, 0x1", # should never execute
124 "addi 1, 0, 0x1234"] # target of ctr
125 with
Program(lst
) as program
:
126 sim
= self
.run_tst_program(program
)
127 self
.assertEqual(sim
.spr
['CTR'], SelectableInt(0x10, 64))
128 self
.assertEqual(sim
.gpr(1), SelectableInt(0x1234, 64))
129 self
.assertEqual(sim
.gpr(2), SelectableInt(0, 64))
131 def test_branch_cond(self
):
133 lst
= [f
"addi 1, 0, {i}", # set r1 to i
134 "cmpi cr0, 1, 1, 10", # compare r1 with 10 and store to cr0
135 "bc 12, 2, 0x8", # beq 0x8 -
136 # branch if r1 equals 10 to the nop below
137 "addi 2, 0, 0x1234", # if r1 == 10 this shouldn't execute
138 "or 0, 0, 0"] # branch target
139 with
Program(lst
) as program
:
140 sim
= self
.run_tst_program(program
)
142 self
.assertEqual(sim
.gpr(2), SelectableInt(0, 64))
144 self
.assertEqual(sim
.gpr(2), SelectableInt(0x1234, 64))
146 def test_branch_loop(self
):
147 lst
= ["addi 1, 0, 0",
151 "cmpi cr0, 1, 1, 10",
153 with
Program(lst
) as program
:
154 sim
= self
.run_tst_program(program
)
156 self
.assertEqual(sim
.gpr(2), SelectableInt(0x37, 64))
159 def test_add_compare(self
):
160 lst
= ["addis 1, 0, 0xffff",
161 "addis 2, 0, 0xffff",
164 with
Program(lst
) as program
:
165 sim
= self
.run_tst_program(program
)
167 self
.assertEqual(sim
.gpr(3), SelectableInt(0x80000000, 64))
170 lst
= ["addis 1, 0, 0xffff",
171 "addis 2, 0, 0xffff",
174 with
Program(lst
) as program
:
175 sim
= self
.run_tst_program(program
)
176 self
.assertEqual(sim
.gpr(3), SelectableInt(0x20000000, 64))
178 def test_mtcrf(self
):
180 # 0x76540000 gives expected (3+4) (2+4) (1+4) (0+4) for
182 # The positions of the CR fields have been verified using
183 # QEMU and 'cmp crx, a, b' instructions
184 lst
= ["addis 1, 0, 0x7654",
185 "mtcrf %d, 1" % (1 << (7-i
)),
187 with
Program(lst
) as program
:
188 sim
= self
.run_tst_program(program
)
192 self
.assertEqual(sim
.cr
, SelectableInt(expected
<< ((7-i
)*4), 32))
193 # check CR[0]/1/2/3 as well
194 print("cr%d", sim
.crl
[i
])
195 self
.assertTrue(SelectableInt(expected
, 4) == sim
.crl
[i
])
197 def run_tst_program(self
, prog
, initial_regs
=[0] * 32):
198 simulator
= self
.run_tst(prog
, initial_regs
)
203 if __name__
== "__main__":