src/soc/decoder/isa/test_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.test.utils import FHDLTestCase
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.simulator.program import Program
   9 from soc.simulator.qemu import run_program
  10 from soc.decoder.isa.caller import ISACaller, inject
  11 from soc.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,)
  12 from soc.decoder.selectable_int import SelectableInt
  13 from soc.decoder.selectable_int import selectconcat as concat
  14 from soc.decoder.orderedset import OrderedSet
  15
  16 class fixedarith(ISACaller):
  17
  18     @inject
  19     def op_addi(self, RA):
  20         if RA == 0:
  21             RT = EXTS(SI)
  22         else:
  23             RT = RA + EXTS(SI)
  24         return (RT,)
  25
  26     instrs = {}
  27     instrs['addi'] = (op_addi, OrderedSet(['RA']),
  28                 OrderedSet(), OrderedSet(['RT']))
  29
  30
  31
  32 class Register:
  33     def __init__(self, num):
  34         self.num = num
  35
  36
  37 class DecoderTestCase(FHDLTestCase):
  38
  39     def run_tst(self, generator):
  40         m = Module()
  41         comb = m.d.comb
  42         instruction = Signal(32)
  43
  44         pdecode = create_pdecode()
  45         simulator = fixedarith(pdecode, [0] * 32)
  46
  47         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
  48         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
  49         sim = Simulator(m)
  50         gen = generator.generate_instructions()
  51
  52         def process():
  53             for ins, code in zip(gen, generator.assembly.splitlines()):
  54
  55                 print("0x{:X}".format(ins & 0xffffffff))
  56                 print(code)
  57
  58                 # ask the decoder to decode this binary data (endian'd)
  59                 yield pdecode2.dec.bigendian.eq(0)  # little / big?
  60                 yield instruction.eq(ins)          # raw binary instr.
  61                 yield Delay(1e-6)
  62                 opname = code.split(' ')[0]
  63                 yield from simulator.call(opname)
  64
  65         sim.add_process(process)
  66         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
  67                            traces=[]):
  68             sim.run()
  69         return simulator
  70
  71     def test_addi(self):
  72         lst = ["addi 1, 0, 0x1234"]
  73         with Program(lst) as program:
  74             self.run_test_program(program)
  75
  76     def run_test_program(self, prog):
  77         simulator = self.run_tst(prog)
  78         print(simulator.gpr)
  79
  80 if __name__ == "__main__":
  81     unittest.main()