src/soc/decoder/isa/test_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.test.utils import FHDLTestCase
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.simulator.program import Program
   9 from soc.simulator.qemu import run_program
  10 from soc.decoder.isa.caller import ISACaller, inject
  11 from soc.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,)
  12 from soc.decoder.selectable_int import SelectableInt
  13 from soc.decoder.selectable_int import selectconcat as concat
  14 from soc.decoder.orderedset import OrderedSet
  15
  16 class fixedarith(ISACaller):
  17
  18     @inject()
  19     def op_addi(self, RA):
  20         if RA == 0:
  21             RT = SI
  22         else:
  23             RT = RA + SI
  24         return (RT,)
  25     @inject()
  26     def op_add(self, RA, RB):
  27         RT = RA + RB
  28         return (RT,)
  29
  30     instrs = {}
  31     instrs['addi'] = (op_addi, OrderedSet(['RA']),
  32                 OrderedSet(), OrderedSet(['RT']))
  33     instrs['add'] = (op_add, OrderedSet(['RA', 'RB']),
  34                 OrderedSet(), OrderedSet(['RT']))
  35
  36
  37
  38 class Register:
  39     def __init__(self, num):
  40         self.num = num
  41
  42
  43 class DecoderTestCase(FHDLTestCase):
  44
  45     def run_tst(self, generator, initial_regs):
  46         m = Module()
  47         comb = m.d.comb
  48         instruction = Signal(32)
  49
  50         pdecode = create_pdecode()
  51         simulator = fixedarith(pdecode, initial_regs)
  52
  53         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
  54         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
  55         sim = Simulator(m)
  56         gen = generator.generate_instructions()
  57
  58         def process():
  59             for ins, code in zip(gen, generator.assembly.splitlines()):
  60
  61                 print("0x{:X}".format(ins & 0xffffffff))
  62                 print(code)
  63
  64                 # ask the decoder to decode this binary data (endian'd)
  65                 yield pdecode2.dec.bigendian.eq(0)  # little / big?
  66                 yield instruction.eq(ins)          # raw binary instr.
  67                 yield Delay(1e-6)
  68                 opname = code.split(' ')[0]
  69                 yield from simulator.call(opname)
  70
  71         sim.add_process(process)
  72         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
  73                            traces=[]):
  74             sim.run()
  75         return simulator
  76
  77     def test_add(self):
  78         lst = ["add 1, 3, 2"]
  79         initial_regs = [0] * 32
  80         initial_regs[3] = 0x1234
  81         initial_regs[2] = 0x4321
  82         with Program(lst) as program:
  83             sim = self.run_test_program(program, initial_regs)
  84             self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
  85
  86     def run_test_program(self, prog, initial_regs):
  87         simulator = self.run_tst(prog, initial_regs)
  88         simulator.gpr.dump()
  89         return simulator
  90
  91 if __name__ == "__main__":
  92     unittest.main()