f15634722f8f94a46e3d7ce473f34a695a89f2ce
[soc.git] / src / soc / decoder / isa / test_caller.py
1 from nmigen import Module, Signal
2 from nmigen.back.pysim import Simulator, Delay
3 from nmigen.test.utils import FHDLTestCase
4 import unittest
5 from soc.decoder.isa.caller import ISACaller
6 from soc.decoder.power_decoder import (create_pdecode)
7 from soc.decoder.power_decoder2 import (PowerDecode2)
8 from soc.simulator.program import Program
9 from soc.decoder.isa.caller import ISACaller, inject
10 from soc.decoder.selectable_int import SelectableInt
11 from soc.decoder.orderedset import OrderedSet
12 from soc.decoder.isa.all import ISA
13
14
15 class Register:
16 def __init__(self, num):
17 self.num = num
18
19
20 class DecoderTestCase(FHDLTestCase):
21
22 def run_tst(self, generator, initial_regs, initial_sprs={}):
23 m = Module()
24 comb = m.d.comb
25 instruction = Signal(32)
26
27 pdecode = create_pdecode()
28
29 m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
30 simulator = ISA(pdecode2, initial_regs, initial_sprs)
31 comb += pdecode2.dec.raw_opcode_in.eq(instruction)
32 sim = Simulator(m)
33 gen = generator.generate_instructions()
34
35 def process():
36 instructions = list(zip(gen, generator.assembly.splitlines()))
37
38 index = simulator.pc.CIA.value//4
39 while index < len(instructions):
40 ins, code = instructions[index]
41
42 print("0x{:X}".format(ins & 0xffffffff))
43 print(code)
44
45 # ask the decoder to decode this binary data (endian'd)
46 yield pdecode2.dec.bigendian.eq(0) # little / big?
47 yield instruction.eq(ins) # raw binary instr.
48 yield Delay(1e-6)
49 opname = code.split(' ')[0]
50 yield from simulator.call(opname)
51 index = simulator.pc.CIA.value//4
52
53 sim.add_process(process)
54 with sim.write_vcd("simulator.vcd", "simulator.gtkw",
55 traces=[]):
56 sim.run()
57 return simulator
58
59 def test_add(self):
60 lst = ["add 1, 3, 2"]
61 initial_regs = [0] * 32
62 initial_regs[3] = 0x1234
63 initial_regs[2] = 0x4321
64 with Program(lst) as program:
65 sim = self.run_tst_program(program, initial_regs)
66 self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
67
68 def test_addi(self):
69 lst = ["addi 3, 0, 0x1234",
70 "addi 2, 0, 0x4321",
71 "add 1, 3, 2"]
72 with Program(lst) as program:
73 sim = self.run_tst_program(program)
74 print(sim.gpr(1))
75 self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
76
77 def test_load_store(self):
78 lst = ["addi 1, 0, 0x0010",
79 "addi 2, 0, 0x1234",
80 "stw 2, 0(1)",
81 "lwz 3, 0(1)"]
82 with Program(lst) as program:
83 sim = self.run_tst_program(program)
84 print(sim.gpr(1))
85 self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
86
87 def test_addpcis(self):
88 lst = ["addpcis 1, 0x1",
89 "addpcis 2, 0x1",
90 "addpcis 3, 0x1"]
91 with Program(lst) as program:
92 sim = self.run_tst_program(program)
93 self.assertEqual(sim.gpr(1), SelectableInt(0x10004, 64))
94 self.assertEqual(sim.gpr(2), SelectableInt(0x10008, 64))
95 self.assertEqual(sim.gpr(3), SelectableInt(0x1000c, 64))
96
97 def test_branch(self):
98 lst = ["ba 0xc", # branch to line 4
99 "addi 1, 0, 0x1234", # Should never execute
100 "ba 0x1000", # exit the program
101 "addi 2, 0, 0x1234", # line 4
102 "ba 0x8"] # branch to line 3
103 with Program(lst) as program:
104 sim = self.run_tst_program(program)
105 self.assertEqual(sim.pc.CIA, SelectableInt(0x1000, 64))
106 self.assertEqual(sim.gpr(1), SelectableInt(0x0, 64))
107 self.assertEqual(sim.gpr(2), SelectableInt(0x1234, 64))
108
109 def test_branch_link(self):
110 lst = ["bl 0xc",
111 "addi 2, 1, 0x1234",
112 "ba 0x1000",
113 "addi 1, 0, 0x1234",
114 "bclr 20, 0, 0"]
115 with Program(lst) as program:
116 sim = self.run_tst_program(program)
117 self.assertEqual(sim.spr['LR'], SelectableInt(0x4, 64))
118
119 def test_branch_ctr(self):
120 lst = ["addi 1, 0, 0x10", # target of jump
121 "mtspr 9, 1", # mtctr 1
122 "bcctr 20, 0, 0", # bctr
123 "addi 2, 0, 0x1", # should never execute
124 "addi 1, 0, 0x1234"] # target of ctr
125 with Program(lst) as program:
126 sim = self.run_tst_program(program)
127 self.assertEqual(sim.spr['CTR'], SelectableInt(0x10, 64))
128 self.assertEqual(sim.gpr(1), SelectableInt(0x1234, 64))
129 self.assertEqual(sim.gpr(2), SelectableInt(0, 64))
130
131 def test_branch_cond(self):
132 for i in [0, 10]:
133 lst = [f"addi 1, 0, {i}", # set r1 to i
134 "cmpi cr0, 1, 1, 10", # compare r1 with 10 and store to cr0
135 "bc 12, 2, 0x8", # beq 0x8 -
136 # branch if r1 equals 10 to the nop below
137 "addi 2, 0, 0x1234", # if r1 == 10 this shouldn't execute
138 "or 0, 0, 0"] # branch target
139 with Program(lst) as program:
140 sim = self.run_tst_program(program)
141 if i == 10:
142 self.assertEqual(sim.gpr(2), SelectableInt(0, 64))
143 else:
144 self.assertEqual(sim.gpr(2), SelectableInt(0x1234, 64))
145
146 def test_branch_loop(self):
147 lst = ["addi 1, 0, 0",
148 "addi 1, 0, 0",
149 "addi 1, 1, 1",
150 "add 2, 2, 1",
151 "cmpi cr0, 1, 1, 10",
152 "bc 12, 0, -0xc"]
153 with Program(lst) as program:
154 sim = self.run_tst_program(program)
155 # Verified with qemu
156 self.assertEqual(sim.gpr(2), SelectableInt(0x37, 64))
157
158 def test_branch_loop_ctr(self):
159 lst = ["addi 1, 0, 0",
160 "addi 2, 0, 7",
161 "mtspr 9, 2", # set ctr to 7
162 "addi 1, 1, 5",
163 "bc 16, 0, -0x4"] # bdnz to the addi above
164 with Program(lst) as program:
165 sim = self.run_tst_program(program)
166 # Verified with qemu
167 self.assertEqual(sim.gpr(1), SelectableInt(0x23, 64))
168
169
170
171 def test_add_compare(self):
172 lst = ["addis 1, 0, 0xffff",
173 "addis 2, 0, 0xffff",
174 "add. 1, 1, 2",
175 "mfcr 3"]
176 with Program(lst) as program:
177 sim = self.run_tst_program(program)
178 # Verified with QEMU
179 self.assertEqual(sim.gpr(3), SelectableInt(0x80000000, 64))
180
181 def test_cmp(self):
182 lst = ["addis 1, 0, 0xffff",
183 "addis 2, 0, 0xffff",
184 "cmp cr2, 0, 1, 2",
185 "mfcr 3"]
186 with Program(lst) as program:
187 sim = self.run_tst_program(program)
188 self.assertEqual(sim.gpr(3), SelectableInt(0x200000, 64))
189
190 def test_slw(self):
191 lst = ["slw 1, 3, 2"]
192 initial_regs = [0] * 32
193 initial_regs[3] = 0xdeadbeefcafebabe
194 initial_regs[2] = 5
195 with Program(lst) as program:
196 sim = self.run_tst_program(program, initial_regs)
197 self.assertEqual(sim.gpr(1), SelectableInt(0x5fd757c0, 64))
198
199 def test_srw(self):
200 lst = ["srw 1, 3, 2"]
201 initial_regs = [0] * 32
202 initial_regs[3] = 0xdeadbeefcafebabe
203 initial_regs[2] = 5
204 with Program(lst) as program:
205 sim = self.run_tst_program(program, initial_regs)
206 self.assertEqual(sim.gpr(1), SelectableInt(0x657f5d5, 64))
207
208 def test_rlwinm(self):
209 lst = ["rlwinm 3, 1, 5, 20, 6"]
210 initial_regs = [0] * 32
211 initial_regs[1] = -1
212 with Program(lst) as program:
213 sim = self.run_tst_program(program, initial_regs)
214 self.assertEqual(sim.gpr(3), SelectableInt(0xfffffffffe000fff, 64))
215
216 def test_rlwimi(self):
217 lst = ["rlwimi 3, 1, 5, 20, 6"]
218 initial_regs = [0] * 32
219 initial_regs[1] = 0xffffffffdeadbeef
220 initial_regs[3] = 0x12345678
221 with Program(lst) as program:
222 sim = self.run_tst_program(program, initial_regs)
223 self.assertEqual(sim.gpr(3), SelectableInt(0xd5b7ddfbd4345dfb, 64))
224
225 def test_rldic(self):
226 lst = ["rldic 3, 1, 5, 20"]
227 initial_regs = [0] * 32
228 initial_regs[1] = 0xdeadbeefcafec0de
229 with Program(lst) as program:
230 sim = self.run_tst_program(program, initial_regs)
231 self.assertEqual(sim.gpr(3), SelectableInt(0xdf95fd81bc0, 64))
232
233 def test_prty(self):
234 lst = ["prtyw 2, 1"]
235 initial_regs = [0] * 32
236 initial_regs[1] = 0xdeadbeeecaffc0de
237 with Program(lst) as program:
238 sim = self.run_tst_program(program, initial_regs)
239 self.assertEqual(sim.gpr(2), SelectableInt(0x100000001, 64))
240
241 def test_popcnt(self):
242 lst = ["popcntb 2, 1",
243 "popcntw 3, 1",
244 "popcntd 4, 1"
245 ]
246 initial_regs = [0] * 32
247 initial_regs[1] = 0xdeadbeefcafec0de
248 with Program(lst) as program:
249 sim = self.run_tst_program(program, initial_regs)
250 self.assertEqual(sim.gpr(2),
251 SelectableInt(0x605060704070206, 64))
252 self.assertEqual(sim.gpr(3),
253 SelectableInt(0x1800000013, 64))
254 self.assertEqual(sim.gpr(4),
255 SelectableInt(0x2b, 64))
256
257 def test_cntlz(self):
258 lst = ["cntlzd 2, 1",
259 "cntlzw 4, 3"]
260 initial_regs = [0] * 32
261 initial_regs[1] = 0x0000beeecaffc0de
262 initial_regs[3] = 0x0000000000ffc0de
263 with Program(lst) as program:
264 sim = self.run_tst_program(program, initial_regs)
265 self.assertEqual(sim.gpr(2), SelectableInt(16, 64))
266 self.assertEqual(sim.gpr(4), SelectableInt(8, 64))
267
268
269 def test_mtcrf(self):
270 for i in range(4):
271 # 0x76540000 gives expected (3+4) (2+4) (1+4) (0+4) for
272 # i=0, 1, 2, 3
273 # The positions of the CR fields have been verified using
274 # QEMU and 'cmp crx, a, b' instructions
275 lst = ["addis 1, 0, 0x7654",
276 "mtcrf %d, 1" % (1 << (7-i)),
277 ]
278 with Program(lst) as program:
279 sim = self.run_tst_program(program)
280 print("cr", sim.cr)
281 expected = (7-i)
282 # check CR itself
283 self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 32))
284 # check CR[0]/1/2/3 as well
285 print("cr%d", sim.crl[i])
286 self.assertTrue(SelectableInt(expected, 4) == sim.crl[i])
287
288 def run_tst_program(self, prog, initial_regs=[0] * 32):
289 simulator = self.run_tst(prog, initial_regs)
290 simulator.gpr.dump()
291 return simulator
292
293
294 if __name__ == "__main__":
295 unittest.main()