fb227396bfeb8da0b771ca4708293032ae3ac16f
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
3 from nmigen
.test
.utils
import FHDLTestCase
5 from soc
.decoder
.isa
.caller
import ISACaller
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
8 from soc
.simulator
.program
import Program
9 from soc
.simulator
.qemu
import run_program
10 from soc
.decoder
.isa
.caller
import ISACaller
, inject
11 from soc
.decoder
.helpers
import (EXTS64
, EXTZ64
, ROTL64
, ROTL32
, MASK
,)
12 from soc
.decoder
.selectable_int
import SelectableInt
13 from soc
.decoder
.selectable_int
import selectconcat
as concat
14 from soc
.decoder
.orderedset
import OrderedSet
16 class fixedarith(ISACaller
):
19 def op_addi(self
, RA
):
26 def op_add(self
, RA
, RB
):
31 instrs
['addi'] = (op_addi
, OrderedSet(['RA']),
32 OrderedSet(), OrderedSet(['RT']))
33 instrs
['add'] = (op_add
, OrderedSet(['RA', 'RB']),
34 OrderedSet(), OrderedSet(['RT']))
39 def __init__(self
, num
):
43 class DecoderTestCase(FHDLTestCase
):
45 def run_tst(self
, generator
, initial_regs
):
48 instruction
= Signal(32)
50 pdecode
= create_pdecode()
51 simulator
= fixedarith(pdecode
, initial_regs
)
53 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
54 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
56 gen
= generator
.generate_instructions()
59 for ins
, code
in zip(gen
, generator
.assembly
.splitlines()):
61 print("0x{:X}".format(ins
& 0xffffffff))
64 # ask the decoder to decode this binary data (endian'd)
65 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
66 yield instruction
.eq(ins
) # raw binary instr.
68 opname
= code
.split(' ')[0]
69 yield from simulator
.call(opname
)
71 sim
.add_process(process
)
72 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
79 initial_regs
= [0] * 32
80 initial_regs
[3] = 0x1234
81 initial_regs
[2] = 0x4321
82 with
Program(lst
) as program
:
83 sim
= self
.run_test_program(program
, initial_regs
)
84 self
.assertEqual(sim
.gpr(1), SelectableInt(0x5555, 64))
86 def run_test_program(self
, prog
, initial_regs
):
87 simulator
= self
.run_tst(prog
, initial_regs
)
91 if __name__
== "__main__":