1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
3 from nmigen
.test
.utils
import FHDLTestCase
5 from soc
.decoder
.isa
.caller
import ISACaller
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
8 from soc
.simulator
.program
import Program
9 from soc
.decoder
.isa
.caller
import ISACaller
, inject
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.decoder
.orderedset
import OrderedSet
12 from soc
.decoder
.isa
import ISA
16 def __init__(self
, num
):
20 class DecoderTestCase(FHDLTestCase
):
22 def run_tst(self
, generator
, initial_regs
):
25 instruction
= Signal(32)
27 pdecode
= create_pdecode()
28 simulator
= ISA(pdecode
, initial_regs
)
30 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
31 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
33 gen
= generator
.generate_instructions()
36 for ins
, code
in zip(gen
, generator
.assembly
.splitlines()):
38 print("0x{:X}".format(ins
& 0xffffffff))
41 # ask the decoder to decode this binary data (endian'd)
42 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
43 yield instruction
.eq(ins
) # raw binary instr.
45 opname
= code
.split(' ')[0]
46 yield from simulator
.call(opname
)
48 sim
.add_process(process
)
49 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
56 initial_regs
= [0] * 32
57 initial_regs
[3] = 0x1234
58 initial_regs
[2] = 0x4321
59 with
Program(lst
) as program
:
60 sim
= self
.run_test_program(program
, initial_regs
)
61 self
.assertEqual(sim
.gpr(1), SelectableInt(0x5555, 64))
63 def run_test_program(self
, prog
, initial_regs
):
64 simulator
= self
.run_tst(prog
, initial_regs
)
68 if __name__
== "__main__":