1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
3 from nmigen
.test
.utils
import FHDLTestCase
5 from soc
.decoder
.isa
.caller
import ISACaller
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
8 from soc
.simulator
.program
import Program
9 from soc
.simulator
.qemu
import run_program
10 from soc
.decoder
.isa
.caller
import ISACaller
, inject
11 from soc
.decoder
.helpers
import (EXTS64
, EXTZ64
, ROTL64
, ROTL32
, MASK
,)
12 from soc
.decoder
.selectable_int
import SelectableInt
13 from soc
.decoder
.selectable_int
import selectconcat
as concat
14 from soc
.decoder
.orderedset
import OrderedSet
16 class fixedarith(ISACaller
):
19 def op_addi(self
, RA
):
27 instrs
['addi'] = (op_addi
, OrderedSet(['RA']),
28 OrderedSet(), OrderedSet(['RT']))
33 def __init__(self
, num
):
37 class DecoderTestCase(FHDLTestCase
):
39 def run_tst(self
, generator
):
42 instruction
= Signal(32)
44 pdecode
= create_pdecode()
45 simulator
= ISACaller(pdecode
, [0] * 32)
47 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
48 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
50 gen
= generator
.generate_instructions()
55 print("0x{:X}".format(ins
& 0xffffffff))
57 # ask the decoder to decode this binary data (endian'd)
58 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
59 yield instruction
.eq(ins
) # raw binary instr.
61 yield from simulator
.execute_op(pdecode2
)
63 sim
.add_process(process
)
64 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
70 lst
= ["addi 1, 0, 0x1234",]
71 with
Program(lst
) as program
:
72 self
.run_test_program(program
)
74 def run_test_program(self
, prog
):
75 simulator
= self
.run_tst(prog
)
78 if __name__
== "__main__":