src/soc/decoder/isa/test_caller_svp64.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.simulator.program import Program
   9 from soc.decoder.isa.caller import ISACaller, SVP64State
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.decoder.orderedset import OrderedSet
  12 from soc.decoder.isa.all import ISA
  13 from soc.decoder.isa.test_caller import Register, run_tst
  14 from soc.sv.trans.svp64 import SVP64Asm
  15 from soc.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         for i in range(32):
  22             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  23
  24     def test_sv_add(self):
  25         # adds:
  26         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  27         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
  28         isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'
  29                        ])
  30         lst = list(isa)
  31         print ("listing", lst)
  32
  33         # initial values in GPR regfile
  34         initial_regs = [0] * 32
  35         initial_regs[9] = 0x1234
  36         initial_regs[10] = 0x1111
  37         initial_regs[5] = 0x4321
  38         initial_regs[6] = 0x2223
  39         # SVSTATE (in this case, VL=2)
  40         svstate = SVP64State()
  41         svstate.vl[0:7] = 2 # VL
  42         svstate.maxvl[0:7] = 2 # MAXVL
  43         print ("SVSTATE", bin(svstate.spr.asint()))
  44         # copy before running
  45         expected_regs = deepcopy(initial_regs)
  46         expected_regs[1] = 0x5555
  47         expected_regs[2] = 0x3334
  48
  49         with Program(lst, bigendian=False) as program:
  50             sim = self.run_tst_program(program, initial_regs, svstate)
  51             self._check_regs(sim, expected_regs)
  52
  53     def test_sv_add_2(self):
  54         # adds:
  55         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  56         #       r1 is scalar so ENDS EARLY
  57         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
  58                        ])
  59         lst = list(isa)
  60         print ("listing", lst)
  61
  62         # initial values in GPR regfile
  63         initial_regs = [0] * 32
  64         initial_regs[9] = 0x1234
  65         initial_regs[10] = 0x1111
  66         initial_regs[5] = 0x4321
  67         initial_regs[6] = 0x2223
  68         # SVSTATE (in this case, VL=2)
  69         svstate = SVP64State()
  70         svstate.vl[0:7] = 2 # VL
  71         svstate.maxvl[0:7] = 2 # MAXVL
  72         print ("SVSTATE", bin(svstate.spr.asint()))
  73         # copy before running
  74         expected_regs = deepcopy(initial_regs)
  75         expected_regs[1] = 0x5555
  76
  77         with Program(lst, bigendian=False) as program:
  78             sim = self.run_tst_program(program, initial_regs, svstate)
  79             self._check_regs(sim, expected_regs)
  80
  81     def test_sv_add_3(self):
  82         # adds:
  83         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  84         #       2 = 5 + 10  => 0x5432 = 0x4321+0x1111
  85         isa = SVP64Asm(['sv.add 1.v, 5, 9.v'
  86                        ])
  87         lst = list(isa)
  88         print ("listing", lst)
  89
  90         # initial values in GPR regfile
  91         initial_regs = [0] * 32
  92         initial_regs[9] = 0x1234
  93         initial_regs[10] = 0x1111
  94         initial_regs[5] = 0x4321
  95         initial_regs[6] = 0x2223
  96         # SVSTATE (in this case, VL=2)
  97         svstate = SVP64State()
  98         svstate.vl[0:7] = 2 # VL
  99         svstate.maxvl[0:7] = 2 # MAXVL
 100         print ("SVSTATE", bin(svstate.spr.asint()))
 101         # copy before running
 102         expected_regs = deepcopy(initial_regs)
 103         expected_regs[1] = 0x5555
 104         expected_regs[2] = 0x5432
 105
 106         with Program(lst, bigendian=False) as program:
 107             sim = self.run_tst_program(program, initial_regs, svstate)
 108             self._check_regs(sim, expected_regs)
 109
 110     def test_sv_add_vl_0(self):
 111         # adds:
 112         #       none because VL is zer0
 113         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
 114                        ])
 115         lst = list(isa)
 116         print ("listing", lst)
 117
 118         # initial values in GPR regfile
 119         initial_regs = [0] * 32
 120         initial_regs[9] = 0x1234
 121         initial_regs[10] = 0x1111
 122         initial_regs[5] = 0x4321
 123         initial_regs[6] = 0x2223
 124         # SVSTATE (in this case, VL=0)
 125         svstate = SVP64State()
 126         svstate.vl[0:7] = 0 # VL
 127         svstate.maxvl[0:7] = 0 # MAXVL
 128         print ("SVSTATE", bin(svstate.spr.asint()))
 129         # copy before running
 130         expected_regs = deepcopy(initial_regs)
 131
 132         with Program(lst, bigendian=False) as program:
 133             sim = self.run_tst_program(program, initial_regs, svstate)
 134             self._check_regs(sim, expected_regs)
 135
 136     def test_sv_add_cr(self):
 137         # adds when Rc=1:                               TODO CRs higher up
 138         #       1 = 5 + 9   => 0 = -1+1                 CR0=0b100
 139         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
 140         isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
 141                        ])
 142         lst = list(isa)
 143         print ("listing", lst)
 144
 145         # initial values in GPR regfile
 146         initial_regs = [0] * 32
 147         initial_regs[9] = 0xffffffffffffffff
 148         initial_regs[10] = 0x1111
 149         initial_regs[5] = 0x1
 150         initial_regs[6] = 0x2223
 151         # SVSTATE (in this case, VL=2)
 152         svstate = SVP64State()
 153         svstate.vl[0:7] = 2 # VL
 154         svstate.maxvl[0:7] = 2 # MAXVL
 155         print ("SVSTATE", bin(svstate.spr.asint()))
 156         # copy before running
 157         expected_regs = deepcopy(initial_regs)
 158         expected_regs[1] = 0
 159         expected_regs[2] = 0x3334
 160
 161         with Program(lst, bigendian=False) as program:
 162             sim = self.run_tst_program(program, initial_regs, svstate)
 163             # XXX TODO, these need to move to higher range (offset)
 164             cr0_idx = SVP64CROffs.CR0
 165             cr1_idx = SVP64CROffs.CR1
 166             CR0 = sim.crl[cr0_idx].get_range().value
 167             CR1 = sim.crl[cr1_idx].get_range().value
 168             print ("CR0", CR0)
 169             print ("CR1", CR1)
 170             self._check_regs(sim, expected_regs)
 171             self.assertEqual(CR0, SelectableInt(2, 4))
 172             self.assertEqual(CR1, SelectableInt(4, 4))
 173
 174     def run_tst_program(self, prog, initial_regs=None,
 175                               svstate=None):
 176         if initial_regs is None:
 177             initial_regs = [0] * 32
 178         simulator = run_tst(prog, initial_regs, svstate=svstate)
 179         simulator.gpr.dump()
 180         return simulator
 181
 182
 183 if __name__ == "__main__":
 184     unittest.main()