src/soc/decoder/isa/test_caller_svp64.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.simulator.program import Program
   9 from soc.decoder.isa.caller import ISACaller, SVP64State
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.decoder.orderedset import OrderedSet
  12 from soc.decoder.isa.all import ISA
  13 from soc.decoder.isa.test_caller import Register, run_tst
  14 from soc.sv.trans.svp64 import SVP64Asm
  15
  16
  17 class DecoderTestCase(FHDLTestCase):
  18
  19     def test_sv_add(self):
  20         isa = SVP64Asm(['sv.add 1, 2, 3'
  21                        ])
  22
  23         lst = list(isa)
  24         print ("listing", lst)
  25         initial_regs = [0] * 32
  26         initial_regs[3] = 0x1234
  27         initial_regs[2] = 0x4321
  28         svstate = SVP64State()
  29         svstate.vl[0:-1] = 2 # VL
  30         svstate.maxvl[0:-1] = 2 # MAXVL
  31         print ("SVSTATE", bin(svstate.spr.asint()))
  32         with Program(lst, bigendian=False) as program:
  33             sim = self.run_tst_program(program, initial_regs, svstate)
  34             self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
  35
  36     def run_tst_program(self, prog, initial_regs=[0] * 32,
  37                               svstate=None):
  38         simulator = run_tst(prog, initial_regs, svstate=svstate)
  39         simulator.gpr.dump()
  40         return simulator
  41
  42
  43 if __name__ == "__main__":
  44     unittest.main()