90f2d40996cec8a2a20a3dac569e80ab9557982a
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from soc
.decoder
.isa
.caller
import ISACaller
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
8 from soc
.simulator
.program
import Program
9 from soc
.decoder
.isa
.caller
import ISACaller
, SVP64State
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.decoder
.orderedset
import OrderedSet
12 from soc
.decoder
.isa
.all
import ISA
13 from soc
.decoder
.isa
.test_caller
import Register
, run_tst
14 from soc
.sv
.trans
.svp64
import SVP64Asm
17 class DecoderTestCase(FHDLTestCase
):
19 def test_sv_add(self
):
20 isa
= SVP64Asm(['sv.add 1, 5, 9'
24 print ("listing", lst
)
25 initial_regs
= [0] * 32
26 initial_regs
[9] = 0x1234
27 initial_regs
[10] = 0x1111
28 initial_regs
[5] = 0x4321
29 initial_regs
[6] = 0x2223
30 svstate
= SVP64State()
31 svstate
.vl
[0:7] = 2 # VL
32 svstate
.maxvl
[0:7] = 2 # MAXVL
33 print ("SVSTATE", bin(svstate
.spr
.asint()))
34 with
Program(lst
, bigendian
=False) as program
:
35 sim
= self
.run_tst_program(program
, initial_regs
, svstate
)
36 self
.assertEqual(sim
.gpr(1), SelectableInt(0x5555, 64))
38 def run_tst_program(self
, prog
, initial_regs
=[0] * 32,
40 simulator
= run_tst(prog
, initial_regs
, svstate
=svstate
)
45 if __name__
== "__main__":