src/soc/decoder/isa/test_caller_svp64.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.simulator.program import Program
   9 from soc.decoder.isa.caller import ISACaller, SVP64State
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.decoder.orderedset import OrderedSet
  12 from soc.decoder.isa.all import ISA
  13 from soc.decoder.isa.test_caller import Register, run_tst
  14 from soc.sv.trans.svp64 import SVP64Asm
  15
  16
  17 class DecoderTestCase(FHDLTestCase):
  18
  19     def test_sv_add(self):
  20         # adds:
  21         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  22         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
  23         isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'
  24                        ])
  25
  26         lst = list(isa)
  27         print ("listing", lst)
  28         initial_regs = [0] * 32
  29         initial_regs[9] = 0x1234
  30         initial_regs[10] = 0x1111
  31         initial_regs[5] = 0x4321
  32         initial_regs[6] = 0x2223
  33         svstate = SVP64State()
  34         svstate.vl[0:7] = 2 # VL
  35         svstate.maxvl[0:7] = 2 # MAXVL
  36         print ("SVSTATE", bin(svstate.spr.asint()))
  37         with Program(lst, bigendian=False) as program:
  38             sim = self.run_tst_program(program, initial_regs, svstate)
  39             self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
  40             self.assertEqual(sim.gpr(2), SelectableInt(0x3334, 64))
  41
  42     def test_sv_add_2(self):
  43         # adds:
  44         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  45         #       r1 is scalar so ENDS EARLY
  46         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
  47                        ])
  48
  49         lst = list(isa)
  50         print ("listing", lst)
  51         initial_regs = [0] * 32
  52         initial_regs[9] = 0x1234
  53         initial_regs[10] = 0x1111
  54         initial_regs[5] = 0x4321
  55         initial_regs[6] = 0x2223
  56         svstate = SVP64State()
  57         svstate.vl[0:7] = 2 # VL
  58         svstate.maxvl[0:7] = 2 # MAXVL
  59         print ("SVSTATE", bin(svstate.spr.asint()))
  60         with Program(lst, bigendian=False) as program:
  61             sim = self.run_tst_program(program, initial_regs, svstate)
  62             self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
  63             self.assertEqual(sim.gpr(2), SelectableInt(0, 64))
  64
  65     def test_sv_add_3(self):
  66         # adds:
  67         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  68         #       2 = 5 + 10  => 0x5432 = 0x4321+0x1111
  69         isa = SVP64Asm(['sv.add 1.v, 5, 9.v'
  70                        ])
  71
  72         lst = list(isa)
  73         print ("listing", lst)
  74         initial_regs = [0] * 32
  75         initial_regs[9] = 0x1234
  76         initial_regs[10] = 0x1111
  77         initial_regs[5] = 0x4321
  78         initial_regs[6] = 0x2223
  79         svstate = SVP64State()
  80         svstate.vl[0:7] = 2 # VL
  81         svstate.maxvl[0:7] = 2 # MAXVL
  82         print ("SVSTATE", bin(svstate.spr.asint()))
  83         with Program(lst, bigendian=False) as program:
  84             sim = self.run_tst_program(program, initial_regs, svstate)
  85             self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
  86             self.assertEqual(sim.gpr(2), SelectableInt(0x5432, 64))
  87
  88     def run_tst_program(self, prog, initial_regs=[0] * 32,
  89                               svstate=None):
  90         simulator = run_tst(prog, initial_regs, svstate=svstate)
  91         simulator.gpr.dump()
  92         return simulator
  93
  94
  95 if __name__ == "__main__":
  96     unittest.main()