src/soc/decoder/isa/test_caller_svp64.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.simulator.program import Program
   9 from soc.decoder.isa.caller import ISACaller, SVP64State
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.decoder.orderedset import OrderedSet
  12 from soc.decoder.isa.all import ISA
  13 from soc.decoder.isa.test_caller import Register, run_tst
  14 from soc.sv.trans.svp64 import SVP64Asm
  15 from copy import deepcopy
  16
  17 class DecoderTestCase(FHDLTestCase):
  18
  19     def _check_regs(self, sim, expected):
  20         for i in range(32):
  21             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  22
  23     def test_sv_add(self):
  24         # adds:
  25         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  26         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
  27         isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'
  28                        ])
  29
  30         lst = list(isa)
  31         print ("listing", lst)
  32         initial_regs = [0] * 32
  33         initial_regs[9] = 0x1234
  34         initial_regs[10] = 0x1111
  35         initial_regs[5] = 0x4321
  36         initial_regs[6] = 0x2223
  37         svstate = SVP64State()
  38         svstate.vl[0:7] = 2 # VL
  39         svstate.maxvl[0:7] = 2 # MAXVL
  40         print ("SVSTATE", bin(svstate.spr.asint()))
  41         # copy before running
  42         expected_regs = deepcopy(initial_regs)
  43         expected_regs[1] = 0x5555
  44         expected_regs[2] = 0x3334
  45
  46         with Program(lst, bigendian=False) as program:
  47             sim = self.run_tst_program(program, initial_regs, svstate)
  48             self._check_regs(sim, expected_regs)
  49
  50     def test_sv_add_2(self):
  51         # adds:
  52         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  53         #       r1 is scalar so ENDS EARLY
  54         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
  55                        ])
  56
  57         lst = list(isa)
  58         print ("listing", lst)
  59         initial_regs = [0] * 32
  60         initial_regs[9] = 0x1234
  61         initial_regs[10] = 0x1111
  62         initial_regs[5] = 0x4321
  63         initial_regs[6] = 0x2223
  64         svstate = SVP64State()
  65         svstate.vl[0:7] = 2 # VL
  66         svstate.maxvl[0:7] = 2 # MAXVL
  67         print ("SVSTATE", bin(svstate.spr.asint()))
  68         # copy before running
  69         expected_regs = deepcopy(initial_regs)
  70         expected_regs[1] = 0x5555
  71
  72         with Program(lst, bigendian=False) as program:
  73             sim = self.run_tst_program(program, initial_regs, svstate)
  74             self._check_regs(sim, expected_regs)
  75
  76     def test_sv_add_3(self):
  77         # adds:
  78         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  79         #       2 = 5 + 10  => 0x5432 = 0x4321+0x1111
  80         isa = SVP64Asm(['sv.add 1.v, 5, 9.v'
  81                        ])
  82
  83         lst = list(isa)
  84         print ("listing", lst)
  85         initial_regs = [0] * 32
  86         initial_regs[9] = 0x1234
  87         initial_regs[10] = 0x1111
  88         initial_regs[5] = 0x4321
  89         initial_regs[6] = 0x2223
  90         svstate = SVP64State()
  91         svstate.vl[0:7] = 2 # VL
  92         svstate.maxvl[0:7] = 2 # MAXVL
  93         print ("SVSTATE", bin(svstate.spr.asint()))
  94         # copy before running
  95         expected_regs = deepcopy(initial_regs)
  96         expected_regs[1] = 0x5555
  97         expected_regs[2] = 0x5432
  98
  99         with Program(lst, bigendian=False) as program:
 100             sim = self.run_tst_program(program, initial_regs, svstate)
 101             self._check_regs(sim, expected_regs)
 102
 103     def run_tst_program(self, prog, initial_regs=[0] * 32,
 104                               svstate=None):
 105         simulator = run_tst(prog, initial_regs, svstate=svstate)
 106         simulator.gpr.dump()
 107         return simulator
 108
 109
 110 if __name__ == "__main__":
 111     unittest.main()