c9d1391a424b8e2e59e2ca5d170a068d4e46bf6c
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from soc
.decoder
.isa
.caller
import ISACaller
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
8 from soc
.simulator
.program
import Program
9 from soc
.decoder
.isa
.caller
import ISACaller
, inject
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.decoder
.orderedset
import OrderedSet
12 from soc
.decoder
.isa
.all
import ISA
13 from soc
.decoder
.isa
.test_caller
import Register
, run_tst
14 from soc
.sv
.trans
.svp64
import SVP64Asm
17 class DecoderTestCase(FHDLTestCase
):
19 def test_sv_add(self
):
20 isa
= SVP64Asm(['sv.add 1, 2, 3'
24 print ("listing", lst
)
25 initial_regs
= [0] * 32
26 initial_regs
[3] = 0x1234
27 initial_regs
[2] = 0x4321
28 with
Program(lst
, bigendian
=False) as program
:
29 sim
= self
.run_tst_program(program
, initial_regs
)
30 self
.assertEqual(sim
.gpr(1), SelectableInt(0x5555, 64))
32 def run_tst_program(self
, prog
, initial_regs
=[0] * 32):
33 simulator
= run_tst(prog
, initial_regs
)
38 if __name__
== "__main__":