dcache: add debug output
[soc.git] / src / soc / decoder / isa / test_caller_svp64_predication.py
1 from nmigen import Module, Signal
2 from nmigen.back.pysim import Simulator, Delay, Settle
3 from nmutil.formaltest import FHDLTestCase
4 import unittest
5 from soc.decoder.isa.caller import ISACaller
6 from soc.decoder.power_decoder import (create_pdecode)
7 from soc.decoder.power_decoder2 import (PowerDecode2)
8 from soc.simulator.program import Program
9 from soc.decoder.isa.caller import ISACaller, SVP64State
10 from soc.decoder.selectable_int import SelectableInt
11 from soc.decoder.orderedset import OrderedSet
12 from soc.decoder.isa.all import ISA
13 from soc.decoder.isa.test_caller import Register, run_tst
14 from soc.sv.trans.svp64 import SVP64Asm
15 from soc.consts import SVP64CROffs
16 from copy import deepcopy
17
18 class DecoderTestCase(FHDLTestCase):
19
20 def _check_regs(self, sim, expected):
21 for i in range(32):
22 self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
23
24 def tst_sv_load_store(self):
25 lst = SVP64Asm(["addi 1, 0, 0x0010",
26 "addi 2, 0, 0x0008",
27 "addi 5, 0, 0x1234",
28 "addi 6, 0, 0x1235",
29 "svstw 5.v, 0(1.v)",
30 "svlwz 9.v, 0(1.v)"])
31 lst = list(lst)
32
33 # SVSTATE (in this case, VL=2)
34 svstate = SVP64State()
35 svstate.vl[0:7] = 2 # VL
36 svstate.maxvl[0:7] = 2 # MAXVL
37 print ("SVSTATE", bin(svstate.spr.asint()))
38
39 with Program(lst, bigendian=False) as program:
40 sim = self.run_tst_program(program, svstate=svstate)
41 print(sim.gpr(1))
42 self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
43 self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
44
45 def test_sv_extsw_intpred(self):
46 # extsb, integer twin-pred mask: source is ~r3 (0b01), dest r3 (0b10)
47 # works as follows, where any zeros indicate "skip element"
48 # - sources are 9 and 10
49 # - dests are 5 and 6
50 # - source mask says "pick first element from source (5)
51 # - dest mask says "pick *second* element from dest (10)
52 #
53 # therefore the operation that's carried out is:
54 # GPR(10) = extsb(GPR(5))
55 #
56 # this is a type of back-to-back VGATHER and VSCATTER but it applies
57 # to *operations*, not just MVs like in traditional Vector ISAs
58 # ascii graphic:
59 #
60 # reg num 0 1 2 3 4 5 6 7 8 9 10
61 # src ~r3=0b01 Y N
62 # |
63 # +-----+
64 # |
65 # dest r3=0b10 N Y
66
67 isa = SVP64Asm(['svextsb/sm=~r3/m=r3 5.v, 9.v'
68 ])
69 lst = list(isa)
70 print ("listing", lst)
71
72 # initial values in GPR regfile
73 initial_regs = [0] * 32
74 initial_regs[3] = 0b10 # predicate mask
75 initial_regs[9] = 0x91 # source ~r3 is 0b01 so this will be used
76 initial_regs[10] = 0x90 # this gets skipped
77 # SVSTATE (in this case, VL=2)
78 svstate = SVP64State()
79 svstate.vl[0:7] = 2 # VL
80 svstate.maxvl[0:7] = 2 # MAXVL
81 print ("SVSTATE", bin(svstate.spr.asint()))
82 # copy before running
83 expected_regs = deepcopy(initial_regs)
84 expected_regs[5] = 0x0 # dest r3 is 0b10: skip
85 expected_regs[6] = 0xffff_ffff_ffff_ff91 # 2nd bit of r3 is 1
86
87 with Program(lst, bigendian=False) as program:
88 sim = self.run_tst_program(program, initial_regs, svstate)
89 self._check_regs(sim, expected_regs)
90
91 def tst_sv_add_intpred(self):
92 # adds, integer predicated mask r3=0b10
93 # 1 = 5 + 9 => not to be touched (skipped)
94 # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
95 isa = SVP64Asm(['svadd/m=r3 1.v, 5.v, 9.v'
96 ])
97 lst = list(isa)
98 print ("listing", lst)
99
100 # initial values in GPR regfile
101 initial_regs = [0] * 32
102 initial_regs[1] = 0xbeef # not to be altered
103 initial_regs[3] = 0b10 # predicate mask
104 initial_regs[9] = 0x1234
105 initial_regs[10] = 0x1111
106 initial_regs[5] = 0x4321
107 initial_regs[6] = 0x2223
108 # SVSTATE (in this case, VL=2)
109 svstate = SVP64State()
110 svstate.vl[0:7] = 2 # VL
111 svstate.maxvl[0:7] = 2 # MAXVL
112 print ("SVSTATE", bin(svstate.spr.asint()))
113 # copy before running
114 expected_regs = deepcopy(initial_regs)
115 expected_regs[1] = 0xbeef
116 expected_regs[2] = 0x3334
117
118 with Program(lst, bigendian=False) as program:
119 sim = self.run_tst_program(program, initial_regs, svstate)
120 self._check_regs(sim, expected_regs)
121
122 def tst_sv_add_cr_pred(self):
123 # adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
124 # 1 = 5 + 9 => not to be touched (skipped)
125 # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
126 isa = SVP64Asm(['svadd/m=ne 1.v, 5.v, 9.v'
127 ])
128 lst = list(isa)
129 print ("listing", lst)
130
131 # initial values in GPR regfile
132 initial_regs = [0] * 32
133 initial_regs[1] = 0xbeef # not to be altered
134 initial_regs[9] = 0x1234
135 initial_regs[10] = 0x1111
136 initial_regs[5] = 0x4321
137 initial_regs[6] = 0x2223
138 # SVSTATE (in this case, VL=2)
139 svstate = SVP64State()
140 svstate.vl[0:7] = 2 # VL
141 svstate.maxvl[0:7] = 2 # MAXVL
142 print ("SVSTATE", bin(svstate.spr.asint()))
143 # copy before running
144 expected_regs = deepcopy(initial_regs)
145 expected_regs[1] = 0xbeef
146 expected_regs[2] = 0x3334
147
148 # set up CR predicate - CR4.eq=0 and CR5.eq=1
149 cr = (0b0010) << ((7-4)*4) # CR5.eq (we hope)
150
151 with Program(lst, bigendian=False) as program:
152 sim = self.run_tst_program(program, initial_regs, svstate,
153 initial_cr=cr)
154 self._check_regs(sim, expected_regs)
155
156 def tst_sv_add_2(self):
157 # adds:
158 # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
159 # r1 is scalar so ENDS EARLY
160 isa = SVP64Asm(['svadd 1, 5.v, 9.v'
161 ])
162 lst = list(isa)
163 print ("listing", lst)
164
165 # initial values in GPR regfile
166 initial_regs = [0] * 32
167 initial_regs[9] = 0x1234
168 initial_regs[10] = 0x1111
169 initial_regs[5] = 0x4321
170 initial_regs[6] = 0x2223
171 # SVSTATE (in this case, VL=2)
172 svstate = SVP64State()
173 svstate.vl[0:7] = 2 # VL
174 svstate.maxvl[0:7] = 2 # MAXVL
175 print ("SVSTATE", bin(svstate.spr.asint()))
176 # copy before running
177 expected_regs = deepcopy(initial_regs)
178 expected_regs[1] = 0x5555
179
180 with Program(lst, bigendian=False) as program:
181 sim = self.run_tst_program(program, initial_regs, svstate)
182 self._check_regs(sim, expected_regs)
183
184 def tst_sv_add_3(self):
185 # adds:
186 # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
187 # 2 = 5 + 10 => 0x5432 = 0x4321+0x1111
188 isa = SVP64Asm(['svadd 1.v, 5, 9.v'
189 ])
190 lst = list(isa)
191 print ("listing", lst)
192
193 # initial values in GPR regfile
194 initial_regs = [0] * 32
195 initial_regs[9] = 0x1234
196 initial_regs[10] = 0x1111
197 initial_regs[5] = 0x4321
198 initial_regs[6] = 0x2223
199 # SVSTATE (in this case, VL=2)
200 svstate = SVP64State()
201 svstate.vl[0:7] = 2 # VL
202 svstate.maxvl[0:7] = 2 # MAXVL
203 print ("SVSTATE", bin(svstate.spr.asint()))
204 # copy before running
205 expected_regs = deepcopy(initial_regs)
206 expected_regs[1] = 0x5555
207 expected_regs[2] = 0x5432
208
209 with Program(lst, bigendian=False) as program:
210 sim = self.run_tst_program(program, initial_regs, svstate)
211 self._check_regs(sim, expected_regs)
212
213 def tst_sv_add_vl_0(self):
214 # adds:
215 # none because VL is zer0
216 isa = SVP64Asm(['svadd 1, 5.v, 9.v'
217 ])
218 lst = list(isa)
219 print ("listing", lst)
220
221 # initial values in GPR regfile
222 initial_regs = [0] * 32
223 initial_regs[9] = 0x1234
224 initial_regs[10] = 0x1111
225 initial_regs[5] = 0x4321
226 initial_regs[6] = 0x2223
227 # SVSTATE (in this case, VL=0)
228 svstate = SVP64State()
229 svstate.vl[0:7] = 0 # VL
230 svstate.maxvl[0:7] = 0 # MAXVL
231 print ("SVSTATE", bin(svstate.spr.asint()))
232 # copy before running
233 expected_regs = deepcopy(initial_regs)
234
235 with Program(lst, bigendian=False) as program:
236 sim = self.run_tst_program(program, initial_regs, svstate)
237 self._check_regs(sim, expected_regs)
238
239 def tst_sv_add_cr(self):
240 # adds when Rc=1: TODO CRs higher up
241 # 1 = 5 + 9 => 0 = -1+1 CR0=0b100
242 # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010
243 isa = SVP64Asm(['svadd. 1.v, 5.v, 9.v'
244 ])
245 lst = list(isa)
246 print ("listing", lst)
247
248 # initial values in GPR regfile
249 initial_regs = [0] * 32
250 initial_regs[9] = 0xffffffffffffffff
251 initial_regs[10] = 0x1111
252 initial_regs[5] = 0x1
253 initial_regs[6] = 0x2223
254 # SVSTATE (in this case, VL=2)
255 svstate = SVP64State()
256 svstate.vl[0:7] = 2 # VL
257 svstate.maxvl[0:7] = 2 # MAXVL
258 print ("SVSTATE", bin(svstate.spr.asint()))
259 # copy before running
260 expected_regs = deepcopy(initial_regs)
261 expected_regs[1] = 0
262 expected_regs[2] = 0x3334
263
264 with Program(lst, bigendian=False) as program:
265 sim = self.run_tst_program(program, initial_regs, svstate)
266 # XXX TODO, these need to move to higher range (offset)
267 cr0_idx = SVP64CROffs.CR0
268 cr1_idx = SVP64CROffs.CR1
269 CR0 = sim.crl[cr0_idx].get_range().value
270 CR1 = sim.crl[cr1_idx].get_range().value
271 print ("CR0", CR0)
272 print ("CR1", CR1)
273 self._check_regs(sim, expected_regs)
274 self.assertEqual(CR0, SelectableInt(2, 4))
275 self.assertEqual(CR1, SelectableInt(4, 4))
276
277 def run_tst_program(self, prog, initial_regs=None,
278 svstate=None,
279 initial_cr=0):
280 if initial_regs is None:
281 initial_regs = [0] * 32
282 simulator = run_tst(prog, initial_regs, svstate=svstate,
283 initial_cr=initial_cr)
284 simulator.gpr.dump()
285 return simulator
286
287
288 if __name__ == "__main__":
289 unittest.main()