radix: reading first page table entry
[soc.git] / src / soc / decoder / power_decoder2.py
1 """Power ISA Decoder second stage
2
3 based on Anton Blanchard microwatt decode2.vhdl
4
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
7 """
8
9 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
10 from nmigen.cli import rtlil
11 from nmutil.util import sel
12
13 from soc.regfile.regfiles import XERRegs
14
15 from nmutil.picker import PriorityPicker
16 from nmutil.iocontrol import RecordObject
17 from nmutil.extend import exts
18
19 from soc.experiment.mem_types import LDSTException
20
21 from soc.decoder.power_svp64_prefix import SVP64PrefixDecoder
22 from soc.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
23 from soc.decoder.power_regspec_map import regspec_decode_read
24 from soc.decoder.power_regspec_map import regspec_decode_write
25 from soc.decoder.power_decoder import create_pdecode
26 from soc.decoder.power_enums import (MicrOp, CryIn, Function,
27 CRInSel, CROutSel,
28 LdstLen, In1Sel, In2Sel, In3Sel,
29 OutSel, SPR, RC, LDSTMode,
30 SVEXTRA, SVEtype)
31 from soc.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
32 Decode2ToOperand)
33 from soc.sv.svp64 import SVP64Rec
34 from soc.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field,
35 SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs)
36
37 from soc.regfile.regfiles import FastRegs
38 from soc.consts import TT
39 from soc.config.state import CoreState
40 from soc.regfile.util import spr_to_fast
41
42
43 def decode_spr_num(spr):
44 return Cat(spr[5:10], spr[0:5])
45
46
47 def instr_is_priv(m, op, insn):
48 """determines if the instruction is privileged or not
49 """
50 comb = m.d.comb
51 is_priv_insn = Signal(reset_less=True)
52 with m.Switch(op):
53 with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
54 MicrOp.OP_MTMSR, MicrOp.OP_RFID):
55 comb += is_priv_insn.eq(1)
56 with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
57 with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):
58 with m.If(insn[20]): # field XFX.spr[-1] i think
59 comb += is_priv_insn.eq(1)
60 return is_priv_insn
61
62
63 class SPRMap(Elaboratable):
64 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
65 """
66
67 def __init__(self):
68 self.spr_i = Signal(10, reset_less=True)
69 self.spr_o = Data(SPR, name="spr_o")
70 self.fast_o = Data(3, name="fast_o")
71
72 def elaborate(self, platform):
73 m = Module()
74 with m.Switch(self.spr_i):
75 for i, x in enumerate(SPR):
76 with m.Case(x.value):
77 m.d.comb += self.spr_o.data.eq(i)
78 m.d.comb += self.spr_o.ok.eq(1)
79 for x, v in spr_to_fast.items():
80 with m.Case(x.value):
81 m.d.comb += self.fast_o.data.eq(v)
82 m.d.comb += self.fast_o.ok.eq(1)
83 return m
84
85
86 class DecodeA(Elaboratable):
87 """DecodeA from instruction
88
89 decodes register RA, implicit and explicit CSRs
90 """
91
92 def __init__(self, dec):
93 self.dec = dec
94 self.sel_in = Signal(In1Sel, reset_less=True)
95 self.insn_in = Signal(32, reset_less=True)
96 self.reg_out = Data(5, name="reg_a")
97 self.spr_out = Data(SPR, "spr_a")
98 self.fast_out = Data(3, "fast_a")
99
100 def elaborate(self, platform):
101 m = Module()
102 comb = m.d.comb
103 op = self.dec.op
104 reg = self.reg_out
105 m.submodules.sprmap = sprmap = SPRMap()
106
107 # select Register A field
108 ra = Signal(5, reset_less=True)
109 comb += ra.eq(self.dec.RA)
110 with m.If((self.sel_in == In1Sel.RA) |
111 ((self.sel_in == In1Sel.RA_OR_ZERO) &
112 (ra != Const(0, 5)))):
113 comb += reg.data.eq(ra)
114 comb += reg.ok.eq(1)
115
116 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
117 # moved it to 1st position (in1_sel)... because
118 rs = Signal(5, reset_less=True)
119 comb += rs.eq(self.dec.RS)
120 with m.If(self.sel_in == In1Sel.RS):
121 comb += reg.data.eq(rs)
122 comb += reg.ok.eq(1)
123
124 # decode Fast-SPR based on instruction type
125 with m.Switch(op.internal_op):
126
127 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
128 with m.Case(MicrOp.OP_BC):
129 with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
130 # constant: CTR
131 comb += self.fast_out.data.eq(FastRegs.CTR)
132 comb += self.fast_out.ok.eq(1)
133 with m.Case(MicrOp.OP_BCREG):
134 xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
135 xo5 = self.dec.FormXL.XO[5] # 3.0B p38
136 with m.If(xo9 & ~xo5):
137 # constant: CTR
138 comb += self.fast_out.data.eq(FastRegs.CTR)
139 comb += self.fast_out.ok.eq(1)
140
141 # MFSPR move from SPRs
142 with m.Case(MicrOp.OP_MFSPR):
143 spr = Signal(10, reset_less=True)
144 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
145 comb += sprmap.spr_i.eq(spr)
146 comb += self.spr_out.eq(sprmap.spr_o)
147 comb += self.fast_out.eq(sprmap.fast_o)
148
149 return m
150
151
152 class DecodeAImm(Elaboratable):
153 """DecodeA immediate from instruction
154
155 decodes register RA, whether immediate-zero, implicit and
156 explicit CSRs
157 """
158
159 def __init__(self, dec):
160 self.dec = dec
161 self.sel_in = Signal(In1Sel, reset_less=True)
162 self.immz_out = Signal(reset_less=True)
163
164 def elaborate(self, platform):
165 m = Module()
166 comb = m.d.comb
167
168 # zero immediate requested
169 ra = Signal(5, reset_less=True)
170 comb += ra.eq(self.dec.RA)
171 with m.If((self.sel_in == In1Sel.RA_OR_ZERO) & (ra == Const(0, 5))):
172 comb += self.immz_out.eq(1)
173
174 return m
175
176
177 class DecodeB(Elaboratable):
178 """DecodeB from instruction
179
180 decodes register RB, different forms of immediate (signed, unsigned),
181 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
182 by industry-standard convention, "lane 2" is where fully-decoded
183 immediates are muxed in.
184 """
185
186 def __init__(self, dec):
187 self.dec = dec
188 self.sel_in = Signal(In2Sel, reset_less=True)
189 self.insn_in = Signal(32, reset_less=True)
190 self.reg_out = Data(7, "reg_b")
191 self.reg_isvec = Signal(1, name="reg_b_isvec") # TODO: in reg_out
192 self.fast_out = Data(3, "fast_b")
193
194 def elaborate(self, platform):
195 m = Module()
196 comb = m.d.comb
197 op = self.dec.op
198 reg = self.reg_out
199
200 # select Register B field
201 with m.Switch(self.sel_in):
202 with m.Case(In2Sel.RB):
203 comb += reg.data.eq(self.dec.RB)
204 comb += reg.ok.eq(1)
205 with m.Case(In2Sel.RS):
206 # for M-Form shiftrot
207 comb += reg.data.eq(self.dec.RS)
208 comb += reg.ok.eq(1)
209
210 # decode SPR2 based on instruction type
211 # BCREG implicitly uses LR or TAR for 2nd reg
212 # CTR however is already in fast_spr1 *not* 2.
213 with m.If(op.internal_op == MicrOp.OP_BCREG):
214 xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
215 xo5 = self.dec.FormXL.XO[5] # 3.0B p38
216 with m.If(~xo9):
217 comb += self.fast_out.data.eq(FastRegs.LR)
218 comb += self.fast_out.ok.eq(1)
219 with m.Elif(xo5):
220 comb += self.fast_out.data.eq(FastRegs.TAR)
221 comb += self.fast_out.ok.eq(1)
222
223 return m
224
225
226 class DecodeBImm(Elaboratable):
227 """DecodeB immediate from instruction
228 """
229 def __init__(self, dec):
230 self.dec = dec
231 self.sel_in = Signal(In2Sel, reset_less=True)
232 self.imm_out = Data(64, "imm_b")
233
234 def elaborate(self, platform):
235 m = Module()
236 comb = m.d.comb
237
238 # select Register B Immediate
239 with m.Switch(self.sel_in):
240 with m.Case(In2Sel.CONST_UI): # unsigned
241 comb += self.imm_out.data.eq(self.dec.UI)
242 comb += self.imm_out.ok.eq(1)
243 with m.Case(In2Sel.CONST_SI): # sign-extended 16-bit
244 si = Signal(16, reset_less=True)
245 comb += si.eq(self.dec.SI)
246 comb += self.imm_out.data.eq(exts(si, 16, 64))
247 comb += self.imm_out.ok.eq(1)
248 with m.Case(In2Sel.CONST_SI_HI): # sign-extended 16+16=32 bit
249 si_hi = Signal(32, reset_less=True)
250 comb += si_hi.eq(self.dec.SI << 16)
251 comb += self.imm_out.data.eq(exts(si_hi, 32, 64))
252 comb += self.imm_out.ok.eq(1)
253 with m.Case(In2Sel.CONST_UI_HI): # unsigned
254 ui = Signal(16, reset_less=True)
255 comb += ui.eq(self.dec.UI)
256 comb += self.imm_out.data.eq(ui << 16)
257 comb += self.imm_out.ok.eq(1)
258 with m.Case(In2Sel.CONST_LI): # sign-extend 24+2=26 bit
259 li = Signal(26, reset_less=True)
260 comb += li.eq(self.dec.LI << 2)
261 comb += self.imm_out.data.eq(exts(li, 26, 64))
262 comb += self.imm_out.ok.eq(1)
263 with m.Case(In2Sel.CONST_BD): # sign-extend (14+2)=16 bit
264 bd = Signal(16, reset_less=True)
265 comb += bd.eq(self.dec.BD << 2)
266 comb += self.imm_out.data.eq(exts(bd, 16, 64))
267 comb += self.imm_out.ok.eq(1)
268 with m.Case(In2Sel.CONST_DS): # sign-extended (14+2=16) bit
269 ds = Signal(16, reset_less=True)
270 comb += ds.eq(self.dec.DS << 2)
271 comb += self.imm_out.data.eq(exts(ds, 16, 64))
272 comb += self.imm_out.ok.eq(1)
273 with m.Case(In2Sel.CONST_M1): # signed (-1)
274 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
275 comb += self.imm_out.ok.eq(1)
276 with m.Case(In2Sel.CONST_SH): # unsigned - for shift
277 comb += self.imm_out.data.eq(self.dec.sh)
278 comb += self.imm_out.ok.eq(1)
279 with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
280 comb += self.imm_out.data.eq(self.dec.SH32)
281 comb += self.imm_out.ok.eq(1)
282
283 return m
284
285
286 class DecodeC(Elaboratable):
287 """DecodeC from instruction
288
289 decodes register RC. this is "lane 3" into some CompUnits (not many)
290 """
291
292 def __init__(self, dec):
293 self.dec = dec
294 self.sel_in = Signal(In3Sel, reset_less=True)
295 self.insn_in = Signal(32, reset_less=True)
296 self.reg_out = Data(5, "reg_c")
297
298 def elaborate(self, platform):
299 m = Module()
300 comb = m.d.comb
301 op = self.dec.op
302 reg = self.reg_out
303
304 # select Register C field
305 with m.Switch(self.sel_in):
306 with m.Case(In3Sel.RB):
307 # for M-Form shiftrot
308 comb += reg.data.eq(self.dec.RB)
309 comb += reg.ok.eq(1)
310 with m.Case(In3Sel.RS):
311 comb += reg.data.eq(self.dec.RS)
312 comb += reg.ok.eq(1)
313
314 return m
315
316
317 class DecodeOut(Elaboratable):
318 """DecodeOut from instruction
319
320 decodes output register RA, RT or SPR
321 """
322
323 def __init__(self, dec):
324 self.dec = dec
325 self.sel_in = Signal(OutSel, reset_less=True)
326 self.insn_in = Signal(32, reset_less=True)
327 self.reg_out = Data(5, "reg_o")
328 self.spr_out = Data(SPR, "spr_o")
329 self.fast_out = Data(3, "fast_o")
330
331 def elaborate(self, platform):
332 m = Module()
333 comb = m.d.comb
334 m.submodules.sprmap = sprmap = SPRMap()
335 op = self.dec.op
336 reg = self.reg_out
337
338 # select Register out field
339 with m.Switch(self.sel_in):
340 with m.Case(OutSel.RT):
341 comb += reg.data.eq(self.dec.RT)
342 comb += reg.ok.eq(1)
343 with m.Case(OutSel.RA):
344 comb += reg.data.eq(self.dec.RA)
345 comb += reg.ok.eq(1)
346 with m.Case(OutSel.SPR):
347 spr = Signal(10, reset_less=True)
348 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
349 # MFSPR move to SPRs - needs mapping
350 with m.If(op.internal_op == MicrOp.OP_MTSPR):
351 comb += sprmap.spr_i.eq(spr)
352 comb += self.spr_out.eq(sprmap.spr_o)
353 comb += self.fast_out.eq(sprmap.fast_o)
354
355 # determine Fast Reg
356 with m.Switch(op.internal_op):
357
358 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
359 with m.Case(MicrOp.OP_BC, MicrOp.OP_BCREG):
360 with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
361 # constant: CTR
362 comb += self.fast_out.data.eq(FastRegs.CTR)
363 comb += self.fast_out.ok.eq(1)
364
365 # RFID 1st spr (fast)
366 with m.Case(MicrOp.OP_RFID):
367 comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
368 comb += self.fast_out.ok.eq(1)
369
370 return m
371
372
373 class DecodeOut2(Elaboratable):
374 """DecodeOut2 from instruction
375
376 decodes output registers (2nd one). note that RA is *implicit* below,
377 which now causes problems with SVP64
378
379 TODO: SVP64 is a little more complex, here. svp64 allows extending
380 by one more destination by having one more EXTRA field. RA-as-src
381 is not the same as RA-as-dest. limited in that it's the same first
382 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
383 for operations that have src-as-dest: mostly this is LD/ST-with-update
384 but there are others.
385 """
386
387 def __init__(self, dec):
388 self.dec = dec
389 self.sel_in = Signal(OutSel, reset_less=True)
390 self.lk = Signal(reset_less=True)
391 self.insn_in = Signal(32, reset_less=True)
392 self.reg_out = Data(5, "reg_o2")
393 self.fast_out = Data(3, "fast_o2")
394
395 def elaborate(self, platform):
396 m = Module()
397 comb = m.d.comb
398 op = self.dec.op
399 #m.submodules.svdec = svdec = SVP64RegExtra()
400
401 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
402 #reg = Signal(5, reset_less=True)
403
404 if hasattr(self.dec.op, "upd"):
405 # update mode LD/ST uses read-reg A also as an output
406 with m.If(self.dec.op.upd == LDSTMode.update):
407 comb += self.reg_out.data.eq(self.dec.RA)
408 comb += self.reg_out.ok.eq(1)
409
410 # B, BC or BCREG: potential implicit register (LR) output
411 # these give bl, bcl, bclrl, etc.
412 with m.Switch(op.internal_op):
413
414 # BC* implicit register (LR)
415 with m.Case(MicrOp.OP_BC, MicrOp.OP_B, MicrOp.OP_BCREG):
416 with m.If(self.lk): # "link" mode
417 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
418 comb += self.fast_out.ok.eq(1)
419
420 # RFID 2nd spr (fast)
421 with m.Case(MicrOp.OP_RFID):
422 comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
423 comb += self.fast_out.ok.eq(1)
424
425 return m
426
427
428 class DecodeRC(Elaboratable):
429 """DecodeRc from instruction
430
431 decodes Record bit Rc
432 """
433
434 def __init__(self, dec):
435 self.dec = dec
436 self.sel_in = Signal(RC, reset_less=True)
437 self.insn_in = Signal(32, reset_less=True)
438 self.rc_out = Data(1, "rc")
439
440 def elaborate(self, platform):
441 m = Module()
442 comb = m.d.comb
443
444 # select Record bit out field
445 with m.Switch(self.sel_in):
446 with m.Case(RC.RC):
447 comb += self.rc_out.data.eq(self.dec.Rc)
448 comb += self.rc_out.ok.eq(1)
449 with m.Case(RC.ONE):
450 comb += self.rc_out.data.eq(1)
451 comb += self.rc_out.ok.eq(1)
452 with m.Case(RC.NONE):
453 comb += self.rc_out.data.eq(0)
454 comb += self.rc_out.ok.eq(1)
455
456 return m
457
458
459 class DecodeOE(Elaboratable):
460 """DecodeOE from instruction
461
462 decodes OE field: uses RC decode detection which might not be good
463
464 -- For now, use "rc" in the decode table to decide whether oe exists.
465 -- This is not entirely correct architecturally: For mulhd and
466 -- mulhdu, the OE field is reserved. It remains to be seen what an
467 -- actual POWER9 does if we set it on those instructions, for now we
468 -- test that further down when assigning to the multiplier oe input.
469 """
470
471 def __init__(self, dec):
472 self.dec = dec
473 self.sel_in = Signal(RC, reset_less=True)
474 self.insn_in = Signal(32, reset_less=True)
475 self.oe_out = Data(1, "oe")
476
477 def elaborate(self, platform):
478 m = Module()
479 comb = m.d.comb
480 op = self.dec.op
481
482 with m.Switch(op.internal_op):
483
484 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
485 # also rotate
486 # XXX ARGH! ignoring OE causes incompatibility with microwatt
487 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
488 with m.Case(MicrOp.OP_MUL_H64, MicrOp.OP_MUL_H32,
489 MicrOp.OP_EXTS, MicrOp.OP_CNTZ,
490 MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC,
491 MicrOp.OP_LOAD, MicrOp.OP_STORE,
492 MicrOp.OP_RLCL, MicrOp.OP_RLCR,
493 MicrOp.OP_EXTSWSLI):
494 pass
495
496 # all other ops decode OE field
497 with m.Default():
498 # select OE bit out field
499 with m.Switch(self.sel_in):
500 with m.Case(RC.RC):
501 comb += self.oe_out.data.eq(self.dec.OE)
502 comb += self.oe_out.ok.eq(1)
503
504 return m
505
506
507 class DecodeCRIn(Elaboratable):
508 """Decodes input CR from instruction
509
510 CR indices - insn fields - (not the data *in* the CR) require only 3
511 bits because they refer to CR0-CR7
512 """
513
514 def __init__(self, dec):
515 self.dec = dec
516 self.sel_in = Signal(CRInSel, reset_less=True)
517 self.insn_in = Signal(32, reset_less=True)
518 self.cr_bitfield = Data(3, "cr_bitfield")
519 self.cr_bitfield_b = Data(3, "cr_bitfield_b")
520 self.cr_bitfield_o = Data(3, "cr_bitfield_o")
521 self.whole_reg = Data(8, "cr_fxm")
522 self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
523
524 def elaborate(self, platform):
525 m = Module()
526 comb = m.d.comb
527 op = self.dec.op
528 m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
529 reverse_o=True)
530
531 # zero-initialisation
532 comb += self.cr_bitfield.ok.eq(0)
533 comb += self.cr_bitfield_b.ok.eq(0)
534 comb += self.cr_bitfield_o.ok.eq(0)
535 comb += self.whole_reg.ok.eq(0)
536 comb += self.sv_override.eq(0)
537
538 # select the relevant CR bitfields
539 with m.Switch(self.sel_in):
540 with m.Case(CRInSel.NONE):
541 pass # No bitfield activated
542 with m.Case(CRInSel.CR0):
543 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
544 comb += self.cr_bitfield.ok.eq(1)
545 comb += self.sv_override.eq(1)
546 with m.Case(CRInSel.CR1):
547 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
548 comb += self.cr_bitfield.ok.eq(1)
549 comb += self.sv_override.eq(2)
550 with m.Case(CRInSel.BI):
551 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
552 comb += self.cr_bitfield.ok.eq(1)
553 with m.Case(CRInSel.BFA):
554 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
555 comb += self.cr_bitfield.ok.eq(1)
556 with m.Case(CRInSel.BA_BB):
557 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
558 comb += self.cr_bitfield.ok.eq(1)
559 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
560 comb += self.cr_bitfield_b.ok.eq(1)
561 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
562 comb += self.cr_bitfield_o.ok.eq(1)
563 with m.Case(CRInSel.BC):
564 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
565 comb += self.cr_bitfield.ok.eq(1)
566 with m.Case(CRInSel.WHOLE_REG):
567 comb += self.whole_reg.ok.eq(1)
568 move_one = Signal(reset_less=True)
569 comb += move_one.eq(self.insn_in[20]) # MSB0 bit 11
570 with m.If((op.internal_op == MicrOp.OP_MFCR) & move_one):
571 # must one-hot the FXM field
572 comb += ppick.i.eq(self.dec.FXM)
573 comb += self.whole_reg.data.eq(ppick.o)
574 with m.Else():
575 # otherwise use all of it
576 comb += self.whole_reg.data.eq(0xff)
577
578 return m
579
580
581 class DecodeCROut(Elaboratable):
582 """Decodes input CR from instruction
583
584 CR indices - insn fields - (not the data *in* the CR) require only 3
585 bits because they refer to CR0-CR7
586 """
587
588 def __init__(self, dec):
589 self.dec = dec
590 self.rc_in = Signal(reset_less=True)
591 self.sel_in = Signal(CROutSel, reset_less=True)
592 self.insn_in = Signal(32, reset_less=True)
593 self.cr_bitfield = Data(3, "cr_bitfield")
594 self.whole_reg = Data(8, "cr_fxm")
595 self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
596
597 def elaborate(self, platform):
598 m = Module()
599 comb = m.d.comb
600 op = self.dec.op
601 m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
602 reverse_o=True)
603
604 comb += self.cr_bitfield.ok.eq(0)
605 comb += self.whole_reg.ok.eq(0)
606 comb += self.sv_override.eq(0)
607
608 # please note these MUST match (setting of cr_bitfield.ok) exactly
609 # with write_cr0 below in PowerDecoder2. the reason it's separated
610 # is to avoid having duplicate copies of DecodeCROut in multiple
611 # PowerDecoderSubsets. register decoding should be a one-off in
612 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
613
614 with m.Switch(self.sel_in):
615 with m.Case(CROutSel.NONE):
616 pass # No bitfield activated
617 with m.Case(CROutSel.CR0):
618 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
619 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
620 comb += self.sv_override.eq(1)
621 with m.Case(CROutSel.CR1):
622 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
623 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
624 comb += self.sv_override.eq(2)
625 with m.Case(CROutSel.BF):
626 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
627 comb += self.cr_bitfield.ok.eq(1)
628 with m.Case(CROutSel.BT):
629 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
630 comb += self.cr_bitfield.ok.eq(1)
631 with m.Case(CROutSel.WHOLE_REG):
632 comb += self.whole_reg.ok.eq(1)
633 move_one = Signal(reset_less=True)
634 comb += move_one.eq(self.insn_in[20])
635 with m.If((op.internal_op == MicrOp.OP_MTCRF)):
636 with m.If(move_one):
637 # must one-hot the FXM field
638 comb += ppick.i.eq(self.dec.FXM)
639 with m.If(ppick.en_o):
640 comb += self.whole_reg.data.eq(ppick.o)
641 with m.Else():
642 comb += self.whole_reg.data.eq(0b00000001) # CR7
643 with m.Else():
644 comb += self.whole_reg.data.eq(self.dec.FXM)
645 with m.Else():
646 # otherwise use all of it
647 comb += self.whole_reg.data.eq(0xff)
648
649 return m
650
651 # dictionary of Input Record field names that, if they exist,
652 # will need a corresponding CSV Decoder file column (actually, PowerOp)
653 # to be decoded (this includes the single bit names)
654 record_names = {'insn_type': 'internal_op',
655 'fn_unit': 'function_unit',
656 'rc': 'rc_sel',
657 'oe': 'rc_sel',
658 'zero_a': 'in1_sel',
659 'imm_data': 'in2_sel',
660 'invert_in': 'inv_a',
661 'invert_out': 'inv_out',
662 'rc': 'cr_out',
663 'oe': 'cr_in',
664 'output_carry': 'cry_out',
665 'input_carry': 'cry_in',
666 'is_32bit': 'is_32b',
667 'is_signed': 'sgn',
668 'lk': 'lk',
669 'data_len': 'ldst_len',
670 'byte_reverse': 'br',
671 'sign_extend': 'sgn_ext',
672 'ldst_mode': 'upd',
673 }
674
675
676 class PowerDecodeSubset(Elaboratable):
677 """PowerDecodeSubset: dynamic subset decoder
678
679 only fields actually requested are copied over. hence, "subset" (duh).
680 """
681 def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None,
682 svp64_en=True):
683
684 self.svp64_en = svp64_en
685 if svp64_en:
686 self.sv_rm = SVP64Rec(name="dec_svp64") # SVP64 RM field
687 self.final = final
688 self.opkls = opkls
689 self.fn_name = fn_name
690 if opkls is None:
691 opkls = Decode2ToOperand
692 self.do = opkls(fn_name)
693 col_subset = self.get_col_subset(self.do)
694
695 # only needed for "main" PowerDecode2
696 if not self.final:
697 self.e = Decode2ToExecute1Type(name=self.fn_name, do=self.do)
698
699 # create decoder if one not already given
700 if dec is None:
701 dec = create_pdecode(name=fn_name, col_subset=col_subset,
702 row_subset=self.rowsubsetfn)
703 self.dec = dec
704
705 # state information needed by the Decoder
706 if state is None:
707 state = CoreState("dec2")
708 self.state = state
709
710 def get_col_subset(self, do):
711 subset = { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
712 for k, v in record_names.items():
713 if hasattr(do, k):
714 subset.add(v)
715 print ("get_col_subset", self.fn_name, do.fields, subset)
716 return subset
717
718 def rowsubsetfn(self, opcode, row):
719 """select per-Function-Unit subset of opcodes to be processed
720
721 normally this just looks at the "unit" column. MMU is different
722 in that it processes specific SPR set/get operations that the SPR
723 pipeline should not.
724 """
725 return (row['unit'] == self.fn_name or
726 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
727 # by the MMU pipeline so we direct those opcodes to MMU **AND**
728 # SPR pipelines, then selectively weed out the SPRs that should
729 # or should not not go to each pipeline, further down.
730 # really this should be done by modifying the CSV syntax
731 # to support multiple tasks (unit column multiple entries)
732 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
733 (self.fn_name == 'MMU' and row['unit'] == 'SPR' and
734 row['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
735 )
736
737 def ports(self):
738 ports = self.dec.ports() + self.e.ports()
739 if self.svp64_en:
740 ports += self.sv_rm.ports()
741 return ports
742
743 def needs_field(self, field, op_field):
744 if self.final:
745 do = self.do
746 else:
747 do = self.e_tmp.do
748 return hasattr(do, field) and self.op_get(op_field) is not None
749
750 def do_copy(self, field, val, final=False):
751 if final or self.final:
752 do = self.do
753 else:
754 do = self.e_tmp.do
755 if hasattr(do, field) and val is not None:
756 return getattr(do, field).eq(val)
757 return []
758
759 def op_get(self, op_field):
760 return getattr(self.dec.op, op_field, None)
761
762 def elaborate(self, platform):
763 m = Module()
764 comb = m.d.comb
765 state = self.state
766 op, do = self.dec.op, self.do
767 msr, cia = state.msr, state.pc
768 # fill in for a normal instruction (not an exception)
769 # copy over if non-exception, non-privileged etc. is detected
770 if not self.final:
771 if self.fn_name is None:
772 name = "tmp"
773 else:
774 name = self.fn_name + "tmp"
775 self.e_tmp = Decode2ToExecute1Type(name=name, opkls=self.opkls)
776
777 # set up submodule decoders
778 m.submodules.dec = self.dec
779 m.submodules.dec_rc = self.dec_rc = dec_rc = DecodeRC(self.dec)
780 m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
781
782 # copy instruction through...
783 for i in [do.insn, dec_rc.insn_in, dec_oe.insn_in, ]:
784 comb += i.eq(self.dec.opcode_in)
785
786 # ...and subdecoders' input fields
787 comb += dec_rc.sel_in.eq(op.rc_sel)
788 comb += dec_oe.sel_in.eq(op.rc_sel) # XXX should be OE sel
789
790 # copy "state" over
791 comb += self.do_copy("msr", msr)
792 comb += self.do_copy("cia", cia)
793
794 # set up instruction type
795 # no op: defaults to OP_ILLEGAL
796 internal_op = self.op_get("internal_op")
797 comb += self.do_copy("insn_type", internal_op)
798
799 # function unit for decoded instruction: requires minor redirect
800 # for SPR set/get
801 fn = self.op_get("function_unit")
802 spr = Signal(10, reset_less=True)
803 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
804
805 # Microwatt doesn't implement the partition table
806 # instead has PRTBL register (SPR) to point to process table
807 is_spr_mv = Signal()
808 is_mmu_spr = Signal()
809 comb += is_spr_mv.eq((internal_op == MicrOp.OP_MTSPR) |
810 (internal_op == MicrOp.OP_MFSPR))
811 comb += is_mmu_spr.eq((spr == SPR.DSISR.value) |
812 (spr == SPR.DAR.value) |
813 (spr == SPR.PRTBL.value) |
814 (spr == SPR.PIDR.value))
815 # MMU must receive MMU SPRs
816 with m.If(is_spr_mv & (fn == Function.SPR) & is_mmu_spr):
817 comb += self.do_copy("fn_unit", Function.NONE)
818 comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)
819 # SPR pipe must *not* receive MMU SPRs
820 with m.Elif(is_spr_mv & (fn == Function.MMU) & ~is_mmu_spr):
821 comb += self.do_copy("fn_unit", Function.NONE)
822 comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)
823 # all others ok
824 with m.Else():
825 comb += self.do_copy("fn_unit", fn)
826
827 # immediates
828 if self.needs_field("zero_a", "in1_sel"):
829 m.submodules.dec_ai = dec_ai = DecodeAImm(self.dec)
830 comb += dec_ai.sel_in.eq(op.in1_sel)
831 comb += self.do_copy("zero_a", dec_ai.immz_out) # RA==0 detected
832 if self.needs_field("imm_data", "in2_sel"):
833 m.submodules.dec_bi = dec_bi = DecodeBImm(self.dec)
834 comb += dec_bi.sel_in.eq(op.in2_sel)
835 comb += self.do_copy("imm_data", dec_bi.imm_out) # imm in RB
836
837 # rc and oe out
838 comb += self.do_copy("rc", dec_rc.rc_out)
839 comb += self.do_copy("oe", dec_oe.oe_out)
840
841 # CR in/out - note: these MUST match with what happens in
842 # DecodeCROut!
843 rc_out = self.dec_rc.rc_out.data
844 with m.Switch(op.cr_out):
845 with m.Case(CROutSel.CR0, CROutSel.CR1):
846 comb += self.do_copy("write_cr0", rc_out) # only when RC=1
847 with m.Case(CROutSel.BF, CROutSel.BT):
848 comb += self.do_copy("write_cr0", 1)
849
850 comb += self.do_copy("input_cr", self.op_get("cr_in")) # CR in
851 comb += self.do_copy("output_cr", self.op_get("cr_out")) # CR out
852
853 # decoded/selected instruction flags
854 comb += self.do_copy("data_len", self.op_get("ldst_len"))
855 comb += self.do_copy("invert_in", self.op_get("inv_a"))
856 comb += self.do_copy("invert_out", self.op_get("inv_out"))
857 comb += self.do_copy("input_carry", self.op_get("cry_in"))
858 comb += self.do_copy("output_carry", self.op_get("cry_out"))
859 comb += self.do_copy("is_32bit", self.op_get("is_32b"))
860 comb += self.do_copy("is_signed", self.op_get("sgn"))
861 lk = self.op_get("lk")
862 if lk is not None:
863 with m.If(lk):
864 comb += self.do_copy("lk", self.dec.LK) # XXX TODO: accessor
865
866 comb += self.do_copy("byte_reverse", self.op_get("br"))
867 comb += self.do_copy("sign_extend", self.op_get("sgn_ext"))
868 comb += self.do_copy("ldst_mode", self.op_get("upd")) # LD/ST mode
869
870 return m
871
872
873 class PowerDecode2(PowerDecodeSubset):
874 """PowerDecode2: the main instruction decoder.
875
876 whilst PowerDecode is responsible for decoding the actual opcode, this
877 module encapsulates further specialist, sparse information and
878 expansion of fields that is inconvenient to have in the CSV files.
879 for example: the encoding of the immediates, which are detected
880 and expanded out to their full value from an annotated (enum)
881 representation.
882
883 implicit register usage is also set up, here. for example: OP_BC
884 requires implicitly reading CTR, OP_RFID requires implicitly writing
885 to SRR1 and so on.
886
887 in addition, PowerDecoder2 is responsible for detecting whether
888 instructions are illegal (or privileged) or not, and instead of
889 just leaving at that, *replacing* the instruction to execute with
890 a suitable alternative (trap).
891
892 LDSTExceptions are done the cycle _after_ they're detected (after
893 they come out of LDSTCompUnit). basically despite the instruction
894 being decoded, the results of the decode are completely ignored
895 and "exception.happened" used to set the "actual" instruction to
896 "OP_TRAP". the LDSTException data structure gets filled in,
897 in the CompTrapOpSubset and that's what it fills in SRR.
898
899 to make this work, TestIssuer must notice "exception.happened"
900 after the (failed) LD/ST and copies the LDSTException info from
901 the output, into here (PowerDecoder2). without incrementing PC.
902 """
903
904 def __init__(self, dec, opkls=None, fn_name=None, final=False,
905 state=None, svp64_en=True):
906 super().__init__(dec, opkls, fn_name, final, state, svp64_en)
907 self.exc = LDSTException("dec2_exc")
908
909 if self.svp64_en:
910 self.cr_out_isvec = Signal(1, name="cr_out_isvec")
911 self.cr_in_isvec = Signal(1, name="cr_in_isvec")
912 self.cr_in_b_isvec = Signal(1, name="cr_in_b_isvec")
913 self.cr_in_o_isvec = Signal(1, name="cr_in_o_isvec")
914 self.in1_isvec = Signal(1, name="reg_a_isvec")
915 self.in2_isvec = Signal(1, name="reg_b_isvec")
916 self.in3_isvec = Signal(1, name="reg_c_isvec")
917 self.o_isvec = Signal(1, name="reg_o_isvec")
918 self.o2_isvec = Signal(1, name="reg_o2_isvec")
919 self.no_in_vec = Signal(1, name="no_in_vec") # no inputs vector
920 self.no_out_vec = Signal(1, name="no_out_vec") # no outputs vector
921 else:
922 self.no_in_vec = Const(1, 1)
923 self.no_out_vec = Const(1, 1)
924
925 def get_col_subset(self, opkls):
926 subset = super().get_col_subset(opkls)
927 subset.add("asmcode")
928 subset.add("in1_sel")
929 subset.add("in2_sel")
930 subset.add("in3_sel")
931 subset.add("out_sel")
932 if self.svp64_en:
933 subset.add("sv_in1")
934 subset.add("sv_in2")
935 subset.add("sv_in3")
936 subset.add("sv_out")
937 subset.add("sv_cr_in")
938 subset.add("sv_cr_out")
939 subset.add("SV_Etype")
940 subset.add("SV_Ptype")
941 subset.add("lk")
942 subset.add("internal_op")
943 subset.add("form")
944 return subset
945
946 def elaborate(self, platform):
947 m = super().elaborate(platform)
948 comb = m.d.comb
949 state = self.state
950 e_out, op, do_out = self.e, self.dec.op, self.e.do
951 dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
952 rc_out = self.dec_rc.rc_out.data
953 e = self.e_tmp
954 do = e.do
955
956 # fill in for a normal instruction (not an exception)
957 # copy over if non-exception, non-privileged etc. is detected
958
959 # set up submodule decoders
960 m.submodules.dec_a = dec_a = DecodeA(self.dec)
961 m.submodules.dec_b = dec_b = DecodeB(self.dec)
962 m.submodules.dec_c = dec_c = DecodeC(self.dec)
963 m.submodules.dec_o = dec_o = DecodeOut(self.dec)
964 m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
965 m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec)
966 m.submodules.dec_cr_out = self.dec_cr_out = DecodeCROut(self.dec)
967
968 if self.svp64_en:
969 # and SVP64 Extra decoders
970 m.submodules.crout_svdec = crout_svdec = SVP64CRExtra()
971 m.submodules.crin_svdec = crin_svdec = SVP64CRExtra()
972 m.submodules.crin_svdec_b = crin_svdec_b = SVP64CRExtra()
973 m.submodules.crin_svdec_o = crin_svdec_o = SVP64CRExtra()
974 m.submodules.in1_svdec = in1_svdec = SVP64RegExtra()
975 m.submodules.in2_svdec = in2_svdec = SVP64RegExtra()
976 m.submodules.in3_svdec = in3_svdec = SVP64RegExtra()
977 m.submodules.o_svdec = o_svdec = SVP64RegExtra()
978 m.submodules.o2_svdec = o2_svdec = SVP64RegExtra()
979
980 # debug access to crout_svdec (used in get_pdecode_cr_out)
981 self.crout_svdec = crout_svdec
982
983 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
984 reg = Signal(5, reset_less=True)
985
986 # copy instruction through...
987 for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
988 self.dec_cr_in.insn_in, self.dec_cr_out.insn_in,
989 dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]:
990 comb += i.eq(self.dec.opcode_in)
991
992 # CR setup
993 comb += self.dec_cr_in.sel_in.eq(op.cr_in)
994 comb += self.dec_cr_out.sel_in.eq(op.cr_out)
995 comb += self.dec_cr_out.rc_in.eq(rc_out)
996
997 # CR register info
998 comb += self.do_copy("read_cr_whole", self.dec_cr_in.whole_reg)
999 comb += self.do_copy("write_cr_whole", self.dec_cr_out.whole_reg)
1000
1001 # ...and subdecoders' input fields
1002 comb += dec_a.sel_in.eq(op.in1_sel)
1003 comb += dec_b.sel_in.eq(op.in2_sel)
1004 comb += dec_c.sel_in.eq(op.in3_sel)
1005 comb += dec_o.sel_in.eq(op.out_sel)
1006 comb += dec_o2.sel_in.eq(op.out_sel)
1007 if hasattr(do, "lk"):
1008 comb += dec_o2.lk.eq(do.lk)
1009
1010 if self.svp64_en:
1011 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1012 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1013 # which in turn were auto-generated by sv_analysis.py
1014 extra = self.sv_rm.extra # SVP64 extra bits 10:18
1015
1016 #######
1017 # CR out
1018 comb += crout_svdec.idx.eq(op.sv_cr_out) # SVP64 CR out
1019 comb += self.cr_out_isvec.eq(crout_svdec.isvec)
1020
1021 #######
1022 # CR in - selection slightly different due to shared CR field sigh
1023 cr_a_idx = Signal(SVEXTRA)
1024 cr_b_idx = Signal(SVEXTRA)
1025
1026 # these change slightly, when decoding BA/BB. really should have
1027 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1028 comb += cr_a_idx.eq(op.sv_cr_in)
1029 comb += cr_b_idx.eq(SVEXTRA.NONE)
1030 with m.If(op.sv_cr_in == SVEXTRA.Idx_1_2.value):
1031 comb += cr_a_idx.eq(SVEXTRA.Idx1)
1032 comb += cr_b_idx.eq(SVEXTRA.Idx2)
1033
1034 comb += self.cr_in_isvec.eq(crin_svdec.isvec)
1035 comb += self.cr_in_b_isvec.eq(crin_svdec_b.isvec)
1036 comb += self.cr_in_o_isvec.eq(crin_svdec_o.isvec)
1037
1038 # indices are slightly different, BA/BB mess sorted above
1039 comb += crin_svdec.idx.eq(cr_a_idx) # SVP64 CR in A
1040 comb += crin_svdec_b.idx.eq(cr_b_idx) # SVP64 CR in B
1041 comb += crin_svdec_o.idx.eq(op.sv_cr_out) # SVP64 CR out
1042
1043 # get SVSTATE srcstep (TODO: elwidth, dststep etc.) needed below
1044 srcstep = Signal.like(self.state.svstate.srcstep)
1045 comb += srcstep.eq(self.state.svstate.srcstep)
1046
1047 # registers a, b, c and out and out2 (LD/ST EA)
1048 for to_reg, fromreg, svdec in (
1049 (e.read_reg1, dec_a.reg_out, in1_svdec),
1050 (e.read_reg2, dec_b.reg_out, in2_svdec),
1051 (e.read_reg3, dec_c.reg_out, in3_svdec),
1052 (e.write_reg, dec_o.reg_out, o_svdec),
1053 (e.write_ea, dec_o2.reg_out, o2_svdec)):
1054 comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
1055 comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
1056 comb += svdec.reg_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1057 comb += to_reg.ok.eq(fromreg.ok)
1058 # detect if Vectorised: add srcstep if yes. TODO: a LOT.
1059 # this trick only holds when elwidth=default and in single-pred
1060 with m.If(svdec.isvec):
1061 comb += to_reg.data.eq(srcstep+svdec.reg_out) # 7-bit output
1062 with m.Else():
1063 comb += to_reg.data.eq(svdec.reg_out) # 7-bit output
1064
1065 comb += in1_svdec.idx.eq(op.sv_in1) # SVP64 reg #1 (in1_sel)
1066 comb += in2_svdec.idx.eq(op.sv_in2) # SVP64 reg #2 (in2_sel)
1067 comb += in3_svdec.idx.eq(op.sv_in3) # SVP64 reg #3 (in3_sel)
1068 comb += o_svdec.idx.eq(op.sv_out) # SVP64 output (out_sel)
1069 # XXX TODO - work out where this should come from. the problem is
1070 # that LD-with-update is implied (computed from "is instruction in
1071 # "update mode" rather than specified cleanly as its own CSV column
1072 #comb += o2_svdec.idx.eq(op.sv_out) # SVP64 output (implicit)
1073
1074 # output reg-is-vectorised (and when no in/out is vectorised)
1075 comb += self.in1_isvec.eq(in1_svdec.isvec)
1076 comb += self.in2_isvec.eq(in2_svdec.isvec)
1077 comb += self.in3_isvec.eq(in3_svdec.isvec)
1078 comb += self.o_isvec.eq(o_svdec.isvec)
1079 comb += self.o2_isvec.eq(o2_svdec.isvec)
1080 # TODO add SPRs here. must be True when *all* are scalar
1081 l = map(lambda svdec: svdec.isvec, [in1_svdec, in2_svdec, in3_svdec,
1082 crin_svdec, crin_svdec_b, crin_svdec_o])
1083 comb += self.no_in_vec.eq(~Cat(*l).bool()) # all input scalar
1084 l = map(lambda svdec: svdec.isvec, [o2_svdec, o_svdec, crout_svdec])
1085 comb += self.no_out_vec.eq(~Cat(*l).bool()) # all output scalar
1086
1087 # condition registers (CR)
1088 for to_reg, cr, name, svdec in (
1089 (e.read_cr1, self.dec_cr_in, "cr_bitfield", crin_svdec),
1090 (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", crin_svdec_b),
1091 (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", crin_svdec_o),
1092 (e.write_cr, self.dec_cr_out, "cr_bitfield", crout_svdec)):
1093 fromreg = getattr(cr, name)
1094 comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
1095 comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
1096 comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1097 with m.If(svdec.isvec):
1098 # check if this is CR0 or CR1: treated differently
1099 # (does not "listen" to EXTRA2/3 spec for a start)
1100 # also: the CRs start from completely different locations
1101 with m.If(cr.sv_override == 1): # CR0
1102 offs = SVP64CROffs.CR0
1103 comb += to_reg.data.eq(srcstep+offs)
1104 with m.Elif(cr.sv_override == 2): # CR1
1105 offs = SVP64CROffs.CR1
1106 comb += to_reg.data.eq(srcstep+1)
1107 with m.Else():
1108 comb += to_reg.data.eq(srcstep+svdec.cr_out) # 7-bit out
1109 with m.Else():
1110 comb += to_reg.data.eq(svdec.cr_out) # 7-bit output
1111 comb += to_reg.ok.eq(fromreg.ok)
1112
1113 else:
1114 # connect up to/from read/write GPRs
1115 for to_reg, fromreg in ((e.read_reg1, dec_a.reg_out),
1116 (e.read_reg2, dec_b.reg_out),
1117 (e.read_reg3, dec_c.reg_out),
1118 (e.write_reg, dec_o.reg_out),
1119 (e.write_ea, dec_o2.reg_out)):
1120 comb += to_reg.data.eq(fromreg.data)
1121 comb += to_reg.ok.eq(fromreg.ok)
1122
1123 # connect up to/from read/write CRs
1124 for to_reg, cr, name in (
1125 (e.read_cr1, self.dec_cr_in, "cr_bitfield", ),
1126 (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", ),
1127 (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", ),
1128 (e.write_cr, self.dec_cr_out, "cr_bitfield", )):
1129 fromreg = getattr(cr, name)
1130 comb += to_reg.data.eq(fromreg.data)
1131 comb += to_reg.ok.eq(fromreg.ok)
1132
1133 # SPRs out
1134 comb += e.read_spr1.eq(dec_a.spr_out)
1135 comb += e.write_spr.eq(dec_o.spr_out)
1136
1137 # Fast regs out
1138 comb += e.read_fast1.eq(dec_a.fast_out)
1139 comb += e.read_fast2.eq(dec_b.fast_out)
1140 comb += e.write_fast1.eq(dec_o.fast_out)
1141 comb += e.write_fast2.eq(dec_o2.fast_out)
1142
1143 # sigh this is exactly the sort of thing for which the
1144 # decoder is designed to not need. MTSPR, MFSPR and others need
1145 # access to the XER bits. however setting e.oe is not appropriate
1146 with m.If(op.internal_op == MicrOp.OP_MFSPR):
1147 comb += e.xer_in.eq(0b111) # SO, CA, OV
1148 with m.If(op.internal_op == MicrOp.OP_CMP):
1149 comb += e.xer_in.eq(1<<XERRegs.SO) # SO
1150 with m.If(op.internal_op == MicrOp.OP_MTSPR):
1151 comb += e.xer_out.eq(1)
1152
1153 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1154 with m.If(op.internal_op == MicrOp.OP_TRAP):
1155 # *DO NOT* call self.trap here. that would reset absolutely
1156 # everything including destroying read of RA and RB.
1157 comb += self.do_copy("trapaddr", 0x70) # strip first nibble
1158
1159 ####################
1160 # ok so the instruction's been decoded, blah blah, however
1161 # now we need to determine if it's actually going to go ahead...
1162 # *or* if in fact it's a privileged operation, whether there's
1163 # an external interrupt, etc. etc. this is a simple priority
1164 # if-elif-elif sequence. decrement takes highest priority,
1165 # EINT next highest, privileged operation third.
1166
1167 # check if instruction is privileged
1168 is_priv_insn = instr_is_priv(m, op.internal_op, e.do.insn)
1169
1170 # different IRQ conditions
1171 ext_irq_ok = Signal()
1172 dec_irq_ok = Signal()
1173 priv_ok = Signal()
1174 illeg_ok = Signal()
1175 exc = self.exc
1176
1177 comb += ext_irq_ok.eq(ext_irq & msr[MSR.EE]) # v3.0B p944 (MSR.EE)
1178 comb += dec_irq_ok.eq(dec_spr[63] & msr[MSR.EE]) # 6.5.11 p1076
1179 comb += priv_ok.eq(is_priv_insn & msr[MSR.PR])
1180 comb += illeg_ok.eq(op.internal_op == MicrOp.OP_ILLEGAL)
1181
1182 # LD/ST exceptions. TestIssuer copies the exception info at us
1183 # after a failed LD/ST.
1184 with m.If(exc.happened):
1185 with m.If(exc.alignment):
1186 self.trap(m, TT.PRIV, 0x600)
1187 with m.Elif(exc.instr_fault):
1188 with m.If(exc.segment_fault):
1189 self.trap(m, TT.PRIV, 0x480)
1190 with m.Else():
1191 # pass exception info to trap to create SRR1
1192 self.trap(m, TT.MEMEXC, 0x400, exc)
1193 with m.Else():
1194 with m.If(exc.segment_fault):
1195 self.trap(m, TT.PRIV, 0x380)
1196 with m.Else():
1197 self.trap(m, TT.PRIV, 0x300)
1198
1199 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1200 with m.Elif(dec_irq_ok):
1201 self.trap(m, TT.DEC, 0x900) # v3.0B 6.5 p1065
1202
1203 # external interrupt? only if MSR.EE set
1204 with m.Elif(ext_irq_ok):
1205 self.trap(m, TT.EINT, 0x500)
1206
1207 # privileged instruction trap
1208 with m.Elif(priv_ok):
1209 self.trap(m, TT.PRIV, 0x700)
1210
1211 # illegal instruction must redirect to trap. this is done by
1212 # *overwriting* the decoded instruction and starting again.
1213 # (note: the same goes for interrupts and for privileged operations,
1214 # just with different trapaddr and traptype)
1215 with m.Elif(illeg_ok):
1216 # illegal instruction trap
1217 self.trap(m, TT.ILLEG, 0x700)
1218
1219 # no exception, just copy things to the output
1220 with m.Else():
1221 comb += e_out.eq(e)
1222
1223 ####################
1224 # follow-up after trap/irq to set up SRR0/1
1225
1226 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1227 # Note: OP_SC could actually be modified to just be a trap
1228 with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
1229 (do_out.insn_type == MicrOp.OP_SC)):
1230 # TRAP write fast1 = SRR0
1231 comb += e_out.write_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
1232 comb += e_out.write_fast1.ok.eq(1)
1233 # TRAP write fast2 = SRR1
1234 comb += e_out.write_fast2.data.eq(FastRegs.SRR1) # constant: SRR1
1235 comb += e_out.write_fast2.ok.eq(1)
1236
1237 # RFID: needs to read SRR0/1
1238 with m.If(do_out.insn_type == MicrOp.OP_RFID):
1239 # TRAP read fast1 = SRR0
1240 comb += e_out.read_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
1241 comb += e_out.read_fast1.ok.eq(1)
1242 # TRAP read fast2 = SRR1
1243 comb += e_out.read_fast2.data.eq(FastRegs.SRR1) # constant: SRR1
1244 comb += e_out.read_fast2.ok.eq(1)
1245
1246 # annoying simulator bug
1247 if hasattr(e_out, "asmcode") and hasattr(self.dec.op, "asmcode"):
1248 comb += e_out.asmcode.eq(self.dec.op.asmcode)
1249
1250 return m
1251
1252 def trap(self, m, traptype, trapaddr, exc=None):
1253 """trap: this basically "rewrites" the decoded instruction as a trap
1254 """
1255 comb = m.d.comb
1256 op, e = self.dec.op, self.e
1257 comb += e.eq(0) # reset eeeeeverything
1258
1259 # start again
1260 comb += self.do_copy("insn", self.dec.opcode_in, True)
1261 comb += self.do_copy("insn_type", MicrOp.OP_TRAP, True)
1262 comb += self.do_copy("fn_unit", Function.TRAP, True)
1263 comb += self.do_copy("trapaddr", trapaddr >> 4, True) # bottom 4 bits
1264 comb += self.do_copy("traptype", traptype, True) # request type
1265 comb += self.do_copy("ldst_exc", exc, True) # request type
1266 comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state"
1267 comb += self.do_copy("cia", self.state.pc, True) # copy of PC "state"
1268
1269
1270
1271 def get_rdflags(e, cu):
1272 rdl = []
1273 for idx in range(cu.n_src):
1274 regfile, regname, _ = cu.get_in_spec(idx)
1275 rdflag, read = regspec_decode_read(e, regfile, regname)
1276 rdl.append(rdflag)
1277 print("rdflags", rdl)
1278 return Cat(*rdl)
1279
1280
1281 if __name__ == '__main__':
1282 pdecode = create_pdecode()
1283 dec2 = PowerDecode2(pdecode)
1284 vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
1285 with open("dec2.il", "w") as f:
1286 f.write(vl)