4dcf078da16d7f13243dd84a07ca59428cfa6cdf
[soc.git] / src / soc / decoder / power_decoder2.py
1 """Power ISA Decoder second stage
2
3 based on Anton Blanchard microwatt decode2.vhdl
4
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
7 """
8
9 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
10 from nmigen.cli import rtlil
11 from soc.regfile.regfiles import XERRegs
12
13 from nmutil.picker import PriorityPicker
14 from nmutil.iocontrol import RecordObject
15 from nmutil.extend import exts
16
17 from soc.experiment.mem_types import LDSTException
18
19 from soc.decoder.power_regspec_map import regspec_decode_read
20 from soc.decoder.power_regspec_map import regspec_decode_write
21 from soc.decoder.power_decoder import create_pdecode
22 from soc.decoder.power_enums import (MicrOp, CryIn, Function,
23 CRInSel, CROutSel,
24 LdstLen, In1Sel, In2Sel, In3Sel,
25 OutSel, SPR, RC, LDSTMode,
26 SVEXTRA, SVEtype)
27 from soc.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
28 Decode2ToOperand)
29 from soc.sv.svp64 import SVP64Rec
30 from soc.consts import MSR
31
32 from soc.regfile.regfiles import FastRegs
33 from soc.consts import TT
34 from soc.config.state import CoreState
35 from soc.regfile.util import spr_to_fast
36
37
38 def decode_spr_num(spr):
39 return Cat(spr[5:10], spr[0:5])
40
41
42 def instr_is_priv(m, op, insn):
43 """determines if the instruction is privileged or not
44 """
45 comb = m.d.comb
46 is_priv_insn = Signal(reset_less=True)
47 with m.Switch(op):
48 with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
49 MicrOp.OP_MTMSR, MicrOp.OP_RFID):
50 comb += is_priv_insn.eq(1)
51 # XXX TODO
52 #with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
53 with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):
54 with m.If(insn[20]): # field XFX.spr[-1] i think
55 comb += is_priv_insn.eq(1)
56 return is_priv_insn
57
58
59 class SPRMap(Elaboratable):
60 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
61 """
62
63 def __init__(self):
64 self.spr_i = Signal(10, reset_less=True)
65 self.spr_o = Data(SPR, name="spr_o")
66 self.fast_o = Data(3, name="fast_o")
67
68 def elaborate(self, platform):
69 m = Module()
70 with m.Switch(self.spr_i):
71 for i, x in enumerate(SPR):
72 with m.Case(x.value):
73 m.d.comb += self.spr_o.data.eq(i)
74 m.d.comb += self.spr_o.ok.eq(1)
75 for x, v in spr_to_fast.items():
76 with m.Case(x.value):
77 m.d.comb += self.fast_o.data.eq(v)
78 m.d.comb += self.fast_o.ok.eq(1)
79 return m
80
81
82 class SVP64ExtraSpec(Elaboratable):
83 """SVP64ExtraSpec - decodes SVP64 Extra specification.
84
85 selects the required EXTRA2/3 field.
86
87 see https://libre-soc.org/openpower/sv/svp64/
88 """
89 def __init__(self):
90 self.extra = Signal(10, reset_less=True)
91 self.etype = Signal(SVEtype, reset_less=True) # 2 or 3 bits
92 self.idx = Signal(SVEXTRA, reset_less=True) # which part of extra
93 self.spec = Signal(3) # EXTRA spec for the register
94
95 def elaborate(self, platform):
96 m = Module()
97 comb = m.d.comb
98 spec = self.spec
99
100 # back in the LDSTRM-* and RM-* files generated by sv_analysis.py
101 # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
102 # which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
103 # the register-extension information. extract those now
104 with m.Switch(self.etype):
105 # 2-bit index selection mode
106 with m.Case(SVEtype.EXTRA2):
107 with m.Switch(self.idx):
108 with m.Case(SVEXTRA.Idx0): # 1st 2 bits
109 comb += spec[1:3].eq(self.extra[0:2])
110 with m.Case(SVEXTRA.Idx1): # 2nd 2 bits
111 comb += spec[1:3].eq(self.extra[2:4])
112 with m.Case(SVEXTRA.Idx2): # 3rd 2 bits
113 comb += spec[1:3].eq(self.extra[4:6])
114 with m.Case(SVEXTRA.Idx3): # 4th 2 bits
115 comb += spec[1:3].eq(self.extra[6:8])
116 # 3-bit index selection mode
117 with m.Case(SVEtype.EXTRA3):
118 with m.Switch(self.idx):
119 with m.Case(SVEXTRA.Idx0): # 1st 3 bits
120 comb += spec.eq(self.extra[0:3])
121 with m.Case(SVEXTRA.Idx1): # 2nd 3 bits
122 comb += spec.eq(self.extra[3:6])
123 with m.Case(SVEXTRA.Idx2): # 3rd 3 bits
124 comb += spec.eq(self.extra[6:9])
125 # cannot fit more than 9 bits so there is no 4th thing
126
127 return m
128
129
130 class SVP64RegExtra(SVP64ExtraSpec):
131 """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
132
133 incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
134 depending on info in one of the positions in the EXTRA field.
135
136 designed so that "no change" to the 5-bit register number occurs if
137 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
138
139 see https://libre-soc.org/openpower/sv/svp64/
140 """
141 def __init__(self):
142 SVP64ExtraSpec.__init__(self)
143 self.reg_in = Signal(5) # incoming reg number (5 bits, RA, RB)
144 self.reg_out = Signal(7) # extra-augmented output (7 bits)
145 self.isvec = Signal(1) # reg is marked as vector if true
146
147 def elaborate(self, platform):
148 m = super().elaborate(platform) # select required EXTRA2/3
149 comb = m.d.comb
150
151 # first get the spec. if not changed it's "scalar identity behaviour"
152 # which is zero which is ok.
153 spec = self.spec
154
155 # now decode it. bit 2 is "scalar/vector". note that spec could be zero
156 # from above, which (by design) has the effect of "no change", below.
157
158 # simple: isvec is top bit of spec
159 comb += self.isvec.eq(spec[2])
160
161 # decode vector differently from scalar
162 with m.If(self.isvec):
163 # Vector: shifted up, extra in LSBs (RA << 2) | spec[0:1]
164 comb += self.reg_out.eq(Cat(spec[:2], self.reg_in))
165 with m.Else():
166 # Scalar: not shifted up, extra in MSBs RA | (spec[0:1] << 5)
167 comb += self.reg_out.eq(Cat(self.reg_in, spec[:2]))
168
169 return m
170
171
172 class SVP64CRExtra(SVP64ExtraSpec):
173 """SVP64CRExtra - decodes SVP64 Extra fields to determine CR extension
174
175 incoming 3-bit CR is turned into a 7-bit and marked as scalar/vector
176 depending on info in one of the positions in the EXTRA field.
177
178 yes, really, 128 CRs. INT is 128, FP is 128, therefore CRs are 128.
179
180 designed so that "no change" to the 3-bit CR register number occurs if
181 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
182
183 see https://libre-soc.org/openpower/sv/svp64/appendix
184 """
185 def __init__(self):
186 SVP64ExtraSpec.__init__(self)
187 self.cr_in = Signal(3) # incoming CR number (3 bits, BA[2:5], BFA)
188 self.cr_out = Signal(7) # extra-augmented CR output (7 bits)
189 self.isvec = Signal(1) # reg is marked as vector if true
190
191 def elaborate(self, platform):
192 m = super().elaborate(platform) # select required EXTRA2/3
193 comb = m.d.comb
194
195 # first get the spec. if not changed it's "scalar identity behaviour"
196 # which is zero which is ok.
197 spec = self.spec
198
199 # now decode it. bit 2 is "scalar/vector". note that spec could be zero
200 # from above, which (by design) has the effect of "no change", below.
201
202 # simple: isvec is top bit of spec
203 comb += self.isvec.eq(spec[2])
204
205 # decode vector differently from scalar, insert bits 0 and 1 accordingly
206 with m.If(self.isvec):
207 # Vector: shifted up, extra in LSBs (CR << 4) | (spec[0:1] << 2)
208 comb += self.cr_out.eq(Cat(Const(0, 2), spec[:2], self.cr_in))
209 with m.Else():
210 # Scalar: not shifted up, extra in MSBs CR | (spec[0:1] << 3)
211 comb += self.cr_out.eq(Cat(self.cr_in, spec[:2]))
212
213 return m
214
215
216 class DecodeA(Elaboratable):
217 """DecodeA from instruction
218
219 decodes register RA, implicit and explicit CSRs
220 """
221
222 def __init__(self, dec):
223 self.dec = dec
224 self.sv_rm = SVP64Rec() # SVP64 RM field
225 self.sel_in = Signal(In1Sel, reset_less=True)
226 self.insn_in = Signal(32, reset_less=True)
227 self.reg_out = Data(7, name="reg_a")
228 self.reg_isvec = Signal(1, name="reg_a_isvec") # TODO: in reg_out
229 self.spr_out = Data(SPR, "spr_a")
230 self.fast_out = Data(3, "fast_a")
231
232 def elaborate(self, platform):
233 m = Module()
234 comb = m.d.comb
235 op = self.dec.op
236 m.submodules.sprmap = sprmap = SPRMap()
237 m.submodules.svdec = svdec = SVP64RegExtra()
238
239 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
240 reg = Signal(5, reset_less=True)
241
242 # select Register A field
243 ra = Signal(5, reset_less=True)
244 comb += ra.eq(self.dec.RA)
245 with m.If((self.sel_in == In1Sel.RA) |
246 ((self.sel_in == In1Sel.RA_OR_ZERO) &
247 (ra != Const(0, 5)))):
248 comb += reg.eq(ra)
249 comb += self.reg_out.ok.eq(1)
250
251 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
252 # moved it to 1st position (in1_sel)... because
253 rs = Signal(5, reset_less=True)
254 comb += rs.eq(self.dec.RS)
255 with m.If(self.sel_in == In1Sel.RS):
256 comb += reg.eq(rs)
257 comb += self.reg_out.ok.eq(1)
258
259 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
260 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
261 # which in turn were auto-generated by sv_analysis.py
262
263 extra = self.sv_rm.extra # SVP64 extra bits 10:18
264 comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
265 comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
266 comb += svdec.idx.eq(op.sv_in1) # SVP64 reg #1 (matches in1_sel)
267 comb += svdec.reg_in.eq(reg) # 5-bit (RA, RS)
268
269 # outputs: 7-bit reg number and whether it's vectorised
270 comb += self.reg_out.data.eq(svdec.reg_out)
271 comb += self.reg_isvec.eq(svdec.isvec)
272
273 # decode Fast-SPR based on instruction type
274 with m.Switch(op.internal_op):
275
276 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
277 with m.Case(MicrOp.OP_BC):
278 with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
279 # constant: CTR
280 comb += self.fast_out.data.eq(FastRegs.CTR)
281 comb += self.fast_out.ok.eq(1)
282 with m.Case(MicrOp.OP_BCREG):
283 xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
284 xo5 = self.dec.FormXL.XO[5] # 3.0B p38
285 with m.If(xo9 & ~xo5):
286 # constant: CTR
287 comb += self.fast_out.data.eq(FastRegs.CTR)
288 comb += self.fast_out.ok.eq(1)
289
290 # MFSPR move from SPRs
291 with m.Case(MicrOp.OP_MFSPR):
292 spr = Signal(10, reset_less=True)
293 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
294 comb += sprmap.spr_i.eq(spr)
295 comb += self.spr_out.eq(sprmap.spr_o)
296 comb += self.fast_out.eq(sprmap.fast_o)
297
298 return m
299
300
301 class DecodeAImm(Elaboratable):
302 """DecodeA immediate from instruction
303
304 decodes register RA, whether immediate-zero, implicit and
305 explicit CSRs
306 """
307
308 def __init__(self, dec):
309 self.dec = dec
310 self.sel_in = Signal(In1Sel, reset_less=True)
311 self.immz_out = Signal(reset_less=True)
312
313 def elaborate(self, platform):
314 m = Module()
315 comb = m.d.comb
316
317 # zero immediate requested
318 ra = Signal(5, reset_less=True)
319 comb += ra.eq(self.dec.RA)
320 with m.If((self.sel_in == In1Sel.RA_OR_ZERO) & (ra == Const(0, 5))):
321 comb += self.immz_out.eq(1)
322
323 return m
324
325
326 class DecodeB(Elaboratable):
327 """DecodeB from instruction
328
329 decodes register RB, different forms of immediate (signed, unsigned),
330 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
331 by industry-standard convention, "lane 2" is where fully-decoded
332 immediates are muxed in.
333 """
334
335 def __init__(self, dec):
336 self.dec = dec
337 self.sv_rm = SVP64Rec() # SVP64 RM field
338 self.sel_in = Signal(In2Sel, reset_less=True)
339 self.insn_in = Signal(32, reset_less=True)
340 self.reg_out = Data(7, "reg_b")
341 self.reg_isvec = Signal(1, name="reg_b_isvec") # TODO: in reg_out
342 self.fast_out = Data(3, "fast_b")
343
344 def elaborate(self, platform):
345 m = Module()
346 comb = m.d.comb
347 op = self.dec.op
348 m.submodules.svdec = svdec = SVP64RegExtra()
349
350 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
351 reg = Signal(5, reset_less=True)
352
353 # select Register B field
354 with m.Switch(self.sel_in):
355 with m.Case(In2Sel.RB):
356 comb += reg.eq(self.dec.RB)
357 comb += self.reg_out.ok.eq(1)
358 with m.Case(In2Sel.RS):
359 # for M-Form shiftrot
360 comb += reg.eq(self.dec.RS)
361 comb += self.reg_out.ok.eq(1)
362
363 # now do the SVP64 munging. different from DecodeA only by sv_in2
364
365 extra = self.sv_rm.extra # SVP64 extra bits 10:18
366 comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
367 comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
368 comb += svdec.idx.eq(op.sv_in2) # SVP64 reg #2 (matches in2_sel)
369 comb += svdec.reg_in.eq(reg) # 5-bit (RA, RS)
370
371 # outputs: 7-bit reg number and whether it's vectorised
372 comb += self.reg_out.data.eq(svdec.reg_out)
373 comb += self.reg_isvec.eq(svdec.isvec)
374
375 # decode SPR2 based on instruction type
376 # BCREG implicitly uses LR or TAR for 2nd reg
377 # CTR however is already in fast_spr1 *not* 2.
378 with m.If(op.internal_op == MicrOp.OP_BCREG):
379 xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
380 xo5 = self.dec.FormXL.XO[5] # 3.0B p38
381 with m.If(~xo9):
382 comb += self.fast_out.data.eq(FastRegs.LR)
383 comb += self.fast_out.ok.eq(1)
384 with m.Elif(xo5):
385 comb += self.fast_out.data.eq(FastRegs.TAR)
386 comb += self.fast_out.ok.eq(1)
387
388 return m
389
390
391 class DecodeBImm(Elaboratable):
392 """DecodeB immediate from instruction
393 """
394 def __init__(self, dec):
395 self.dec = dec
396 self.sel_in = Signal(In2Sel, reset_less=True)
397 self.imm_out = Data(64, "imm_b")
398
399 def elaborate(self, platform):
400 m = Module()
401 comb = m.d.comb
402
403 # select Register B Immediate
404 with m.Switch(self.sel_in):
405 with m.Case(In2Sel.CONST_UI): # unsigned
406 comb += self.imm_out.data.eq(self.dec.UI)
407 comb += self.imm_out.ok.eq(1)
408 with m.Case(In2Sel.CONST_SI): # sign-extended 16-bit
409 si = Signal(16, reset_less=True)
410 comb += si.eq(self.dec.SI)
411 comb += self.imm_out.data.eq(exts(si, 16, 64))
412 comb += self.imm_out.ok.eq(1)
413 with m.Case(In2Sel.CONST_SI_HI): # sign-extended 16+16=32 bit
414 si_hi = Signal(32, reset_less=True)
415 comb += si_hi.eq(self.dec.SI << 16)
416 comb += self.imm_out.data.eq(exts(si_hi, 32, 64))
417 comb += self.imm_out.ok.eq(1)
418 with m.Case(In2Sel.CONST_UI_HI): # unsigned
419 ui = Signal(16, reset_less=True)
420 comb += ui.eq(self.dec.UI)
421 comb += self.imm_out.data.eq(ui << 16)
422 comb += self.imm_out.ok.eq(1)
423 with m.Case(In2Sel.CONST_LI): # sign-extend 24+2=26 bit
424 li = Signal(26, reset_less=True)
425 comb += li.eq(self.dec.LI << 2)
426 comb += self.imm_out.data.eq(exts(li, 26, 64))
427 comb += self.imm_out.ok.eq(1)
428 with m.Case(In2Sel.CONST_BD): # sign-extend (14+2)=16 bit
429 bd = Signal(16, reset_less=True)
430 comb += bd.eq(self.dec.BD << 2)
431 comb += self.imm_out.data.eq(exts(bd, 16, 64))
432 comb += self.imm_out.ok.eq(1)
433 with m.Case(In2Sel.CONST_DS): # sign-extended (14+2=16) bit
434 ds = Signal(16, reset_less=True)
435 comb += ds.eq(self.dec.DS << 2)
436 comb += self.imm_out.data.eq(exts(ds, 16, 64))
437 comb += self.imm_out.ok.eq(1)
438 with m.Case(In2Sel.CONST_M1): # signed (-1)
439 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
440 comb += self.imm_out.ok.eq(1)
441 with m.Case(In2Sel.CONST_SH): # unsigned - for shift
442 comb += self.imm_out.data.eq(self.dec.sh)
443 comb += self.imm_out.ok.eq(1)
444 with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
445 comb += self.imm_out.data.eq(self.dec.SH32)
446 comb += self.imm_out.ok.eq(1)
447
448 return m
449
450
451 class DecodeC(Elaboratable):
452 """DecodeC from instruction
453
454 decodes register RC. this is "lane 3" into some CompUnits (not many)
455 """
456
457 def __init__(self, dec):
458 self.dec = dec
459 self.sv_rm = SVP64Rec() # SVP64 RM field
460 self.sel_in = Signal(In3Sel, reset_less=True)
461 self.insn_in = Signal(32, reset_less=True)
462 self.reg_out = Data(7, "reg_c")
463 self.reg_isvec = Signal(1, name="reg_c_isvec") # TODO: in reg_out
464
465 def elaborate(self, platform):
466 m = Module()
467 comb = m.d.comb
468 op = self.dec.op
469 m.submodules.svdec = svdec = SVP64RegExtra()
470
471 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
472 reg = Signal(5, reset_less=True)
473
474 # select Register C field
475 with m.Switch(self.sel_in):
476 with m.Case(In3Sel.RB):
477 # for M-Form shiftrot
478 comb += reg.eq(self.dec.RB)
479 comb += self.reg_out.ok.eq(1)
480 with m.Case(In3Sel.RS):
481 comb += reg.eq(self.dec.RS)
482 comb += self.reg_out.ok.eq(1)
483
484 # now do the SVP64 munging. different from DecodeA only by sv_in3
485
486 extra = self.sv_rm.extra # SVP64 extra bits 10:18
487 comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
488 comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
489 comb += svdec.idx.eq(op.sv_in3) # SVP64 reg #3 (matches in3_sel)
490 comb += svdec.reg_in.eq(reg) # 5-bit (RA, RS)
491
492 # outputs: 7-bit reg number and whether it's vectorised
493 comb += self.reg_out.data.eq(svdec.reg_out)
494 comb += self.reg_isvec.eq(svdec.isvec)
495
496 return m
497
498
499 class DecodeOut(Elaboratable):
500 """DecodeOut from instruction
501
502 decodes output register RA, RT or SPR
503 """
504
505 def __init__(self, dec):
506 self.dec = dec
507 self.sv_rm = SVP64Rec() # SVP64 RM field
508 self.sel_in = Signal(OutSel, reset_less=True)
509 self.insn_in = Signal(32, reset_less=True)
510 self.reg_out = Data(7, "reg_o")
511 self.reg_isvec = Signal(1, name="reg_o_isvec") # TODO: in reg_out
512 self.spr_out = Data(SPR, "spr_o")
513 self.fast_out = Data(3, "fast_o")
514
515 def elaborate(self, platform):
516 m = Module()
517 comb = m.d.comb
518 m.submodules.sprmap = sprmap = SPRMap()
519 op = self.dec.op
520 m.submodules.svdec = svdec = SVP64RegExtra()
521
522 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
523 reg = Signal(5, reset_less=True)
524
525 # select Register out field
526 with m.Switch(self.sel_in):
527 with m.Case(OutSel.RT):
528 comb += reg.eq(self.dec.RT)
529 comb += self.reg_out.ok.eq(1)
530 with m.Case(OutSel.RA):
531 comb += reg.eq(self.dec.RA)
532 comb += self.reg_out.ok.eq(1)
533 with m.Case(OutSel.SPR):
534 spr = Signal(10, reset_less=True)
535 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
536 # MFSPR move to SPRs - needs mapping
537 with m.If(op.internal_op == MicrOp.OP_MTSPR):
538 comb += sprmap.spr_i.eq(spr)
539 comb += self.spr_out.eq(sprmap.spr_o)
540 comb += self.fast_out.eq(sprmap.fast_o)
541
542 # now do the SVP64 munging. different from DecodeA only by sv_out
543
544 extra = self.sv_rm.extra # SVP64 extra bits 10:18
545 comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
546 comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
547 comb += svdec.idx.eq(op.sv_out) # SVP64 reg out1 (matches out_sel)
548 comb += svdec.reg_in.eq(reg) # 5-bit (RA, RS)
549
550 # outputs: 7-bit reg number and whether it's vectorised
551 comb += self.reg_out.data.eq(svdec.reg_out)
552 comb += self.reg_isvec.eq(svdec.isvec)
553
554 # determine Fast Reg
555 with m.Switch(op.internal_op):
556
557 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
558 with m.Case(MicrOp.OP_BC, MicrOp.OP_BCREG):
559 with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
560 # constant: CTR
561 comb += self.fast_out.data.eq(FastRegs.CTR)
562 comb += self.fast_out.ok.eq(1)
563
564 # RFID 1st spr (fast)
565 with m.Case(MicrOp.OP_RFID):
566 comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
567 comb += self.fast_out.ok.eq(1)
568
569 return m
570
571
572 class DecodeOut2(Elaboratable):
573 """DecodeOut2 from instruction
574
575 decodes output registers (2nd one). note that RA is *implicit* below,
576 which now causes problems with SVP64
577
578 TODO: SVP64 is a little more complex, here. svp64 allows extending
579 by one more destination by having one more EXTRA field. RA-as-src
580 is not the same as RA-as-dest. limited in that it's the same first
581 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
582 for operations that have src-as-dest: mostly this is LD/ST-with-update
583 but there are others.
584 """
585
586 def __init__(self, dec):
587 self.dec = dec
588 self.sv_rm = SVP64Rec() # SVP64 RM field
589 self.sel_in = Signal(OutSel, reset_less=True)
590 self.lk = Signal(reset_less=True)
591 self.insn_in = Signal(32, reset_less=True)
592 self.reg_out = Data(7, "reg_o2")
593 #self.reg_isvec = Signal(1, name="reg_o2_isvec") # TODO: in reg_out
594 self.fast_out = Data(3, "fast_o2")
595
596 def elaborate(self, platform):
597 m = Module()
598 comb = m.d.comb
599 op = self.dec.op
600 #m.submodules.svdec = svdec = SVP64RegExtra()
601
602 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
603 #reg = Signal(5, reset_less=True)
604
605 if hasattr(self.dec.op, "upd"):
606 # update mode LD/ST uses read-reg A also as an output
607 with m.If(self.dec.op.upd == LDSTMode.update):
608 comb += self.reg_out.data.eq(self.dec.RA)
609 comb += self.reg_out.ok.eq(1)
610
611 # B, BC or BCREG: potential implicit register (LR) output
612 # these give bl, bcl, bclrl, etc.
613 with m.Switch(op.internal_op):
614
615 # BC* implicit register (LR)
616 with m.Case(MicrOp.OP_BC, MicrOp.OP_B, MicrOp.OP_BCREG):
617 with m.If(self.lk): # "link" mode
618 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
619 comb += self.fast_out.ok.eq(1)
620
621 # RFID 2nd spr (fast)
622 with m.Case(MicrOp.OP_RFID):
623 comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
624 comb += self.fast_out.ok.eq(1)
625
626 return m
627
628
629 class DecodeRC(Elaboratable):
630 """DecodeRc from instruction
631
632 decodes Record bit Rc
633 """
634
635 def __init__(self, dec):
636 self.dec = dec
637 self.sel_in = Signal(RC, reset_less=True)
638 self.insn_in = Signal(32, reset_less=True)
639 self.rc_out = Data(1, "rc")
640
641 def elaborate(self, platform):
642 m = Module()
643 comb = m.d.comb
644
645 # select Record bit out field
646 with m.Switch(self.sel_in):
647 with m.Case(RC.RC):
648 comb += self.rc_out.data.eq(self.dec.Rc)
649 comb += self.rc_out.ok.eq(1)
650 with m.Case(RC.ONE):
651 comb += self.rc_out.data.eq(1)
652 comb += self.rc_out.ok.eq(1)
653 with m.Case(RC.NONE):
654 comb += self.rc_out.data.eq(0)
655 comb += self.rc_out.ok.eq(1)
656
657 return m
658
659
660 class DecodeOE(Elaboratable):
661 """DecodeOE from instruction
662
663 decodes OE field: uses RC decode detection which might not be good
664
665 -- For now, use "rc" in the decode table to decide whether oe exists.
666 -- This is not entirely correct architecturally: For mulhd and
667 -- mulhdu, the OE field is reserved. It remains to be seen what an
668 -- actual POWER9 does if we set it on those instructions, for now we
669 -- test that further down when assigning to the multiplier oe input.
670 """
671
672 def __init__(self, dec):
673 self.dec = dec
674 self.sel_in = Signal(RC, reset_less=True)
675 self.insn_in = Signal(32, reset_less=True)
676 self.oe_out = Data(1, "oe")
677
678 def elaborate(self, platform):
679 m = Module()
680 comb = m.d.comb
681 op = self.dec.op
682
683 with m.Switch(op.internal_op):
684
685 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
686 # also rotate
687 # XXX ARGH! ignoring OE causes incompatibility with microwatt
688 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
689 with m.Case(MicrOp.OP_MUL_H64, MicrOp.OP_MUL_H32,
690 MicrOp.OP_EXTS, MicrOp.OP_CNTZ,
691 MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC,
692 MicrOp.OP_LOAD, MicrOp.OP_STORE,
693 MicrOp.OP_RLCL, MicrOp.OP_RLCR,
694 MicrOp.OP_EXTSWSLI):
695 pass
696
697 # all other ops decode OE field
698 with m.Default():
699 # select OE bit out field
700 with m.Switch(self.sel_in):
701 with m.Case(RC.RC):
702 comb += self.oe_out.data.eq(self.dec.OE)
703 comb += self.oe_out.ok.eq(1)
704
705 return m
706
707
708 class DecodeCRIn(Elaboratable):
709 """Decodes input CR from instruction
710
711 CR indices - insn fields - (not the data *in* the CR) require only 3
712 bits because they refer to CR0-CR7
713 """
714
715 def __init__(self, dec):
716 self.dec = dec
717 self.sv_rm = SVP64Rec() # SVP64 RM field
718 self.sel_in = Signal(CRInSel, reset_less=True)
719 self.insn_in = Signal(32, reset_less=True)
720 self.cr_bitfield = Data(7, "cr_bitfield")
721 self.cr_bitfield_b = Data(7, "cr_bitfield_b")
722 self.cr_bitfield_o = Data(7, "cr_bitfield_o")
723 self.cr_isvec = Signal(1, name="cr_isvec")
724 self.cr_b_isvec = Signal(1, name="cr_b_isvec")
725 self.cr_o_isvec = Signal(1, name="cr_o_isvec")
726 self.whole_reg = Data(8, "cr_fxm")
727
728 def elaborate(self, platform):
729 m = Module()
730 comb = m.d.comb
731 op = self.dec.op
732 m.submodules.svdec = svdec = SVP64CRExtra()
733 m.submodules.svdec_b = svdec_b = SVP64CRExtra()
734 m.submodules.svdec_o = svdec_o = SVP64CRExtra()
735 m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
736 reverse_o=True)
737
738 # get the 3-bit reg data before svp64-munging it into 7-bit plus isvec
739 cr_bf = Signal(3, reset_less=True)
740 cr_bf_b = Signal(3, reset_less=True)
741 cr_bf_o = Signal(3, reset_less=True)
742
743 # index selection slightly different due to shared CR field sigh
744 cr_a_idx = Signal(SVEXTRA)
745 cr_b_idx = Signal(SVEXTRA)
746
747 # zero-initialisation
748 comb += self.cr_bitfield.ok.eq(0)
749 comb += self.cr_bitfield_b.ok.eq(0)
750 comb += self.cr_bitfield_o.ok.eq(0)
751 comb += self.whole_reg.ok.eq(0)
752
753 # these change slighly, when decoding BA/BB. really should have
754 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
755 comb += cr_a_idx.eq(op.sv_cr_in)
756 comb += cr_b_idx.eq(SVEXTRA.NONE)
757 with m.If(op.sv_cr_in == SVEXTRA.Idx_1_2.value):
758 comb += cr_a_idx.eq(SVEXTRA.Idx1)
759 comb += cr_b_idx.eq(SVEXTRA.Idx2)
760
761 # select the relevant CR bitfields
762 with m.Switch(self.sel_in):
763 with m.Case(CRInSel.NONE):
764 pass # No bitfield activated
765 with m.Case(CRInSel.CR0):
766 comb += cr_bf.eq(0) # CR0 (MSB0 numbering)
767 comb += self.cr_bitfield.ok.eq(1)
768 with m.Case(CRInSel.BI):
769 comb += cr_bf.eq(self.dec.BI[2:5])
770 comb += self.cr_bitfield.ok.eq(1)
771 with m.Case(CRInSel.BFA):
772 comb += cr_bf.eq(self.dec.FormX.BFA)
773 comb += self.cr_bitfield.ok.eq(1)
774 with m.Case(CRInSel.BA_BB):
775 comb += cr_bf.eq(self.dec.BA[2:5])
776 comb += self.cr_bitfield.ok.eq(1)
777 comb += cr_bf_b.eq(self.dec.BB[2:5])
778 comb += self.cr_bitfield_b.ok.eq(1)
779 comb += cr_bf_o.eq(self.dec.BT[2:5])
780 comb += self.cr_bitfield_o.ok.eq(1)
781 with m.Case(CRInSel.BC):
782 comb += cr_bf.eq(self.dec.BC[2:5])
783 comb += self.cr_bitfield.ok.eq(1)
784 with m.Case(CRInSel.WHOLE_REG):
785 comb += self.whole_reg.ok.eq(1)
786 move_one = Signal(reset_less=True)
787 comb += move_one.eq(self.insn_in[20]) # MSB0 bit 11
788 with m.If((op.internal_op == MicrOp.OP_MFCR) & move_one):
789 # must one-hot the FXM field
790 comb += ppick.i.eq(self.dec.FXM)
791 comb += self.whole_reg.data.eq(ppick.o)
792 with m.Else():
793 # otherwise use all of it
794 comb += self.whole_reg.data.eq(0xff)
795
796 # now do the SVP64 munging.
797 extra = self.sv_rm.extra # SVP64 extra bits 10:18
798
799 comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
800 comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
801 comb += svdec.cr_in.eq(cr_bf) # 3-bit (CR0/BC/BFA)
802
803 comb += svdec_b.extra.eq(extra) # EXTRA field of SVP64 RM
804 comb += svdec_b.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
805 comb += svdec_b.cr_in.eq(cr_bf_b) # 3-bit (BB[2:5])
806
807 comb += svdec_o.extra.eq(extra) # EXTRA field of SVP64 RM
808 comb += svdec_o.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
809 comb += svdec_o.cr_in.eq(cr_bf_o) # 3-bit (BT[2:5])
810
811 # indices are slightly different, BA/BB mess sorted above
812 comb += svdec.idx.eq(cr_a_idx) # SVP64 CR in A
813 comb += svdec_b.idx.eq(cr_b_idx) # SVP64 CR in B
814 comb += svdec_o.idx.eq(op.sv_cr_out) # SVP64 CR out
815
816 # outputs: 7-bit reg number and whether it's vectorised
817 comb += self.cr_bitfield.data.eq(svdec.cr_out)
818 comb += self.cr_isvec.eq(svdec.isvec)
819 comb += self.cr_bitfield_b.data.eq(svdec_b.cr_out)
820 comb += self.cr_b_isvec.eq(svdec_b.isvec)
821 comb += self.cr_bitfield_o.data.eq(svdec_o.cr_out)
822 comb += self.cr_o_isvec.eq(svdec_o.isvec)
823
824 return m
825
826
827 class DecodeCROut(Elaboratable):
828 """Decodes input CR from instruction
829
830 CR indices - insn fields - (not the data *in* the CR) require only 3
831 bits because they refer to CR0-CR7
832 """
833
834 def __init__(self, dec):
835 self.dec = dec
836 self.sv_rm = SVP64Rec() # SVP64 RM field
837 self.rc_in = Signal(reset_less=True)
838 self.sel_in = Signal(CROutSel, reset_less=True)
839 self.insn_in = Signal(32, reset_less=True)
840 self.cr_bitfield = Data(7, "cr_bitfield")
841 self.cr_isvec = Signal(1, name="cr_isvec")
842 self.whole_reg = Data(8, "cr_fxm")
843
844 def elaborate(self, platform):
845 m = Module()
846 comb = m.d.comb
847 op = self.dec.op
848 m.submodules.svdec = svdec = SVP64CRExtra()
849 m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
850 reverse_o=True)
851
852 # get the 3-bit reg data before svp64-munging it into 7-bit plus isvec
853 cr_bf = Signal(3, reset_less=True)
854
855 comb += self.cr_bitfield.ok.eq(0)
856 comb += self.whole_reg.ok.eq(0)
857
858 with m.Switch(self.sel_in):
859 with m.Case(CROutSel.NONE):
860 pass # No bitfield activated
861 with m.Case(CROutSel.CR0):
862 comb += cr_bf.eq(0) # CR0 (MSB0 numbering)
863 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
864 with m.Case(CROutSel.BF):
865 comb += cr_bf.eq(self.dec.FormX.BF)
866 comb += self.cr_bitfield.ok.eq(1)
867 with m.Case(CROutSel.BT):
868 comb += cr_bf.eq(self.dec.FormXL.BT[2:5])
869 comb += self.cr_bitfield.ok.eq(1)
870 with m.Case(CROutSel.WHOLE_REG):
871 comb += self.whole_reg.ok.eq(1)
872 move_one = Signal(reset_less=True)
873 comb += move_one.eq(self.insn_in[20])
874 with m.If((op.internal_op == MicrOp.OP_MTCRF)):
875 with m.If(move_one):
876 # must one-hot the FXM field
877 comb += ppick.i.eq(self.dec.FXM)
878 with m.If(ppick.en_o):
879 comb += self.whole_reg.data.eq(ppick.o)
880 with m.Else():
881 comb += self.whole_reg.data.eq(0b00000001) # CR7
882 with m.Else():
883 comb += self.whole_reg.data.eq(self.dec.FXM)
884 with m.Else():
885 # otherwise use all of it
886 comb += self.whole_reg.data.eq(0xff)
887
888 # now do the SVP64 munging.
889 extra = self.sv_rm.extra # SVP64 extra bits 10:18
890 comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
891 comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
892 comb += svdec.cr_in.eq(cr_bf) # 3-bit (CR0/BC/BFA)
893 comb += svdec.idx.eq(op.sv_cr_out) # SVP64 CR out
894
895 # outputs: 7-bit reg number and whether it's vectorised
896 comb += self.cr_bitfield.data.eq(svdec.cr_out)
897 comb += self.cr_isvec.eq(svdec.isvec)
898
899 return m
900
901 # dictionary of Input Record field names that, if they exist,
902 # will need a corresponding CSV Decoder file column (actually, PowerOp)
903 # to be decoded (this includes the single bit names)
904 record_names = {'insn_type': 'internal_op',
905 'fn_unit': 'function_unit',
906 'rc': 'rc_sel',
907 'oe': 'rc_sel',
908 'zero_a': 'in1_sel',
909 'imm_data': 'in2_sel',
910 'invert_in': 'inv_a',
911 'invert_out': 'inv_out',
912 'rc': 'cr_out',
913 'oe': 'cr_in',
914 'output_carry': 'cry_out',
915 'input_carry': 'cry_in',
916 'is_32bit': 'is_32b',
917 'is_signed': 'sgn',
918 'lk': 'lk',
919 'data_len': 'ldst_len',
920 'byte_reverse': 'br',
921 'sign_extend': 'sgn_ext',
922 'ldst_mode': 'upd',
923 }
924
925
926 class PowerDecodeSubset(Elaboratable):
927 """PowerDecodeSubset: dynamic subset decoder
928
929 only fields actually requested are copied over. hence, "subset" (duh).
930 """
931 def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None):
932
933 self.sv_rm = SVP64Rec(name="dec_svp64") # SVP64 RM field
934 self.final = final
935 self.opkls = opkls
936 self.fn_name = fn_name
937 if opkls is None:
938 opkls = Decode2ToOperand
939 self.do = opkls(fn_name)
940 col_subset = self.get_col_subset(self.do)
941
942 # only needed for "main" PowerDecode2
943 if not self.final:
944 self.e = Decode2ToExecute1Type(name=self.fn_name, do=self.do)
945
946 # create decoder if one not already given
947 if dec is None:
948 dec = create_pdecode(name=fn_name, col_subset=col_subset,
949 row_subset=self.rowsubsetfn)
950 self.dec = dec
951
952 # state information needed by the Decoder
953 if state is None:
954 state = CoreState("dec2")
955 self.state = state
956
957 def get_col_subset(self, do):
958 subset = {'sv_cr_in', 'sv_cr_out', 'SV_Etype',
959 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
960 for k, v in record_names.items():
961 if hasattr(do, k):
962 subset.add(v)
963 print ("get_col_subset", self.fn_name, do.fields, subset)
964 return subset
965
966 def rowsubsetfn(self, opcode, row):
967 return row['unit'] == self.fn_name
968
969 def ports(self):
970 return self.dec.ports() + self.e.ports() + self.sv_rm.ports()
971
972 def needs_field(self, field, op_field):
973 if self.final:
974 do = self.do
975 else:
976 do = self.e_tmp.do
977 return hasattr(do, field) and self.op_get(op_field) is not None
978
979 def do_copy(self, field, val, final=False):
980 if final or self.final:
981 do = self.do
982 else:
983 do = self.e_tmp.do
984 if hasattr(do, field) and val is not None:
985 return getattr(do, field).eq(val)
986 return []
987
988 def op_get(self, op_field):
989 return getattr(self.dec.op, op_field, None)
990
991 def elaborate(self, platform):
992 m = Module()
993 comb = m.d.comb
994 state = self.state
995 op, do = self.dec.op, self.do
996 msr, cia = state.msr, state.pc
997
998 # fill in for a normal instruction (not an exception)
999 # copy over if non-exception, non-privileged etc. is detected
1000 if not self.final:
1001 if self.fn_name is None:
1002 name = "tmp"
1003 else:
1004 name = self.fn_name + "tmp"
1005 self.e_tmp = Decode2ToExecute1Type(name=name, opkls=self.opkls)
1006
1007 # set up submodule decoders
1008 m.submodules.dec = self.dec
1009 m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
1010 m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
1011 m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec)
1012 m.submodules.dec_cr_out = self.dec_cr_out = DecodeCROut(self.dec)
1013
1014 # copy instruction through...
1015 for i in [do.insn,
1016 dec_rc.insn_in, dec_oe.insn_in,
1017 self.dec_cr_in.insn_in, self.dec_cr_out.insn_in]:
1018 comb += i.eq(self.dec.opcode_in)
1019
1020 # ...and subdecoders' input fields
1021 comb += dec_rc.sel_in.eq(op.rc_sel)
1022 comb += dec_oe.sel_in.eq(op.rc_sel) # XXX should be OE sel
1023 comb += self.dec_cr_in.sel_in.eq(op.cr_in)
1024 comb += self.dec_cr_in.sv_rm.eq(self.sv_rm)
1025 comb += self.dec_cr_out.sv_rm.eq(self.sv_rm)
1026 comb += self.dec_cr_out.sel_in.eq(op.cr_out)
1027 comb += self.dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
1028
1029 # copy "state" over
1030 comb += self.do_copy("msr", msr)
1031 comb += self.do_copy("cia", cia)
1032
1033 # set up instruction type
1034 # no op: defaults to OP_ILLEGAL
1035 comb += self.do_copy("insn_type", self.op_get("internal_op"))
1036
1037 # function unit for decoded instruction: requires minor redirect
1038 # for SPR set/get
1039 fn = self.op_get("function_unit")
1040 spr = Signal(10, reset_less=True)
1041 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
1042
1043 # for first test only forward SPRs 18 and 19 to MMU, when
1044 # operation is MTSPR or MFSPR. TODO: add other MMU SPRs
1045 with m.If(((self.dec.op.internal_op == MicrOp.OP_MTSPR) |
1046 (self.dec.op.internal_op == MicrOp.OP_MFSPR)) &
1047 ((spr == SPR.DSISR) | (spr == SPR.DAR))):
1048 comb += self.do_copy("fn_unit", Function.MMU)
1049 with m.Else():
1050 comb += self.do_copy("fn_unit",fn)
1051
1052 # immediates
1053 if self.needs_field("zero_a", "in1_sel"):
1054 m.submodules.dec_ai = dec_ai = DecodeAImm(self.dec)
1055 comb += dec_ai.sel_in.eq(op.in1_sel)
1056 comb += self.do_copy("zero_a", dec_ai.immz_out) # RA==0 detected
1057 if self.needs_field("imm_data", "in2_sel"):
1058 m.submodules.dec_bi = dec_bi = DecodeBImm(self.dec)
1059 comb += dec_bi.sel_in.eq(op.in2_sel)
1060 comb += self.do_copy("imm_data", dec_bi.imm_out) # imm in RB
1061
1062 # rc and oe out
1063 comb += self.do_copy("rc", dec_rc.rc_out)
1064 comb += self.do_copy("oe", dec_oe.oe_out)
1065
1066 # CR in/out
1067 comb += self.do_copy("read_cr_whole", self.dec_cr_in.whole_reg)
1068 comb += self.do_copy("write_cr_whole", self.dec_cr_out.whole_reg)
1069 comb += self.do_copy("write_cr0", self.dec_cr_out.cr_bitfield.ok)
1070
1071 comb += self.do_copy("input_cr", self.op_get("cr_in")) # CR in
1072 comb += self.do_copy("output_cr", self.op_get("cr_out")) # CR out
1073
1074 # decoded/selected instruction flags
1075 comb += self.do_copy("data_len", self.op_get("ldst_len"))
1076 comb += self.do_copy("invert_in", self.op_get("inv_a"))
1077 comb += self.do_copy("invert_out", self.op_get("inv_out"))
1078 comb += self.do_copy("input_carry", self.op_get("cry_in"))
1079 comb += self.do_copy("output_carry", self.op_get("cry_out"))
1080 comb += self.do_copy("is_32bit", self.op_get("is_32b"))
1081 comb += self.do_copy("is_signed", self.op_get("sgn"))
1082 lk = self.op_get("lk")
1083 if lk is not None:
1084 with m.If(lk):
1085 comb += self.do_copy("lk", self.dec.LK) # XXX TODO: accessor
1086
1087 comb += self.do_copy("byte_reverse", self.op_get("br"))
1088 comb += self.do_copy("sign_extend", self.op_get("sgn_ext"))
1089 comb += self.do_copy("ldst_mode", self.op_get("upd")) # LD/ST mode
1090
1091 return m
1092
1093
1094 class PowerDecode2(PowerDecodeSubset):
1095 """PowerDecode2: the main instruction decoder.
1096
1097 whilst PowerDecode is responsible for decoding the actual opcode, this
1098 module encapsulates further specialist, sparse information and
1099 expansion of fields that is inconvenient to have in the CSV files.
1100 for example: the encoding of the immediates, which are detected
1101 and expanded out to their full value from an annotated (enum)
1102 representation.
1103
1104 implicit register usage is also set up, here. for example: OP_BC
1105 requires implicitly reading CTR, OP_RFID requires implicitly writing
1106 to SRR1 and so on.
1107
1108 in addition, PowerDecoder2 is responsible for detecting whether
1109 instructions are illegal (or privileged) or not, and instead of
1110 just leaving at that, *replacing* the instruction to execute with
1111 a suitable alternative (trap).
1112
1113 LDSTExceptions are done the cycle _after_ they're detected (after
1114 they come out of LDSTCompUnit). basically despite the instruction
1115 being decoded, the results of the decode are completely ignored
1116 and "exception.happened" used to set the "actual" instruction to
1117 "OP_TRAP". the LDSTException data structure gets filled in,
1118 in the CompTrapOpSubset and that's what it fills in SRR.
1119
1120 to make this work, TestIssuer must notice "exception.happened"
1121 after the (failed) LD/ST and copies the LDSTException info from
1122 the output, into here (PowerDecoder2). without incrementing PC.
1123 """
1124
1125 def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None):
1126 super().__init__(dec, opkls, fn_name, final, state)
1127 self.exc = LDSTException("dec2_exc")
1128
1129 def get_col_subset(self, opkls):
1130 subset = super().get_col_subset(opkls)
1131 subset.add("asmcode")
1132 subset.add("in1_sel")
1133 subset.add("in2_sel")
1134 subset.add("in3_sel")
1135 subset.add("out_sel")
1136 subset.add("sv_in1")
1137 subset.add("sv_in2")
1138 subset.add("sv_in3")
1139 subset.add("sv_out")
1140 subset.add("sv_cr_in")
1141 subset.add("sv_cr_out")
1142 subset.add("SV_Etype")
1143 subset.add("SV_Ptype")
1144 subset.add("lk")
1145 subset.add("internal_op")
1146 subset.add("form")
1147 return subset
1148
1149 def elaborate(self, platform):
1150 m = super().elaborate(platform)
1151 comb = m.d.comb
1152 state = self.state
1153 e_out, op, do_out = self.e, self.dec.op, self.e.do
1154 dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
1155 e = self.e_tmp
1156 do = e.do
1157
1158 # fill in for a normal instruction (not an exception)
1159 # copy over if non-exception, non-privileged etc. is detected
1160
1161 # set up submodule decoders
1162 m.submodules.dec_a = dec_a = DecodeA(self.dec)
1163 m.submodules.dec_b = dec_b = DecodeB(self.dec)
1164 m.submodules.dec_c = dec_c = DecodeC(self.dec)
1165 m.submodules.dec_o = dec_o = DecodeOut(self.dec)
1166 m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
1167
1168 # copy instruction through...
1169 for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
1170 dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]:
1171 comb += i.eq(self.dec.opcode_in)
1172
1173 # ... and svp64 rm
1174 for i in [dec_a.insn_in, dec_b.insn_in,
1175 dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]:
1176 comb += i.eq(self.sv_rm)
1177
1178 # ...and subdecoders' input fields
1179 comb += dec_a.sel_in.eq(op.in1_sel)
1180 comb += dec_b.sel_in.eq(op.in2_sel)
1181 comb += dec_c.sel_in.eq(op.in3_sel)
1182 comb += dec_o.sel_in.eq(op.out_sel)
1183 comb += dec_o2.sel_in.eq(op.out_sel)
1184 if hasattr(do, "lk"):
1185 comb += dec_o2.lk.eq(do.lk)
1186
1187 # registers a, b, c and out and out2 (LD/ST EA)
1188 for to_reg, fromreg in (
1189 (e.read_reg1, dec_a.reg_out),
1190 (e.read_reg2, dec_b.reg_out),
1191 (e.read_reg3, dec_c.reg_out),
1192 (e.write_reg, dec_o.reg_out),
1193 (e.write_ea, dec_o2.reg_out)):
1194 comb += to_reg.data.eq(fromreg.data)
1195 comb += to_reg.ok.eq(fromreg.ok)
1196
1197 # SPRs out
1198 comb += e.read_spr1.eq(dec_a.spr_out)
1199 comb += e.write_spr.eq(dec_o.spr_out)
1200
1201 # Fast regs out
1202 comb += e.read_fast1.eq(dec_a.fast_out)
1203 comb += e.read_fast2.eq(dec_b.fast_out)
1204 comb += e.write_fast1.eq(dec_o.fast_out)
1205 comb += e.write_fast2.eq(dec_o2.fast_out)
1206
1207 # condition registers (CR)
1208 for to_reg, fromreg in (
1209 (e.read_cr1, self.dec_cr_in.cr_bitfield),
1210 (e.read_cr2, self.dec_cr_in.cr_bitfield_b),
1211 (e.read_cr3, self.dec_cr_in.cr_bitfield_o),
1212 (e.write_cr, self.dec_cr_out.cr_bitfield)):
1213 comb += to_reg.data.eq(fromreg.data)
1214 comb += to_reg.ok.eq(fromreg.ok)
1215
1216 # sigh this is exactly the sort of thing for which the
1217 # decoder is designed to not need. MTSPR, MFSPR and others need
1218 # access to the XER bits. however setting e.oe is not appropriate
1219 with m.If(op.internal_op == MicrOp.OP_MFSPR):
1220 comb += e.xer_in.eq(0b111) # SO, CA, OV
1221 with m.If(op.internal_op == MicrOp.OP_CMP):
1222 comb += e.xer_in.eq(1<<XERRegs.SO) # SO
1223 with m.If(op.internal_op == MicrOp.OP_MTSPR):
1224 comb += e.xer_out.eq(1)
1225
1226 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1227 with m.If(op.internal_op == MicrOp.OP_TRAP):
1228 # *DO NOT* call self.trap here. that would reset absolutely
1229 # everything including destroying read of RA and RB.
1230 comb += self.do_copy("trapaddr", 0x70) # strip first nibble
1231
1232 ####################
1233 # ok so the instruction's been decoded, blah blah, however
1234 # now we need to determine if it's actually going to go ahead...
1235 # *or* if in fact it's a privileged operation, whether there's
1236 # an external interrupt, etc. etc. this is a simple priority
1237 # if-elif-elif sequence. decrement takes highest priority,
1238 # EINT next highest, privileged operation third.
1239
1240 # check if instruction is privileged
1241 is_priv_insn = instr_is_priv(m, op.internal_op, e.do.insn)
1242
1243 # different IRQ conditions
1244 ext_irq_ok = Signal()
1245 dec_irq_ok = Signal()
1246 priv_ok = Signal()
1247 illeg_ok = Signal()
1248 exc = self.exc
1249
1250 comb += ext_irq_ok.eq(ext_irq & msr[MSR.EE]) # v3.0B p944 (MSR.EE)
1251 comb += dec_irq_ok.eq(dec_spr[63] & msr[MSR.EE]) # 6.5.11 p1076
1252 comb += priv_ok.eq(is_priv_insn & msr[MSR.PR])
1253 comb += illeg_ok.eq(op.internal_op == MicrOp.OP_ILLEGAL)
1254
1255 # LD/ST exceptions. TestIssuer copies the exception info at us
1256 # after a failed LD/ST.
1257 with m.If(exc.happened):
1258 with m.If(exc.alignment):
1259 self.trap(m, TT.PRIV, 0x600)
1260 with m.Elif(exc.instr_fault):
1261 with m.If(exc.segment_fault):
1262 self.trap(m, TT.PRIV, 0x480)
1263 with m.Else():
1264 # pass exception info to trap to create SRR1
1265 self.trap(m, TT.MEMEXC, 0x400, exc)
1266 with m.Else():
1267 with m.If(exc.segment_fault):
1268 self.trap(m, TT.PRIV, 0x380)
1269 with m.Else():
1270 self.trap(m, TT.PRIV, 0x300)
1271
1272 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1273 with m.Elif(dec_irq_ok):
1274 self.trap(m, TT.DEC, 0x900) # v3.0B 6.5 p1065
1275
1276 # external interrupt? only if MSR.EE set
1277 with m.Elif(ext_irq_ok):
1278 self.trap(m, TT.EINT, 0x500)
1279
1280 # privileged instruction trap
1281 with m.Elif(priv_ok):
1282 self.trap(m, TT.PRIV, 0x700)
1283
1284 # illegal instruction must redirect to trap. this is done by
1285 # *overwriting* the decoded instruction and starting again.
1286 # (note: the same goes for interrupts and for privileged operations,
1287 # just with different trapaddr and traptype)
1288 with m.Elif(illeg_ok):
1289 # illegal instruction trap
1290 self.trap(m, TT.ILLEG, 0x700)
1291
1292 # no exception, just copy things to the output
1293 with m.Else():
1294 comb += e_out.eq(e)
1295
1296 ####################
1297 # follow-up after trap/irq to set up SRR0/1
1298
1299 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1300 # Note: OP_SC could actually be modified to just be a trap
1301 with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
1302 (do_out.insn_type == MicrOp.OP_SC)):
1303 # TRAP write fast1 = SRR0
1304 comb += e_out.write_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
1305 comb += e_out.write_fast1.ok.eq(1)
1306 # TRAP write fast2 = SRR1
1307 comb += e_out.write_fast2.data.eq(FastRegs.SRR1) # constant: SRR1
1308 comb += e_out.write_fast2.ok.eq(1)
1309
1310 # RFID: needs to read SRR0/1
1311 with m.If(do_out.insn_type == MicrOp.OP_RFID):
1312 # TRAP read fast1 = SRR0
1313 comb += e_out.read_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
1314 comb += e_out.read_fast1.ok.eq(1)
1315 # TRAP read fast2 = SRR1
1316 comb += e_out.read_fast2.data.eq(FastRegs.SRR1) # constant: SRR1
1317 comb += e_out.read_fast2.ok.eq(1)
1318
1319 # annoying simulator bug
1320 if hasattr(e_out, "asmcode") and hasattr(self.dec.op, "asmcode"):
1321 comb += e_out.asmcode.eq(self.dec.op.asmcode)
1322
1323 return m
1324
1325 def trap(self, m, traptype, trapaddr, exc=None):
1326 """trap: this basically "rewrites" the decoded instruction as a trap
1327 """
1328 comb = m.d.comb
1329 op, e = self.dec.op, self.e
1330 comb += e.eq(0) # reset eeeeeverything
1331
1332 # start again
1333 comb += self.do_copy("insn", self.dec.opcode_in, True)
1334 comb += self.do_copy("insn_type", MicrOp.OP_TRAP, True)
1335 comb += self.do_copy("fn_unit", Function.TRAP, True)
1336 comb += self.do_copy("trapaddr", trapaddr >> 4, True) # bottom 4 bits
1337 comb += self.do_copy("traptype", traptype, True) # request type
1338 comb += self.do_copy("ldst_exc", exc, True) # request type
1339 comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state"
1340 comb += self.do_copy("cia", self.state.pc, True) # copy of PC "state"
1341
1342
1343 def get_rdflags(e, cu):
1344 rdl = []
1345 for idx in range(cu.n_src):
1346 regfile, regname, _ = cu.get_in_spec(idx)
1347 rdflag, read = regspec_decode_read(e, regfile, regname)
1348 rdl.append(rdflag)
1349 print("rdflags", rdl)
1350 return Cat(*rdl)
1351
1352
1353 if __name__ == '__main__':
1354 pdecode = create_pdecode()
1355 dec2 = PowerDecode2(pdecode)
1356 vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
1357 with open("dec2.il", "w") as f:
1358 f.write(vl)