dcache: add debug output
[soc.git] / src / soc / decoder / power_decoder2.py
1 """Power ISA Decoder second stage
2
3 based on Anton Blanchard microwatt decode2.vhdl
4
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
7 """
8
9 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
10 from nmigen.cli import rtlil
11 from nmutil.util import sel
12
13 from soc.regfile.regfiles import XERRegs
14
15 from nmutil.picker import PriorityPicker
16 from nmutil.iocontrol import RecordObject
17 from nmutil.extend import exts
18
19 from soc.experiment.mem_types import LDSTException
20
21 from soc.decoder.power_svp64_prefix import SVP64PrefixDecoder
22 from soc.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
23 from soc.decoder.power_regspec_map import regspec_decode_read
24 from soc.decoder.power_regspec_map import regspec_decode_write
25 from soc.decoder.power_decoder import create_pdecode
26 from soc.decoder.power_enums import (MicrOp, CryIn, Function,
27 CRInSel, CROutSel,
28 LdstLen, In1Sel, In2Sel, In3Sel,
29 OutSel, SPR, RC, LDSTMode,
30 SVEXTRA, SVEtype)
31 from soc.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
32 Decode2ToOperand)
33 from soc.sv.svp64 import SVP64Rec
34 from soc.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field,
35 SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs)
36
37 from soc.regfile.regfiles import FastRegs
38 from soc.consts import TT
39 from soc.config.state import CoreState
40 from soc.regfile.util import spr_to_fast
41
42
43 def decode_spr_num(spr):
44 return Cat(spr[5:10], spr[0:5])
45
46
47 def instr_is_priv(m, op, insn):
48 """determines if the instruction is privileged or not
49 """
50 comb = m.d.comb
51 is_priv_insn = Signal(reset_less=True)
52 with m.Switch(op):
53 with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
54 MicrOp.OP_MTMSR, MicrOp.OP_RFID):
55 comb += is_priv_insn.eq(1)
56 with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
57 with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):
58 with m.If(insn[20]): # field XFX.spr[-1] i think
59 comb += is_priv_insn.eq(1)
60 return is_priv_insn
61
62
63 class SPRMap(Elaboratable):
64 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
65 """
66
67 def __init__(self):
68 self.spr_i = Signal(10, reset_less=True)
69 self.spr_o = Data(SPR, name="spr_o")
70 self.fast_o = Data(3, name="fast_o")
71
72 def elaborate(self, platform):
73 m = Module()
74 with m.Switch(self.spr_i):
75 for i, x in enumerate(SPR):
76 with m.Case(x.value):
77 m.d.comb += self.spr_o.data.eq(i)
78 m.d.comb += self.spr_o.ok.eq(1)
79 for x, v in spr_to_fast.items():
80 with m.Case(x.value):
81 m.d.comb += self.fast_o.data.eq(v)
82 m.d.comb += self.fast_o.ok.eq(1)
83 return m
84
85
86 class DecodeA(Elaboratable):
87 """DecodeA from instruction
88
89 decodes register RA, implicit and explicit CSRs
90 """
91
92 def __init__(self, dec):
93 self.dec = dec
94 self.sel_in = Signal(In1Sel, reset_less=True)
95 self.insn_in = Signal(32, reset_less=True)
96 self.reg_out = Data(5, name="reg_a")
97 self.spr_out = Data(SPR, "spr_a")
98 self.fast_out = Data(3, "fast_a")
99
100 def elaborate(self, platform):
101 m = Module()
102 comb = m.d.comb
103 op = self.dec.op
104 reg = self.reg_out
105 m.submodules.sprmap = sprmap = SPRMap()
106
107 # select Register A field
108 ra = Signal(5, reset_less=True)
109 comb += ra.eq(self.dec.RA)
110 with m.If((self.sel_in == In1Sel.RA) |
111 ((self.sel_in == In1Sel.RA_OR_ZERO) &
112 (ra != Const(0, 5)))):
113 comb += reg.data.eq(ra)
114 comb += reg.ok.eq(1)
115
116 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
117 # moved it to 1st position (in1_sel)... because
118 rs = Signal(5, reset_less=True)
119 comb += rs.eq(self.dec.RS)
120 with m.If(self.sel_in == In1Sel.RS):
121 comb += reg.data.eq(rs)
122 comb += reg.ok.eq(1)
123
124 # decode Fast-SPR based on instruction type
125 with m.Switch(op.internal_op):
126
127 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
128 with m.Case(MicrOp.OP_BC):
129 with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
130 # constant: CTR
131 comb += self.fast_out.data.eq(FastRegs.CTR)
132 comb += self.fast_out.ok.eq(1)
133 with m.Case(MicrOp.OP_BCREG):
134 xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
135 xo5 = self.dec.FormXL.XO[5] # 3.0B p38
136 with m.If(xo9 & ~xo5):
137 # constant: CTR
138 comb += self.fast_out.data.eq(FastRegs.CTR)
139 comb += self.fast_out.ok.eq(1)
140
141 # MFSPR move from SPRs
142 with m.Case(MicrOp.OP_MFSPR):
143 spr = Signal(10, reset_less=True)
144 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
145 comb += sprmap.spr_i.eq(spr)
146 comb += self.spr_out.eq(sprmap.spr_o)
147 comb += self.fast_out.eq(sprmap.fast_o)
148
149 return m
150
151
152 class DecodeAImm(Elaboratable):
153 """DecodeA immediate from instruction
154
155 decodes register RA, whether immediate-zero, implicit and
156 explicit CSRs
157 """
158
159 def __init__(self, dec):
160 self.dec = dec
161 self.sel_in = Signal(In1Sel, reset_less=True)
162 self.immz_out = Signal(reset_less=True)
163
164 def elaborate(self, platform):
165 m = Module()
166 comb = m.d.comb
167
168 # zero immediate requested
169 ra = Signal(5, reset_less=True)
170 comb += ra.eq(self.dec.RA)
171 with m.If((self.sel_in == In1Sel.RA_OR_ZERO) & (ra == Const(0, 5))):
172 comb += self.immz_out.eq(1)
173
174 return m
175
176
177 class DecodeB(Elaboratable):
178 """DecodeB from instruction
179
180 decodes register RB, different forms of immediate (signed, unsigned),
181 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
182 by industry-standard convention, "lane 2" is where fully-decoded
183 immediates are muxed in.
184 """
185
186 def __init__(self, dec):
187 self.dec = dec
188 self.sel_in = Signal(In2Sel, reset_less=True)
189 self.insn_in = Signal(32, reset_less=True)
190 self.reg_out = Data(7, "reg_b")
191 self.reg_isvec = Signal(1, name="reg_b_isvec") # TODO: in reg_out
192 self.fast_out = Data(3, "fast_b")
193
194 def elaborate(self, platform):
195 m = Module()
196 comb = m.d.comb
197 op = self.dec.op
198 reg = self.reg_out
199
200 # select Register B field
201 with m.Switch(self.sel_in):
202 with m.Case(In2Sel.RB):
203 comb += reg.data.eq(self.dec.RB)
204 comb += reg.ok.eq(1)
205 with m.Case(In2Sel.RS):
206 # for M-Form shiftrot
207 comb += reg.data.eq(self.dec.RS)
208 comb += reg.ok.eq(1)
209
210 # decode SPR2 based on instruction type
211 # BCREG implicitly uses LR or TAR for 2nd reg
212 # CTR however is already in fast_spr1 *not* 2.
213 with m.If(op.internal_op == MicrOp.OP_BCREG):
214 xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
215 xo5 = self.dec.FormXL.XO[5] # 3.0B p38
216 with m.If(~xo9):
217 comb += self.fast_out.data.eq(FastRegs.LR)
218 comb += self.fast_out.ok.eq(1)
219 with m.Elif(xo5):
220 comb += self.fast_out.data.eq(FastRegs.TAR)
221 comb += self.fast_out.ok.eq(1)
222
223 return m
224
225
226 class DecodeBImm(Elaboratable):
227 """DecodeB immediate from instruction
228 """
229 def __init__(self, dec):
230 self.dec = dec
231 self.sel_in = Signal(In2Sel, reset_less=True)
232 self.imm_out = Data(64, "imm_b")
233
234 def elaborate(self, platform):
235 m = Module()
236 comb = m.d.comb
237
238 # select Register B Immediate
239 with m.Switch(self.sel_in):
240 with m.Case(In2Sel.CONST_UI): # unsigned
241 comb += self.imm_out.data.eq(self.dec.UI)
242 comb += self.imm_out.ok.eq(1)
243 with m.Case(In2Sel.CONST_SI): # sign-extended 16-bit
244 si = Signal(16, reset_less=True)
245 comb += si.eq(self.dec.SI)
246 comb += self.imm_out.data.eq(exts(si, 16, 64))
247 comb += self.imm_out.ok.eq(1)
248 with m.Case(In2Sel.CONST_SI_HI): # sign-extended 16+16=32 bit
249 si_hi = Signal(32, reset_less=True)
250 comb += si_hi.eq(self.dec.SI << 16)
251 comb += self.imm_out.data.eq(exts(si_hi, 32, 64))
252 comb += self.imm_out.ok.eq(1)
253 with m.Case(In2Sel.CONST_UI_HI): # unsigned
254 ui = Signal(16, reset_less=True)
255 comb += ui.eq(self.dec.UI)
256 comb += self.imm_out.data.eq(ui << 16)
257 comb += self.imm_out.ok.eq(1)
258 with m.Case(In2Sel.CONST_LI): # sign-extend 24+2=26 bit
259 li = Signal(26, reset_less=True)
260 comb += li.eq(self.dec.LI << 2)
261 comb += self.imm_out.data.eq(exts(li, 26, 64))
262 comb += self.imm_out.ok.eq(1)
263 with m.Case(In2Sel.CONST_BD): # sign-extend (14+2)=16 bit
264 bd = Signal(16, reset_less=True)
265 comb += bd.eq(self.dec.BD << 2)
266 comb += self.imm_out.data.eq(exts(bd, 16, 64))
267 comb += self.imm_out.ok.eq(1)
268 with m.Case(In2Sel.CONST_DS): # sign-extended (14+2=16) bit
269 ds = Signal(16, reset_less=True)
270 comb += ds.eq(self.dec.DS << 2)
271 comb += self.imm_out.data.eq(exts(ds, 16, 64))
272 comb += self.imm_out.ok.eq(1)
273 with m.Case(In2Sel.CONST_M1): # signed (-1)
274 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
275 comb += self.imm_out.ok.eq(1)
276 with m.Case(In2Sel.CONST_SH): # unsigned - for shift
277 comb += self.imm_out.data.eq(self.dec.sh)
278 comb += self.imm_out.ok.eq(1)
279 with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
280 comb += self.imm_out.data.eq(self.dec.SH32)
281 comb += self.imm_out.ok.eq(1)
282
283 return m
284
285
286 class DecodeC(Elaboratable):
287 """DecodeC from instruction
288
289 decodes register RC. this is "lane 3" into some CompUnits (not many)
290 """
291
292 def __init__(self, dec):
293 self.dec = dec
294 self.sel_in = Signal(In3Sel, reset_less=True)
295 self.insn_in = Signal(32, reset_less=True)
296 self.reg_out = Data(5, "reg_c")
297
298 def elaborate(self, platform):
299 m = Module()
300 comb = m.d.comb
301 op = self.dec.op
302 reg = self.reg_out
303
304 # select Register C field
305 with m.Switch(self.sel_in):
306 with m.Case(In3Sel.RB):
307 # for M-Form shiftrot
308 comb += reg.data.eq(self.dec.RB)
309 comb += reg.ok.eq(1)
310 with m.Case(In3Sel.RS):
311 comb += reg.data.eq(self.dec.RS)
312 comb += reg.ok.eq(1)
313
314 return m
315
316
317 class DecodeOut(Elaboratable):
318 """DecodeOut from instruction
319
320 decodes output register RA, RT or SPR
321 """
322
323 def __init__(self, dec):
324 self.dec = dec
325 self.sel_in = Signal(OutSel, reset_less=True)
326 self.insn_in = Signal(32, reset_less=True)
327 self.reg_out = Data(5, "reg_o")
328 self.spr_out = Data(SPR, "spr_o")
329 self.fast_out = Data(3, "fast_o")
330
331 def elaborate(self, platform):
332 m = Module()
333 comb = m.d.comb
334 m.submodules.sprmap = sprmap = SPRMap()
335 op = self.dec.op
336 reg = self.reg_out
337
338 # select Register out field
339 with m.Switch(self.sel_in):
340 with m.Case(OutSel.RT):
341 comb += reg.data.eq(self.dec.RT)
342 comb += reg.ok.eq(1)
343 with m.Case(OutSel.RA):
344 comb += reg.data.eq(self.dec.RA)
345 comb += reg.ok.eq(1)
346 with m.Case(OutSel.SPR):
347 spr = Signal(10, reset_less=True)
348 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
349 # MFSPR move to SPRs - needs mapping
350 with m.If(op.internal_op == MicrOp.OP_MTSPR):
351 comb += sprmap.spr_i.eq(spr)
352 comb += self.spr_out.eq(sprmap.spr_o)
353 comb += self.fast_out.eq(sprmap.fast_o)
354
355 # determine Fast Reg
356 with m.Switch(op.internal_op):
357
358 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
359 with m.Case(MicrOp.OP_BC, MicrOp.OP_BCREG):
360 with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
361 # constant: CTR
362 comb += self.fast_out.data.eq(FastRegs.CTR)
363 comb += self.fast_out.ok.eq(1)
364
365 # RFID 1st spr (fast)
366 with m.Case(MicrOp.OP_RFID):
367 comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
368 comb += self.fast_out.ok.eq(1)
369
370 return m
371
372
373 class DecodeOut2(Elaboratable):
374 """DecodeOut2 from instruction
375
376 decodes output registers (2nd one). note that RA is *implicit* below,
377 which now causes problems with SVP64
378
379 TODO: SVP64 is a little more complex, here. svp64 allows extending
380 by one more destination by having one more EXTRA field. RA-as-src
381 is not the same as RA-as-dest. limited in that it's the same first
382 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
383 for operations that have src-as-dest: mostly this is LD/ST-with-update
384 but there are others.
385 """
386
387 def __init__(self, dec):
388 self.dec = dec
389 self.sel_in = Signal(OutSel, reset_less=True)
390 self.lk = Signal(reset_less=True)
391 self.insn_in = Signal(32, reset_less=True)
392 self.reg_out = Data(5, "reg_o2")
393 self.fast_out = Data(3, "fast_o2")
394
395 def elaborate(self, platform):
396 m = Module()
397 comb = m.d.comb
398 op = self.dec.op
399 #m.submodules.svdec = svdec = SVP64RegExtra()
400
401 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
402 #reg = Signal(5, reset_less=True)
403
404 if hasattr(self.dec.op, "upd"):
405 # update mode LD/ST uses read-reg A also as an output
406 with m.If(self.dec.op.upd == LDSTMode.update):
407 comb += self.reg_out.data.eq(self.dec.RA)
408 comb += self.reg_out.ok.eq(1)
409
410 # B, BC or BCREG: potential implicit register (LR) output
411 # these give bl, bcl, bclrl, etc.
412 with m.Switch(op.internal_op):
413
414 # BC* implicit register (LR)
415 with m.Case(MicrOp.OP_BC, MicrOp.OP_B, MicrOp.OP_BCREG):
416 with m.If(self.lk): # "link" mode
417 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
418 comb += self.fast_out.ok.eq(1)
419
420 # RFID 2nd spr (fast)
421 with m.Case(MicrOp.OP_RFID):
422 comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
423 comb += self.fast_out.ok.eq(1)
424
425 return m
426
427
428 class DecodeRC(Elaboratable):
429 """DecodeRc from instruction
430
431 decodes Record bit Rc
432 """
433
434 def __init__(self, dec):
435 self.dec = dec
436 self.sel_in = Signal(RC, reset_less=True)
437 self.insn_in = Signal(32, reset_less=True)
438 self.rc_out = Data(1, "rc")
439
440 def elaborate(self, platform):
441 m = Module()
442 comb = m.d.comb
443
444 # select Record bit out field
445 with m.Switch(self.sel_in):
446 with m.Case(RC.RC):
447 comb += self.rc_out.data.eq(self.dec.Rc)
448 comb += self.rc_out.ok.eq(1)
449 with m.Case(RC.ONE):
450 comb += self.rc_out.data.eq(1)
451 comb += self.rc_out.ok.eq(1)
452 with m.Case(RC.NONE):
453 comb += self.rc_out.data.eq(0)
454 comb += self.rc_out.ok.eq(1)
455
456 return m
457
458
459 class DecodeOE(Elaboratable):
460 """DecodeOE from instruction
461
462 decodes OE field: uses RC decode detection which might not be good
463
464 -- For now, use "rc" in the decode table to decide whether oe exists.
465 -- This is not entirely correct architecturally: For mulhd and
466 -- mulhdu, the OE field is reserved. It remains to be seen what an
467 -- actual POWER9 does if we set it on those instructions, for now we
468 -- test that further down when assigning to the multiplier oe input.
469 """
470
471 def __init__(self, dec):
472 self.dec = dec
473 self.sel_in = Signal(RC, reset_less=True)
474 self.insn_in = Signal(32, reset_less=True)
475 self.oe_out = Data(1, "oe")
476
477 def elaborate(self, platform):
478 m = Module()
479 comb = m.d.comb
480 op = self.dec.op
481
482 with m.Switch(op.internal_op):
483
484 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
485 # also rotate
486 # XXX ARGH! ignoring OE causes incompatibility with microwatt
487 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
488 with m.Case(MicrOp.OP_MUL_H64, MicrOp.OP_MUL_H32,
489 MicrOp.OP_EXTS, MicrOp.OP_CNTZ,
490 MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC,
491 MicrOp.OP_LOAD, MicrOp.OP_STORE,
492 MicrOp.OP_RLCL, MicrOp.OP_RLCR,
493 MicrOp.OP_EXTSWSLI):
494 pass
495
496 # all other ops decode OE field
497 with m.Default():
498 # select OE bit out field
499 with m.Switch(self.sel_in):
500 with m.Case(RC.RC):
501 comb += self.oe_out.data.eq(self.dec.OE)
502 comb += self.oe_out.ok.eq(1)
503
504 return m
505
506
507 class DecodeCRIn(Elaboratable):
508 """Decodes input CR from instruction
509
510 CR indices - insn fields - (not the data *in* the CR) require only 3
511 bits because they refer to CR0-CR7
512 """
513
514 def __init__(self, dec):
515 self.dec = dec
516 self.sel_in = Signal(CRInSel, reset_less=True)
517 self.insn_in = Signal(32, reset_less=True)
518 self.cr_bitfield = Data(3, "cr_bitfield")
519 self.cr_bitfield_b = Data(3, "cr_bitfield_b")
520 self.cr_bitfield_o = Data(3, "cr_bitfield_o")
521 self.whole_reg = Data(8, "cr_fxm")
522 self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
523
524 def elaborate(self, platform):
525 m = Module()
526 comb = m.d.comb
527 op = self.dec.op
528 m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
529 reverse_o=True)
530
531 # zero-initialisation
532 comb += self.cr_bitfield.ok.eq(0)
533 comb += self.cr_bitfield_b.ok.eq(0)
534 comb += self.cr_bitfield_o.ok.eq(0)
535 comb += self.whole_reg.ok.eq(0)
536 comb += self.sv_override.eq(0)
537
538 # select the relevant CR bitfields
539 with m.Switch(self.sel_in):
540 with m.Case(CRInSel.NONE):
541 pass # No bitfield activated
542 with m.Case(CRInSel.CR0):
543 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
544 comb += self.cr_bitfield.ok.eq(1)
545 comb += self.sv_override.eq(1)
546 with m.Case(CRInSel.CR1):
547 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
548 comb += self.cr_bitfield.ok.eq(1)
549 comb += self.sv_override.eq(2)
550 with m.Case(CRInSel.BI):
551 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
552 comb += self.cr_bitfield.ok.eq(1)
553 with m.Case(CRInSel.BFA):
554 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
555 comb += self.cr_bitfield.ok.eq(1)
556 with m.Case(CRInSel.BA_BB):
557 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
558 comb += self.cr_bitfield.ok.eq(1)
559 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
560 comb += self.cr_bitfield_b.ok.eq(1)
561 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
562 comb += self.cr_bitfield_o.ok.eq(1)
563 with m.Case(CRInSel.BC):
564 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
565 comb += self.cr_bitfield.ok.eq(1)
566 with m.Case(CRInSel.WHOLE_REG):
567 comb += self.whole_reg.ok.eq(1)
568 move_one = Signal(reset_less=True)
569 comb += move_one.eq(self.insn_in[20]) # MSB0 bit 11
570 with m.If((op.internal_op == MicrOp.OP_MFCR) & move_one):
571 # must one-hot the FXM field
572 comb += ppick.i.eq(self.dec.FXM)
573 comb += self.whole_reg.data.eq(ppick.o)
574 with m.Else():
575 # otherwise use all of it
576 comb += self.whole_reg.data.eq(0xff)
577
578 return m
579
580
581 class DecodeCROut(Elaboratable):
582 """Decodes input CR from instruction
583
584 CR indices - insn fields - (not the data *in* the CR) require only 3
585 bits because they refer to CR0-CR7
586 """
587
588 def __init__(self, dec):
589 self.dec = dec
590 self.rc_in = Signal(reset_less=True)
591 self.sel_in = Signal(CROutSel, reset_less=True)
592 self.insn_in = Signal(32, reset_less=True)
593 self.cr_bitfield = Data(3, "cr_bitfield")
594 self.whole_reg = Data(8, "cr_fxm")
595 self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
596
597 def elaborate(self, platform):
598 m = Module()
599 comb = m.d.comb
600 op = self.dec.op
601 m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
602 reverse_o=True)
603
604 comb += self.cr_bitfield.ok.eq(0)
605 comb += self.whole_reg.ok.eq(0)
606 comb += self.sv_override.eq(0)
607
608 # please note these MUST match (setting of cr_bitfield.ok) exactly
609 # with write_cr0 below in PowerDecoder2. the reason it's separated
610 # is to avoid having duplicate copies of DecodeCROut in multiple
611 # PowerDecoderSubsets. register decoding should be a one-off in
612 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
613
614 with m.Switch(self.sel_in):
615 with m.Case(CROutSel.NONE):
616 pass # No bitfield activated
617 with m.Case(CROutSel.CR0):
618 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
619 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
620 comb += self.sv_override.eq(1)
621 with m.Case(CROutSel.CR1):
622 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
623 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
624 comb += self.sv_override.eq(2)
625 with m.Case(CROutSel.BF):
626 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
627 comb += self.cr_bitfield.ok.eq(1)
628 with m.Case(CROutSel.BT):
629 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
630 comb += self.cr_bitfield.ok.eq(1)
631 with m.Case(CROutSel.WHOLE_REG):
632 comb += self.whole_reg.ok.eq(1)
633 move_one = Signal(reset_less=True)
634 comb += move_one.eq(self.insn_in[20])
635 with m.If((op.internal_op == MicrOp.OP_MTCRF)):
636 with m.If(move_one):
637 # must one-hot the FXM field
638 comb += ppick.i.eq(self.dec.FXM)
639 with m.If(ppick.en_o):
640 comb += self.whole_reg.data.eq(ppick.o)
641 with m.Else():
642 comb += self.whole_reg.data.eq(0b00000001) # CR7
643 with m.Else():
644 comb += self.whole_reg.data.eq(self.dec.FXM)
645 with m.Else():
646 # otherwise use all of it
647 comb += self.whole_reg.data.eq(0xff)
648
649 return m
650
651 # dictionary of Input Record field names that, if they exist,
652 # will need a corresponding CSV Decoder file column (actually, PowerOp)
653 # to be decoded (this includes the single bit names)
654 record_names = {'insn_type': 'internal_op',
655 'fn_unit': 'function_unit',
656 'rc': 'rc_sel',
657 'oe': 'rc_sel',
658 'zero_a': 'in1_sel',
659 'imm_data': 'in2_sel',
660 'invert_in': 'inv_a',
661 'invert_out': 'inv_out',
662 'rc': 'cr_out',
663 'oe': 'cr_in',
664 'output_carry': 'cry_out',
665 'input_carry': 'cry_in',
666 'is_32bit': 'is_32b',
667 'is_signed': 'sgn',
668 'lk': 'lk',
669 'data_len': 'ldst_len',
670 'byte_reverse': 'br',
671 'sign_extend': 'sgn_ext',
672 'ldst_mode': 'upd',
673 }
674
675
676 class PowerDecodeSubset(Elaboratable):
677 """PowerDecodeSubset: dynamic subset decoder
678
679 only fields actually requested are copied over. hence, "subset" (duh).
680 """
681 def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None):
682
683 self.sv_rm = SVP64Rec(name="dec_svp64") # SVP64 RM field
684 self.final = final
685 self.opkls = opkls
686 self.fn_name = fn_name
687 if opkls is None:
688 opkls = Decode2ToOperand
689 self.do = opkls(fn_name)
690 col_subset = self.get_col_subset(self.do)
691
692 # only needed for "main" PowerDecode2
693 if not self.final:
694 self.e = Decode2ToExecute1Type(name=self.fn_name, do=self.do)
695
696 # create decoder if one not already given
697 if dec is None:
698 dec = create_pdecode(name=fn_name, col_subset=col_subset,
699 row_subset=self.rowsubsetfn)
700 self.dec = dec
701
702 # state information needed by the Decoder
703 if state is None:
704 state = CoreState("dec2")
705 self.state = state
706
707 def get_col_subset(self, do):
708 subset = { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
709 for k, v in record_names.items():
710 if hasattr(do, k):
711 subset.add(v)
712 print ("get_col_subset", self.fn_name, do.fields, subset)
713 return subset
714
715 def rowsubsetfn(self, opcode, row):
716 return row['unit'] == self.fn_name
717
718 def ports(self):
719 return self.dec.ports() + self.e.ports() + self.sv_rm.ports()
720
721 def needs_field(self, field, op_field):
722 if self.final:
723 do = self.do
724 else:
725 do = self.e_tmp.do
726 return hasattr(do, field) and self.op_get(op_field) is not None
727
728 def do_copy(self, field, val, final=False):
729 if final or self.final:
730 do = self.do
731 else:
732 do = self.e_tmp.do
733 if hasattr(do, field) and val is not None:
734 return getattr(do, field).eq(val)
735 return []
736
737 def op_get(self, op_field):
738 return getattr(self.dec.op, op_field, None)
739
740 def elaborate(self, platform):
741 m = Module()
742 comb = m.d.comb
743 state = self.state
744 op, do = self.dec.op, self.do
745 msr, cia = state.msr, state.pc
746 # fill in for a normal instruction (not an exception)
747 # copy over if non-exception, non-privileged etc. is detected
748 if not self.final:
749 if self.fn_name is None:
750 name = "tmp"
751 else:
752 name = self.fn_name + "tmp"
753 self.e_tmp = Decode2ToExecute1Type(name=name, opkls=self.opkls)
754
755 # set up submodule decoders
756 m.submodules.dec = self.dec
757 m.submodules.dec_rc = self.dec_rc = dec_rc = DecodeRC(self.dec)
758 m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
759
760 # copy instruction through...
761 for i in [do.insn, dec_rc.insn_in, dec_oe.insn_in, ]:
762 comb += i.eq(self.dec.opcode_in)
763
764 # ...and subdecoders' input fields
765 comb += dec_rc.sel_in.eq(op.rc_sel)
766 comb += dec_oe.sel_in.eq(op.rc_sel) # XXX should be OE sel
767
768 # copy "state" over
769 comb += self.do_copy("msr", msr)
770 comb += self.do_copy("cia", cia)
771
772 # set up instruction type
773 # no op: defaults to OP_ILLEGAL
774 if self.fn_name=="MMU":
775 # mmu is special case: needs SPR opcode as well
776 mmu0 = self.mmu0_spr_dec
777 with m.If(((mmu0.dec.op.internal_op == MicrOp.OP_MTSPR) |
778 (mmu0.dec.op.internal_op == MicrOp.OP_MFSPR))):
779 comb += self.do_copy("insn_type", mmu0.op_get("internal_op"))
780 with m.Else():
781 comb += self.do_copy("insn_type", self.op_get("internal_op"))
782 else:
783 comb += self.do_copy("insn_type", self.op_get("internal_op"))
784
785 # function unit for decoded instruction: requires minor redirect
786 # for SPR set/get
787 fn = self.op_get("function_unit")
788 spr = Signal(10, reset_less=True)
789 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
790
791 # Microwatt doesn't implement the partition table
792 # instead has PRTBL(SVSRR0) register (SPR) to point to process table
793 with m.If(((self.dec.op.internal_op == MicrOp.OP_MTSPR) |
794 (self.dec.op.internal_op == MicrOp.OP_MFSPR)) &
795 ((spr == SPR.DSISR.value) | (spr == SPR.DAR.value) |
796 (spr==SPR.SVSRR0.value) | (spr==SPR.PIDR.value))):
797 comb += self.do_copy("fn_unit", Function.MMU)
798 with m.Else():
799 comb += self.do_copy("fn_unit",fn)
800
801 # immediates
802 if self.needs_field("zero_a", "in1_sel"):
803 m.submodules.dec_ai = dec_ai = DecodeAImm(self.dec)
804 comb += dec_ai.sel_in.eq(op.in1_sel)
805 comb += self.do_copy("zero_a", dec_ai.immz_out) # RA==0 detected
806 if self.needs_field("imm_data", "in2_sel"):
807 m.submodules.dec_bi = dec_bi = DecodeBImm(self.dec)
808 comb += dec_bi.sel_in.eq(op.in2_sel)
809 comb += self.do_copy("imm_data", dec_bi.imm_out) # imm in RB
810
811 # rc and oe out
812 comb += self.do_copy("rc", dec_rc.rc_out)
813 comb += self.do_copy("oe", dec_oe.oe_out)
814
815 # CR in/out - note: these MUST match with what happens in
816 # DecodeCROut!
817 rc_out = self.dec_rc.rc_out.data
818 with m.Switch(op.cr_out):
819 with m.Case(CROutSel.CR0, CROutSel.CR1):
820 comb += self.do_copy("write_cr0", rc_out) # only when RC=1
821 with m.Case(CROutSel.BF, CROutSel.BT):
822 comb += self.do_copy("write_cr0", 1)
823
824 comb += self.do_copy("input_cr", self.op_get("cr_in")) # CR in
825 comb += self.do_copy("output_cr", self.op_get("cr_out")) # CR out
826
827 # decoded/selected instruction flags
828 comb += self.do_copy("data_len", self.op_get("ldst_len"))
829 comb += self.do_copy("invert_in", self.op_get("inv_a"))
830 comb += self.do_copy("invert_out", self.op_get("inv_out"))
831 comb += self.do_copy("input_carry", self.op_get("cry_in"))
832 comb += self.do_copy("output_carry", self.op_get("cry_out"))
833 comb += self.do_copy("is_32bit", self.op_get("is_32b"))
834 comb += self.do_copy("is_signed", self.op_get("sgn"))
835 lk = self.op_get("lk")
836 if lk is not None:
837 with m.If(lk):
838 comb += self.do_copy("lk", self.dec.LK) # XXX TODO: accessor
839
840 comb += self.do_copy("byte_reverse", self.op_get("br"))
841 comb += self.do_copy("sign_extend", self.op_get("sgn_ext"))
842 comb += self.do_copy("ldst_mode", self.op_get("upd")) # LD/ST mode
843
844 return m
845
846
847 class PowerDecode2(PowerDecodeSubset):
848 """PowerDecode2: the main instruction decoder.
849
850 whilst PowerDecode is responsible for decoding the actual opcode, this
851 module encapsulates further specialist, sparse information and
852 expansion of fields that is inconvenient to have in the CSV files.
853 for example: the encoding of the immediates, which are detected
854 and expanded out to their full value from an annotated (enum)
855 representation.
856
857 implicit register usage is also set up, here. for example: OP_BC
858 requires implicitly reading CTR, OP_RFID requires implicitly writing
859 to SRR1 and so on.
860
861 in addition, PowerDecoder2 is responsible for detecting whether
862 instructions are illegal (or privileged) or not, and instead of
863 just leaving at that, *replacing* the instruction to execute with
864 a suitable alternative (trap).
865
866 LDSTExceptions are done the cycle _after_ they're detected (after
867 they come out of LDSTCompUnit). basically despite the instruction
868 being decoded, the results of the decode are completely ignored
869 and "exception.happened" used to set the "actual" instruction to
870 "OP_TRAP". the LDSTException data structure gets filled in,
871 in the CompTrapOpSubset and that's what it fills in SRR.
872
873 to make this work, TestIssuer must notice "exception.happened"
874 after the (failed) LD/ST and copies the LDSTException info from
875 the output, into here (PowerDecoder2). without incrementing PC.
876 """
877
878 def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None):
879 super().__init__(dec, opkls, fn_name, final, state)
880 self.exc = LDSTException("dec2_exc")
881
882 self.cr_out_isvec = Signal(1, name="cr_out_isvec")
883 self.cr_in_isvec = Signal(1, name="cr_in_isvec")
884 self.cr_in_b_isvec = Signal(1, name="cr_in_b_isvec")
885 self.cr_in_o_isvec = Signal(1, name="cr_in_o_isvec")
886 self.in1_isvec = Signal(1, name="reg_a_isvec")
887 self.in2_isvec = Signal(1, name="reg_b_isvec")
888 self.in3_isvec = Signal(1, name="reg_c_isvec")
889 self.o_isvec = Signal(1, name="reg_o_isvec")
890 self.o2_isvec = Signal(1, name="reg_o2_isvec")
891 self.no_in_vec = Signal(1, name="no_in_vec") # no inputs are vectors
892 self.no_out_vec = Signal(1, name="no_out_vec") # no outputs are vectors
893
894 def get_col_subset(self, opkls):
895 subset = super().get_col_subset(opkls)
896 subset.add("asmcode")
897 subset.add("in1_sel")
898 subset.add("in2_sel")
899 subset.add("in3_sel")
900 subset.add("out_sel")
901 subset.add("sv_in1")
902 subset.add("sv_in2")
903 subset.add("sv_in3")
904 subset.add("sv_out")
905 subset.add("sv_cr_in")
906 subset.add("sv_cr_out")
907 subset.add("SV_Etype")
908 subset.add("SV_Ptype")
909 subset.add("lk")
910 subset.add("internal_op")
911 subset.add("form")
912 return subset
913
914 def elaborate(self, platform):
915 m = super().elaborate(platform)
916 comb = m.d.comb
917 state = self.state
918 e_out, op, do_out = self.e, self.dec.op, self.e.do
919 dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
920 rc_out = self.dec_rc.rc_out.data
921 e = self.e_tmp
922 do = e.do
923
924 # fill in for a normal instruction (not an exception)
925 # copy over if non-exception, non-privileged etc. is detected
926
927 # set up submodule decoders
928 m.submodules.dec_a = dec_a = DecodeA(self.dec)
929 m.submodules.dec_b = dec_b = DecodeB(self.dec)
930 m.submodules.dec_c = dec_c = DecodeC(self.dec)
931 m.submodules.dec_o = dec_o = DecodeOut(self.dec)
932 m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
933 m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec)
934 m.submodules.dec_cr_out = self.dec_cr_out = DecodeCROut(self.dec)
935
936 # and SVP64 Extra decoders
937 m.submodules.crout_svdec = crout_svdec = SVP64CRExtra()
938 m.submodules.crin_svdec = crin_svdec = SVP64CRExtra()
939 m.submodules.crin_svdec_b = crin_svdec_b = SVP64CRExtra()
940 m.submodules.crin_svdec_o = crin_svdec_o = SVP64CRExtra()
941 m.submodules.in1_svdec = in1_svdec = SVP64RegExtra()
942 m.submodules.in2_svdec = in2_svdec = SVP64RegExtra()
943 m.submodules.in3_svdec = in3_svdec = SVP64RegExtra()
944 m.submodules.o_svdec = o_svdec = SVP64RegExtra()
945 m.submodules.o2_svdec = o2_svdec = SVP64RegExtra()
946
947 # debug access to crout_svdec (used in get_pdecode_cr_out)
948 self.crout_svdec = crout_svdec
949
950 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
951 reg = Signal(5, reset_less=True)
952
953 # copy instruction through...
954 for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
955 self.dec_cr_in.insn_in, self.dec_cr_out.insn_in,
956 dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]:
957 comb += i.eq(self.dec.opcode_in)
958
959 # CR setup
960 comb += self.dec_cr_in.sel_in.eq(op.cr_in)
961 comb += self.dec_cr_out.sel_in.eq(op.cr_out)
962 comb += self.dec_cr_out.rc_in.eq(rc_out)
963
964 # CR register info
965 comb += self.do_copy("read_cr_whole", self.dec_cr_in.whole_reg)
966 comb += self.do_copy("write_cr_whole", self.dec_cr_out.whole_reg)
967
968 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
969 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
970 # which in turn were auto-generated by sv_analysis.py
971 extra = self.sv_rm.extra # SVP64 extra bits 10:18
972
973 #######
974 # CR out
975 comb += crout_svdec.idx.eq(op.sv_cr_out) # SVP64 CR out
976 comb += self.cr_out_isvec.eq(crout_svdec.isvec)
977
978 #######
979 # CR in - index selection slightly different due to shared CR field sigh
980 cr_a_idx = Signal(SVEXTRA)
981 cr_b_idx = Signal(SVEXTRA)
982
983 # these change slightly, when decoding BA/BB. really should have
984 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
985 comb += cr_a_idx.eq(op.sv_cr_in)
986 comb += cr_b_idx.eq(SVEXTRA.NONE)
987 with m.If(op.sv_cr_in == SVEXTRA.Idx_1_2.value):
988 comb += cr_a_idx.eq(SVEXTRA.Idx1)
989 comb += cr_b_idx.eq(SVEXTRA.Idx2)
990
991 comb += self.cr_in_isvec.eq(crin_svdec.isvec)
992 comb += self.cr_in_b_isvec.eq(crin_svdec_b.isvec)
993 comb += self.cr_in_o_isvec.eq(crin_svdec_o.isvec)
994
995 # indices are slightly different, BA/BB mess sorted above
996 comb += crin_svdec.idx.eq(cr_a_idx) # SVP64 CR in A
997 comb += crin_svdec_b.idx.eq(cr_b_idx) # SVP64 CR in B
998 comb += crin_svdec_o.idx.eq(op.sv_cr_out) # SVP64 CR out
999
1000 # ...and subdecoders' input fields
1001 comb += dec_a.sel_in.eq(op.in1_sel)
1002 comb += dec_b.sel_in.eq(op.in2_sel)
1003 comb += dec_c.sel_in.eq(op.in3_sel)
1004 comb += dec_o.sel_in.eq(op.out_sel)
1005 comb += dec_o2.sel_in.eq(op.out_sel)
1006 if hasattr(do, "lk"):
1007 comb += dec_o2.lk.eq(do.lk)
1008
1009 # get SVSTATE srcstep (TODO: elwidth, dststep etc.) needed below
1010 srcstep = Signal.like(self.state.svstate.srcstep)
1011 comb += srcstep.eq(self.state.svstate.srcstep)
1012
1013 # registers a, b, c and out and out2 (LD/ST EA)
1014 for to_reg, fromreg, svdec in (
1015 (e.read_reg1, dec_a.reg_out, in1_svdec),
1016 (e.read_reg2, dec_b.reg_out, in2_svdec),
1017 (e.read_reg3, dec_c.reg_out, in3_svdec),
1018 (e.write_reg, dec_o.reg_out, o_svdec),
1019 (e.write_ea, dec_o2.reg_out, o2_svdec)):
1020 comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
1021 comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
1022 comb += svdec.reg_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1023 comb += to_reg.ok.eq(fromreg.ok)
1024 # detect if Vectorised: add srcstep if yes. TODO: a LOT.
1025 # this trick only holds when elwidth=default and in single-pred
1026 with m.If(svdec.isvec):
1027 comb += to_reg.data.eq(srcstep+svdec.reg_out) # 7-bit output
1028 with m.Else():
1029 comb += to_reg.data.eq(svdec.reg_out) # 7-bit output
1030
1031 comb += in1_svdec.idx.eq(op.sv_in1) # SVP64 reg #1 (matches in1_sel)
1032 comb += in2_svdec.idx.eq(op.sv_in2) # SVP64 reg #2 (matches in2_sel)
1033 comb += in3_svdec.idx.eq(op.sv_in3) # SVP64 reg #3 (matches in3_sel)
1034 comb += o_svdec.idx.eq(op.sv_out) # SVP64 output (matches out_sel)
1035 # XXX TODO - work out where this should come from. the problem is
1036 # that LD-with-update is implied (computed from "is instruction in
1037 # "update mode" rather than specified cleanly as its own CSV column
1038 #comb += o2_svdec.idx.eq(op.sv_out) # SVP64 output (implicit)
1039
1040 # output reg-is-vectorised (and when no input or output is vectorised)
1041 comb += self.in1_isvec.eq(in1_svdec.isvec)
1042 comb += self.in2_isvec.eq(in2_svdec.isvec)
1043 comb += self.in3_isvec.eq(in3_svdec.isvec)
1044 comb += self.o_isvec.eq(o_svdec.isvec)
1045 comb += self.o2_isvec.eq(o2_svdec.isvec)
1046 # TODO add SPRs here. must be True when *all* are scalar
1047 l = map(lambda svdec: svdec.isvec, [in1_svdec, in2_svdec, in3_svdec,
1048 crin_svdec, crin_svdec_b, crin_svdec_o])
1049 comb += self.no_in_vec.eq(~Cat(*l).bool()) # all input scalar
1050 l = map(lambda svdec: svdec.isvec, [o2_svdec, o_svdec, crout_svdec])
1051 comb += self.no_out_vec.eq(~Cat(*l).bool()) # all output scalar
1052
1053 # SPRs out
1054 comb += e.read_spr1.eq(dec_a.spr_out)
1055 comb += e.write_spr.eq(dec_o.spr_out)
1056
1057 # Fast regs out
1058 comb += e.read_fast1.eq(dec_a.fast_out)
1059 comb += e.read_fast2.eq(dec_b.fast_out)
1060 comb += e.write_fast1.eq(dec_o.fast_out)
1061 comb += e.write_fast2.eq(dec_o2.fast_out)
1062
1063 # condition registers (CR)
1064 for to_reg, cr, name, svdec in (
1065 (e.read_cr1, self.dec_cr_in, "cr_bitfield", crin_svdec),
1066 (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", crin_svdec_b),
1067 (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", crin_svdec_o),
1068 (e.write_cr, self.dec_cr_out, "cr_bitfield", crout_svdec)):
1069 fromreg = getattr(cr, name)
1070 comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM
1071 comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn
1072 comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1073 with m.If(svdec.isvec):
1074 # check if this is CR0 or CR1: treated differently
1075 # (does not "listen" to EXTRA2/3 spec for a start)
1076 # also: the CRs start from completely different locations
1077 with m.If(cr.sv_override == 1): # CR0
1078 offs = SVP64CROffs.CR0
1079 comb += to_reg.data.eq(srcstep+offs)
1080 with m.Elif(cr.sv_override == 2): # CR1
1081 offs = SVP64CROffs.CR1
1082 comb += to_reg.data.eq(srcstep+1)
1083 with m.Else():
1084 comb += to_reg.data.eq(srcstep+svdec.cr_out) # 7-bit output
1085 with m.Else():
1086 comb += to_reg.data.eq(svdec.cr_out) # 7-bit output
1087 comb += to_reg.ok.eq(fromreg.ok)
1088
1089 # sigh this is exactly the sort of thing for which the
1090 # decoder is designed to not need. MTSPR, MFSPR and others need
1091 # access to the XER bits. however setting e.oe is not appropriate
1092 with m.If(op.internal_op == MicrOp.OP_MFSPR):
1093 comb += e.xer_in.eq(0b111) # SO, CA, OV
1094 with m.If(op.internal_op == MicrOp.OP_CMP):
1095 comb += e.xer_in.eq(1<<XERRegs.SO) # SO
1096 with m.If(op.internal_op == MicrOp.OP_MTSPR):
1097 comb += e.xer_out.eq(1)
1098
1099 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1100 with m.If(op.internal_op == MicrOp.OP_TRAP):
1101 # *DO NOT* call self.trap here. that would reset absolutely
1102 # everything including destroying read of RA and RB.
1103 comb += self.do_copy("trapaddr", 0x70) # strip first nibble
1104
1105 ####################
1106 # ok so the instruction's been decoded, blah blah, however
1107 # now we need to determine if it's actually going to go ahead...
1108 # *or* if in fact it's a privileged operation, whether there's
1109 # an external interrupt, etc. etc. this is a simple priority
1110 # if-elif-elif sequence. decrement takes highest priority,
1111 # EINT next highest, privileged operation third.
1112
1113 # check if instruction is privileged
1114 is_priv_insn = instr_is_priv(m, op.internal_op, e.do.insn)
1115
1116 # different IRQ conditions
1117 ext_irq_ok = Signal()
1118 dec_irq_ok = Signal()
1119 priv_ok = Signal()
1120 illeg_ok = Signal()
1121 exc = self.exc
1122
1123 comb += ext_irq_ok.eq(ext_irq & msr[MSR.EE]) # v3.0B p944 (MSR.EE)
1124 comb += dec_irq_ok.eq(dec_spr[63] & msr[MSR.EE]) # 6.5.11 p1076
1125 comb += priv_ok.eq(is_priv_insn & msr[MSR.PR])
1126 comb += illeg_ok.eq(op.internal_op == MicrOp.OP_ILLEGAL)
1127
1128 # LD/ST exceptions. TestIssuer copies the exception info at us
1129 # after a failed LD/ST.
1130 with m.If(exc.happened):
1131 with m.If(exc.alignment):
1132 self.trap(m, TT.PRIV, 0x600)
1133 with m.Elif(exc.instr_fault):
1134 with m.If(exc.segment_fault):
1135 self.trap(m, TT.PRIV, 0x480)
1136 with m.Else():
1137 # pass exception info to trap to create SRR1
1138 self.trap(m, TT.MEMEXC, 0x400, exc)
1139 with m.Else():
1140 with m.If(exc.segment_fault):
1141 self.trap(m, TT.PRIV, 0x380)
1142 with m.Else():
1143 self.trap(m, TT.PRIV, 0x300)
1144
1145 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1146 with m.Elif(dec_irq_ok):
1147 self.trap(m, TT.DEC, 0x900) # v3.0B 6.5 p1065
1148
1149 # external interrupt? only if MSR.EE set
1150 with m.Elif(ext_irq_ok):
1151 self.trap(m, TT.EINT, 0x500)
1152
1153 # privileged instruction trap
1154 with m.Elif(priv_ok):
1155 self.trap(m, TT.PRIV, 0x700)
1156
1157 # illegal instruction must redirect to trap. this is done by
1158 # *overwriting* the decoded instruction and starting again.
1159 # (note: the same goes for interrupts and for privileged operations,
1160 # just with different trapaddr and traptype)
1161 with m.Elif(illeg_ok):
1162 # illegal instruction trap
1163 self.trap(m, TT.ILLEG, 0x700)
1164
1165 # no exception, just copy things to the output
1166 with m.Else():
1167 comb += e_out.eq(e)
1168
1169 ####################
1170 # follow-up after trap/irq to set up SRR0/1
1171
1172 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1173 # Note: OP_SC could actually be modified to just be a trap
1174 with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
1175 (do_out.insn_type == MicrOp.OP_SC)):
1176 # TRAP write fast1 = SRR0
1177 comb += e_out.write_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
1178 comb += e_out.write_fast1.ok.eq(1)
1179 # TRAP write fast2 = SRR1
1180 comb += e_out.write_fast2.data.eq(FastRegs.SRR1) # constant: SRR1
1181 comb += e_out.write_fast2.ok.eq(1)
1182
1183 # RFID: needs to read SRR0/1
1184 with m.If(do_out.insn_type == MicrOp.OP_RFID):
1185 # TRAP read fast1 = SRR0
1186 comb += e_out.read_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
1187 comb += e_out.read_fast1.ok.eq(1)
1188 # TRAP read fast2 = SRR1
1189 comb += e_out.read_fast2.data.eq(FastRegs.SRR1) # constant: SRR1
1190 comb += e_out.read_fast2.ok.eq(1)
1191
1192 # annoying simulator bug
1193 if hasattr(e_out, "asmcode") and hasattr(self.dec.op, "asmcode"):
1194 comb += e_out.asmcode.eq(self.dec.op.asmcode)
1195
1196 return m
1197
1198 def trap(self, m, traptype, trapaddr, exc=None):
1199 """trap: this basically "rewrites" the decoded instruction as a trap
1200 """
1201 comb = m.d.comb
1202 op, e = self.dec.op, self.e
1203 comb += e.eq(0) # reset eeeeeverything
1204
1205 # start again
1206 comb += self.do_copy("insn", self.dec.opcode_in, True)
1207 comb += self.do_copy("insn_type", MicrOp.OP_TRAP, True)
1208 comb += self.do_copy("fn_unit", Function.TRAP, True)
1209 comb += self.do_copy("trapaddr", trapaddr >> 4, True) # bottom 4 bits
1210 comb += self.do_copy("traptype", traptype, True) # request type
1211 comb += self.do_copy("ldst_exc", exc, True) # request type
1212 comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state"
1213 comb += self.do_copy("cia", self.state.pc, True) # copy of PC "state"
1214
1215
1216
1217 def get_rdflags(e, cu):
1218 rdl = []
1219 for idx in range(cu.n_src):
1220 regfile, regname, _ = cu.get_in_spec(idx)
1221 rdflag, read = regspec_decode_read(e, regfile, regname)
1222 rdl.append(rdflag)
1223 print("rdflags", rdl)
1224 return Cat(*rdl)
1225
1226
1227 if __name__ == '__main__':
1228 pdecode = create_pdecode()
1229 dec2 = PowerDecode2(pdecode)
1230 vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
1231 with open("dec2.il", "w") as f:
1232 f.write(vl)