src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
   7 from nmigen.cli import rtlil
   8
   9 from nmutil.iocontrol import RecordObject
  10 from nmutil.extend import exts
  11
  12 from soc.decoder.power_regspec_map import regspec_decode_read
  13 from soc.decoder.power_regspec_map import regspec_decode_write
  14 from soc.decoder.power_decoder import create_pdecode
  15 from soc.decoder.power_enums import (InternalOp, CryIn, Function,
  16                                      CRInSel, CROutSel,
  17                                      LdstLen, In1Sel, In2Sel, In3Sel,
  18                                      OutSel, SPR, RC)
  19 from soc.decoder.decode2execute1 import Decode2ToExecute1Type, Data
  20
  21 from soc.regfile.regfiles import FastRegs
  22
  23 # see traptype (and trap main_stage.py)
  24
  25 TT_FP = 1<<0
  26 TT_PRIV = 1<<1
  27 TT_TRAP = 1<<2
  28 TT_ADDR = 1<<3
  29
  30 def decode_spr_num(spr):
  31     return Cat(spr[5:10], spr[0:5])
  32
  33
  34 def instr_is_priv(m, op, insn):
  35     """determines if the instruction is privileged or not
  36     """
  37     comb = m.d.comb
  38     Signal = is_priv_insn(reset_less=True)
  39     with m.Switch(op):
  40         with m.Case(InternalOp.OP_ATTN)  : comb += is_priv_insn.eq(1)
  41         with m.Case(InternalOp.OP_MFMSR) : comb += is_priv_insn.eq(1)
  42         with m.Case(InternalOp.OP_MTMSRD): comb += is_priv_insn.eq(1)
  43         with m.Case(InternalOp.OP_RFID)  : comb += is_priv_insn.eq(1)
  44         with m.Case(InternalOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
  45     with m.If(op == OP_MFSPR | op == OP_MTSPR):
  46         with m.If(insn[20]): # field XFX.spr[-1] i think
  47             comb += is_priv_insn.eq(1)
  48     return is_priv_insn
  49
  50
  51 class DecodeA(Elaboratable):
  52     """DecodeA from instruction
  53
  54     decodes register RA, whether immediate-zero, implicit and
  55     explicit CSRs
  56     """
  57
  58     def __init__(self, dec):
  59         self.dec = dec
  60         self.sel_in = Signal(In1Sel, reset_less=True)
  61         self.insn_in = Signal(32, reset_less=True)
  62         self.reg_out = Data(5, name="reg_a")
  63         self.immz_out = Signal(reset_less=True)
  64         self.spr_out = Data(10, "spr_a")
  65         self.fast_out = Data(3, "fast_a")
  66
  67     def elaborate(self, platform):
  68         m = Module()
  69         comb = m.d.comb
  70
  71         # select Register A field
  72         ra = Signal(5, reset_less=True)
  73         comb += ra.eq(self.dec.RA)
  74         with m.If((self.sel_in == In1Sel.RA) |
  75                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  76                    (ra != Const(0, 5)))):
  77             comb += self.reg_out.data.eq(ra)
  78             comb += self.reg_out.ok.eq(1)
  79
  80         # zero immediate requested
  81         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
  82                   (self.reg_out.data == Const(0, 5))):
  83             comb += self.immz_out.eq(1)
  84
  85         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
  86         with m.If(self.sel_in == In1Sel.RS):
  87             comb += self.reg_out.data.eq(self.dec.RS)
  88             comb += self.reg_out.ok.eq(1)
  89
  90         # decode Fast-SPR based on instruction type
  91         op = self.dec.op
  92         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
  93         with m.If(op.internal_op == InternalOp.OP_BC):
  94             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
  95                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
  96                 comb += self.fast_out.ok.eq(1)
  97         with m.Elif(op.internal_op == InternalOp.OP_BCREG):
  98             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
  99             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
 100             with m.If(xo9 & ~xo5):
 101                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
 102                 comb += self.fast_out.ok.eq(1)
 103
 104         # MFSPR move from SPRs
 105         with m.If(op.internal_op == InternalOp.OP_MFSPR):
 106             spr = Signal(10, reset_less=True)
 107             comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
 108             with m.Switch(spr):
 109                 # fast SPRs
 110                 with m.Case(SPR.CTR.value):
 111                     comb += self.fast_out.data.eq(FastRegs.CTR)
 112                     comb += self.fast_out.ok.eq(1)
 113                 with m.Case(SPR.LR.value):
 114                     comb += self.fast_out.data.eq(FastRegs.LR)
 115                     comb += self.fast_out.ok.eq(1)
 116                 with m.Case(SPR.TAR.value):
 117                     comb += self.fast_out.data.eq(FastRegs.TAR)
 118                     comb += self.fast_out.ok.eq(1)
 119                 with m.Case(SPR.SRR0.value):
 120                     comb += self.fast_out.data.eq(FastRegs.SRR0)
 121                     comb += self.fast_out.ok.eq(1)
 122                 with m.Case(SPR.SRR1.value):
 123                     comb += self.fast_out.data.eq(FastRegs.SRR1)
 124                     comb += self.fast_out.ok.eq(1)
 125                 with m.Case(SPR.XER.value):
 126                     pass # do nothing
 127                 # XXX TODO: map to internal SPR numbers
 128                 # XXX TODO: dec and tb not to go through mapping.
 129                 with m.Default():
 130                     comb += self.spr_out.data.eq(spr)
 131                     comb += self.spr_out.ok.eq(1)
 132
 133
 134         return m
 135
 136
 137 class DecodeB(Elaboratable):
 138     """DecodeB from instruction
 139
 140     decodes register RB, different forms of immediate (signed, unsigned),
 141     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 142     by industry-standard convention, "lane 2" is where fully-decoded
 143     immediates are muxed in.
 144     """
 145
 146     def __init__(self, dec):
 147         self.dec = dec
 148         self.sel_in = Signal(In2Sel, reset_less=True)
 149         self.insn_in = Signal(32, reset_less=True)
 150         self.reg_out = Data(5, "reg_b")
 151         self.imm_out = Data(64, "imm_b")
 152         self.fast_out = Data(3, "fast_b")
 153
 154     def elaborate(self, platform):
 155         m = Module()
 156         comb = m.d.comb
 157
 158         # select Register B field
 159         with m.Switch(self.sel_in):
 160             with m.Case(In2Sel.RB):
 161                 comb += self.reg_out.data.eq(self.dec.RB)
 162                 comb += self.reg_out.ok.eq(1)
 163             with m.Case(In2Sel.RS):
 164                 comb += self.reg_out.data.eq(self.dec.RS) # for M-Form shiftrot
 165                 comb += self.reg_out.ok.eq(1)
 166             with m.Case(In2Sel.CONST_UI):
 167                 comb += self.imm_out.data.eq(self.dec.UI)
 168                 comb += self.imm_out.ok.eq(1)
 169             with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here?
 170                 comb += self.imm_out.data.eq(
 171                     exts(self.dec.SI, 16, 64))
 172                 comb += self.imm_out.ok.eq(1)
 173             with m.Case(In2Sel.CONST_UI_HI):
 174                 comb += self.imm_out.data.eq(self.dec.UI<<16)
 175                 comb += self.imm_out.ok.eq(1)
 176             with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here?
 177                 comb += self.imm_out.data.eq(self.dec.SI<<16)
 178                 comb += self.imm_out.data.eq(
 179                     exts(self.dec.SI << 16, 32, 64))
 180                 comb += self.imm_out.ok.eq(1)
 181             with m.Case(In2Sel.CONST_LI):
 182                 comb += self.imm_out.data.eq(self.dec.LI<<2)
 183                 comb += self.imm_out.ok.eq(1)
 184             with m.Case(In2Sel.CONST_BD):
 185                 comb += self.imm_out.data.eq(self.dec.BD<<2)
 186                 comb += self.imm_out.ok.eq(1)
 187             with m.Case(In2Sel.CONST_DS):
 188                 comb += self.imm_out.data.eq(self.dec.DS<<2)
 189                 comb += self.imm_out.ok.eq(1)
 190             with m.Case(In2Sel.CONST_M1):
 191                 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
 192                 comb += self.imm_out.ok.eq(1)
 193             with m.Case(In2Sel.CONST_SH):
 194                 comb += self.imm_out.data.eq(self.dec.sh)
 195                 comb += self.imm_out.ok.eq(1)
 196             with m.Case(In2Sel.CONST_SH32):
 197                 comb += self.imm_out.data.eq(self.dec.SH32)
 198                 comb += self.imm_out.ok.eq(1)
 199
 200         # decode SPR2 based on instruction type
 201         op = self.dec.op
 202         # BCREG implicitly uses LR or TAR for 2nd reg
 203         # CTR however is already in fast_spr1 *not* 2.
 204         with m.If(op.internal_op == InternalOp.OP_BCREG):
 205             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
 206             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
 207             with m.If(~xo9):
 208                 comb += self.fast_out.data.eq(FastRegs.LR)
 209                 comb += self.fast_out.ok.eq(1)
 210             with m.Elif(xo5):
 211                 comb += self.fast_out.data.eq(FastRegs.TAR)
 212                 comb += self.fast_out.ok.eq(1)
 213
 214         return m
 215
 216
 217 class DecodeC(Elaboratable):
 218     """DecodeC from instruction
 219
 220     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 221     """
 222
 223     def __init__(self, dec):
 224         self.dec = dec
 225         self.sel_in = Signal(In3Sel, reset_less=True)
 226         self.insn_in = Signal(32, reset_less=True)
 227         self.reg_out = Data(5, "reg_c")
 228
 229     def elaborate(self, platform):
 230         m = Module()
 231         comb = m.d.comb
 232
 233         # select Register C field
 234         with m.Switch(self.sel_in):
 235             with m.Case(In3Sel.RB):
 236                 comb += self.reg_out.data.eq(self.dec.RB) # for M-Form shiftrot
 237                 comb += self.reg_out.ok.eq(1)
 238             with m.Case(In3Sel.RS):
 239                 comb += self.reg_out.data.eq(self.dec.RS)
 240                 comb += self.reg_out.ok.eq(1)
 241
 242         return m
 243
 244
 245 class DecodeOut(Elaboratable):
 246     """DecodeOut from instruction
 247
 248     decodes output register RA, RT or SPR
 249     """
 250
 251     def __init__(self, dec):
 252         self.dec = dec
 253         self.sel_in = Signal(OutSel, reset_less=True)
 254         self.insn_in = Signal(32, reset_less=True)
 255         self.reg_out = Data(5, "reg_o")
 256         self.spr_out = Data(10, "spr_o")
 257         self.fast_out = Data(3, "fast_o")
 258
 259     def elaborate(self, platform):
 260         m = Module()
 261         comb = m.d.comb
 262         op = self.dec.op
 263
 264         # select Register out field
 265         with m.Switch(self.sel_in):
 266             with m.Case(OutSel.RT):
 267                 comb += self.reg_out.data.eq(self.dec.RT)
 268                 comb += self.reg_out.ok.eq(1)
 269             with m.Case(OutSel.RA):
 270                 comb += self.reg_out.data.eq(self.dec.RA)
 271                 comb += self.reg_out.ok.eq(1)
 272             with m.Case(OutSel.SPR):
 273                 spr = Signal(10, reset_less=True)
 274                 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
 275                 # TODO MTSPR 1st spr (fast)
 276                 with m.If(op.internal_op == InternalOp.OP_MTSPR):
 277                     with m.Switch(spr):
 278                         # fast SPRs
 279                         with m.Case(SPR.CTR.value):
 280                             comb += self.fast_out.data.eq(FastRegs.CTR)
 281                             comb += self.fast_out.ok.eq(1)
 282                         with m.Case(SPR.LR.value):
 283                             comb += self.fast_out.data.eq(FastRegs.LR)
 284                             comb += self.fast_out.ok.eq(1)
 285                         with m.Case(SPR.TAR.value):
 286                             comb += self.fast_out.data.eq(FastRegs.TAR)
 287                             comb += self.fast_out.ok.eq(1)
 288                         with m.Case(SPR.SRR0.value):
 289                             comb += self.fast_out.data.eq(FastRegs.SRR0)
 290                             comb += self.fast_out.ok.eq(1)
 291                         with m.Case(SPR.SRR1.value):
 292                             comb += self.fast_out.data.eq(FastRegs.SRR1)
 293                             comb += self.fast_out.ok.eq(1)
 294                         with m.Case(SPR.XER.value):
 295                             pass # do nothing
 296                         # XXX TODO: map to internal SPR numbers
 297                         # XXX TODO: dec and tb not to go through mapping.
 298                         with m.Default():
 299                             comb += self.spr_out.data.eq(spr)
 300                             comb += self.spr_out.ok.eq(1)
 301
 302         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
 303         op = self.dec.op
 304         with m.If((op.internal_op == InternalOp.OP_BC) |
 305                   (op.internal_op == InternalOp.OP_BCREG)):
 306             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
 307                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
 308                 comb += self.fast_out.ok.eq(1)
 309
 310         # RFID 1st spr (fast)
 311         with m.If(op.internal_op == InternalOp.OP_RFID):
 312             comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
 313             comb += self.fast_out.ok.eq(1)
 314
 315         return m
 316
 317
 318 class DecodeOut2(Elaboratable):
 319     """DecodeOut2 from instruction
 320
 321     decodes output registers
 322     """
 323
 324     def __init__(self, dec):
 325         self.dec = dec
 326         self.sel_in = Signal(OutSel, reset_less=True)
 327         self.lk = Signal(reset_less=True)
 328         self.insn_in = Signal(32, reset_less=True)
 329         self.reg_out = Data(5, "reg_o")
 330         self.fast_out = Data(3, "fast_o")
 331
 332     def elaborate(self, platform):
 333         m = Module()
 334         comb = m.d.comb
 335
 336         # update mode LD/ST uses read-reg A also as an output
 337         with m.If(self.dec.op.upd):
 338             comb += self.reg_out.eq(self.dec.RA)
 339             comb += self.reg_out.ok.eq(1)
 340
 341         # BC or BCREG: potential implicit register (LR) output
 342         op = self.dec.op
 343         with m.If((op.internal_op == InternalOp.OP_BC) |
 344                   (op.internal_op == InternalOp.OP_BCREG)):
 345             with m.If(self.lk): # "link" mode
 346                 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
 347                 comb += self.fast_out.ok.eq(1)
 348
 349         # RFID 2nd spr (fast)
 350         with m.If(op.internal_op == InternalOp.OP_RFID):
 351                 comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
 352                 comb += self.fast_out.ok.eq(1)
 353
 354         return m
 355
 356
 357 class DecodeRC(Elaboratable):
 358     """DecodeRc from instruction
 359
 360     decodes Record bit Rc
 361     """
 362     def __init__(self, dec):
 363         self.dec = dec
 364         self.sel_in = Signal(RC, reset_less=True)
 365         self.insn_in = Signal(32, reset_less=True)
 366         self.rc_out = Data(1, "rc")
 367
 368     def elaborate(self, platform):
 369         m = Module()
 370         comb = m.d.comb
 371
 372         # select Record bit out field
 373         with m.Switch(self.sel_in):
 374             with m.Case(RC.RC):
 375                 comb += self.rc_out.data.eq(self.dec.Rc)
 376                 comb += self.rc_out.ok.eq(1)
 377             with m.Case(RC.ONE):
 378                 comb += self.rc_out.data.eq(1)
 379                 comb += self.rc_out.ok.eq(1)
 380             with m.Case(RC.NONE):
 381                 comb += self.rc_out.data.eq(0)
 382                 comb += self.rc_out.ok.eq(1)
 383
 384         return m
 385
 386
 387 class DecodeOE(Elaboratable):
 388     """DecodeOE from instruction
 389
 390     decodes OE field: uses RC decode detection which might not be good
 391
 392     -- For now, use "rc" in the decode table to decide whether oe exists.
 393     -- This is not entirely correct architecturally: For mulhd and
 394     -- mulhdu, the OE field is reserved. It remains to be seen what an
 395     -- actual POWER9 does if we set it on those instructions, for now we
 396     -- test that further down when assigning to the multiplier oe input.
 397     """
 398     def __init__(self, dec):
 399         self.dec = dec
 400         self.sel_in = Signal(RC, reset_less=True)
 401         self.insn_in = Signal(32, reset_less=True)
 402         self.oe_out = Data(1, "oe")
 403
 404     def elaborate(self, platform):
 405         m = Module()
 406         comb = m.d.comb
 407
 408         # select OE bit out field
 409         with m.Switch(self.sel_in):
 410             with m.Case(RC.RC):
 411                 comb += self.oe_out.data.eq(self.dec.OE)
 412                 comb += self.oe_out.ok.eq(1)
 413
 414         return m
 415
 416 class DecodeCRIn(Elaboratable):
 417     """Decodes input CR from instruction
 418
 419     CR indices - insn fields - (not the data *in* the CR) require only 3
 420     bits because they refer to CR0-CR7
 421     """
 422
 423     def __init__(self, dec):
 424         self.dec = dec
 425         self.sel_in = Signal(CRInSel, reset_less=True)
 426         self.insn_in = Signal(32, reset_less=True)
 427         self.cr_bitfield = Data(3, "cr_bitfield")
 428         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 429         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 430         self.whole_reg = Signal(reset_less=True)
 431
 432     def elaborate(self, platform):
 433         m = Module()
 434         comb = m.d.comb
 435
 436         comb += self.cr_bitfield.ok.eq(0)
 437         comb += self.cr_bitfield_b.ok.eq(0)
 438         comb += self.whole_reg.eq(0)
 439         with m.Switch(self.sel_in):
 440             with m.Case(CRInSel.NONE):
 441                 pass # No bitfield activated
 442             with m.Case(CRInSel.CR0):
 443                 comb += self.cr_bitfield.data.eq(0)
 444                 comb += self.cr_bitfield.ok.eq(1)
 445             with m.Case(CRInSel.BI):
 446                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 447                 comb += self.cr_bitfield.ok.eq(1)
 448             with m.Case(CRInSel.BFA):
 449                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 450                 comb += self.cr_bitfield.ok.eq(1)
 451             with m.Case(CRInSel.BA_BB):
 452                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 453                 comb += self.cr_bitfield.ok.eq(1)
 454                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 455                 comb += self.cr_bitfield_b.ok.eq(1)
 456                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 457                 comb += self.cr_bitfield_o.ok.eq(1)
 458             with m.Case(CRInSel.BC):
 459                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 460                 comb += self.cr_bitfield.ok.eq(1)
 461             with m.Case(CRInSel.WHOLE_REG):
 462                 comb += self.whole_reg.eq(1)
 463
 464         return m
 465
 466
 467 class DecodeCROut(Elaboratable):
 468     """Decodes input CR from instruction
 469
 470     CR indices - insn fields - (not the data *in* the CR) require only 3
 471     bits because they refer to CR0-CR7
 472     """
 473
 474     def __init__(self, dec):
 475         self.dec = dec
 476         self.rc_in = Signal(reset_less=True)
 477         self.sel_in = Signal(CROutSel, reset_less=True)
 478         self.insn_in = Signal(32, reset_less=True)
 479         self.cr_bitfield = Data(3, "cr_bitfield")
 480         self.whole_reg = Signal(reset_less=True)
 481
 482     def elaborate(self, platform):
 483         m = Module()
 484         comb = m.d.comb
 485
 486         comb += self.cr_bitfield.ok.eq(0)
 487         comb += self.whole_reg.eq(0)
 488         with m.Switch(self.sel_in):
 489             with m.Case(CROutSel.NONE):
 490                 pass # No bitfield activated
 491             with m.Case(CROutSel.CR0):
 492                 comb += self.cr_bitfield.data.eq(0)
 493                 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
 494             with m.Case(CROutSel.BF):
 495                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
 496                 comb += self.cr_bitfield.ok.eq(1)
 497             with m.Case(CROutSel.BT):
 498                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 499                 comb += self.cr_bitfield.ok.eq(1)
 500             with m.Case(CROutSel.WHOLE_REG):
 501                 comb += self.whole_reg.eq(1)
 502
 503         return m
 504
 505
 506 class XerBits:
 507     def __init__(self):
 508         self.ca = Signal(2, reset_less=True)
 509         self.ov = Signal(2, reset_less=True)
 510         self.so = Signal(reset_less=True)
 511
 512     def ports(self):
 513         return [self.ca, self.ov, self.so]
 514
 515
 516 class PowerDecode2(Elaboratable):
 517
 518     def __init__(self, dec):
 519
 520         self.dec = dec
 521         self.e = Decode2ToExecute1Type()
 522
 523     def ports(self):
 524         return self.dec.ports() + self.e.ports()
 525
 526     def elaborate(self, platform):
 527         m = Module()
 528         comb = m.d.comb
 529         e, op = self.e, self.dec.op
 530
 531         # set up submodule decoders
 532         m.submodules.dec = self.dec
 533         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 534         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 535         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 536         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 537         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
 538         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 539         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 540         m.submodules.dec_cr_in = dec_cr_in = DecodeCRIn(self.dec)
 541         m.submodules.dec_cr_out = dec_cr_out = DecodeCROut(self.dec)
 542
 543         # copy instruction through...
 544         for i in [e.insn, dec_a.insn_in, dec_b.insn_in,
 545                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in, dec_rc.insn_in,
 546                   dec_oe.insn_in, dec_cr_in.insn_in, dec_cr_out.insn_in]:
 547             comb += i.eq(self.dec.opcode_in)
 548
 549         # ...and subdecoders' input fields
 550         comb += dec_a.sel_in.eq(op.in1_sel)
 551         comb += dec_b.sel_in.eq(op.in2_sel)
 552         comb += dec_c.sel_in.eq(op.in3_sel)
 553         comb += dec_o.sel_in.eq(op.out_sel)
 554         comb += dec_o2.sel_in.eq(op.out_sel)
 555         comb += dec_o2.lk.eq(e.lk)
 556         comb += dec_rc.sel_in.eq(op.rc_sel)
 557         comb += dec_oe.sel_in.eq(op.rc_sel) # XXX should be OE sel
 558         comb += dec_cr_in.sel_in.eq(op.cr_in)
 559         comb += dec_cr_out.sel_in.eq(op.cr_out)
 560         comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
 561
 562
 563         comb += e.nia.eq(0)    # XXX TODO (or remove? not sure yet)
 564         fu = op.function_unit
 565         itype = Mux(fu == Function.NONE, InternalOp.OP_ILLEGAL, op.internal_op)
 566         comb += e.insn_type.eq(itype)
 567         comb += e.fn_unit.eq(fu)
 568
 569         # registers a, b, c and out and out2 (LD/ST EA)
 570         comb += e.read_reg1.eq(dec_a.reg_out)
 571         comb += e.read_reg2.eq(dec_b.reg_out)
 572         comb += e.read_reg3.eq(dec_c.reg_out)
 573         comb += e.write_reg.eq(dec_o.reg_out)
 574         comb += e.write_ea.eq(dec_o2.reg_out)
 575         comb += e.imm_data.eq(dec_b.imm_out) # immediate in RB (usually)
 576         comb += e.zero_a.eq(dec_a.immz_out)  # RA==0 detected
 577
 578         # rc and oe out
 579         comb += e.rc.eq(dec_rc.rc_out)
 580         comb += e.oe.eq(dec_oe.oe_out)
 581
 582         # SPRs out
 583         comb += e.read_spr1.eq(dec_a.spr_out)
 584         comb += e.write_spr.eq(dec_o.spr_out)
 585
 586         # Fast regs out
 587         comb += e.read_fast1.eq(dec_a.fast_out)
 588         comb += e.read_fast2.eq(dec_b.fast_out)
 589         comb += e.write_fast1.eq(dec_o.fast_out)
 590         comb += e.write_fast1.eq(dec_o2.fast_out)
 591
 592         comb += e.read_cr1.eq(dec_cr_in.cr_bitfield)
 593         comb += e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
 594         comb += e.read_cr3.eq(dec_cr_in.cr_bitfield_o)
 595         comb += e.read_cr_whole.eq(dec_cr_in.whole_reg)
 596
 597         comb += e.write_cr.eq(dec_cr_out.cr_bitfield)
 598         comb += e.write_cr_whole.eq(dec_cr_out.whole_reg)
 599
 600         # decoded/selected instruction flags
 601         comb += e.data_len.eq(op.ldst_len)
 602         comb += e.invert_a.eq(op.inv_a)
 603         comb += e.invert_out.eq(op.inv_out)
 604         comb += e.input_carry.eq(op.cry_in)   # carry comes in
 605         comb += e.output_carry.eq(op.cry_out) # carry goes out
 606         comb += e.is_32bit.eq(op.is_32b)
 607         comb += e.is_signed.eq(op.sgn)
 608         with m.If(op.lk):
 609             comb += e.lk.eq(self.dec.LK) # XXX TODO: accessor
 610
 611         comb += e.byte_reverse.eq(op.br)
 612         comb += e.sign_extend.eq(op.sgn_ext)
 613         comb += e.update.eq(op.upd) # LD/ST "update" mode.
 614
 615
 616         # These should be removed eventually
 617         comb += e.input_cr.eq(op.cr_in)   # condition reg comes in
 618         comb += e.output_cr.eq(op.cr_out) # condition reg goes in
 619
 620         # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
 621         with m.If(op.internal_op == InternalOp.OP_TRAP):
 622             comb += e.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
 623
 624         return m
 625
 626         # privileged instruction
 627         with m.If(instr_is_priv(m, op.internal_op, e.insn) & msr[MSR_PR]):
 628             # don't request registers RA/RT
 629             comb += e.read_reg1.eq(0)
 630             comb += e.read_reg2.eq(0)
 631             comb += e.read_reg3.eq(0)
 632             comb += e.write_reg.eq(0)
 633             comb += e.write_ea.eq(0)
 634             # privileged instruction trap
 635             comb += op.internal_op.eq(InternalOp.OP_TRAP)
 636             comb += e.traptype.eq(TT_PRIV) # request privileged instruction
 637             comb += e.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
 638         return m
 639
 640     def regspecmap_read(self, regfile, regname):
 641         """regspecmap_read: provides PowerDecode2 with an encoding relationship
 642         to Function Unit port regfiles (read-enable, read regnum, write regnum)
 643         regfile and regname arguments are fields 1 and 2 from a given regspec.
 644         """
 645         return regspec_decode_read(self.e, regfile, regname)
 646
 647     def regspecmap_write(self, regfile, regname):
 648         """regspecmap_write: provides PowerDecode2 with an encoding relationship
 649         to Function Unit port regfiles (write port, write regnum)
 650         regfile and regname arguments are fields 1 and 2 from a given regspec.
 651         """
 652         return regspec_decode_write(self.e, regfile, regname)
 653
 654     def rdflags(self, cu):
 655         rdl = []
 656         for idx in range(cu.n_src):
 657             regfile, regname, _ = cu.get_in_spec(idx)
 658             rdflag, read = self.regspecmap_read(regfile, regname)
 659             rdl.append(rdflag)
 660         print ("rdflags", rdl)
 661         return Cat(*rdl)
 662
 663
 664 if __name__ == '__main__':
 665     pdecode = create_pdecode()
 666     dec2 = PowerDecode2(pdecode)
 667     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 668     with open("dec2.il", "w") as f:
 669         f.write(vl)
 670