cd9bae1bd0e40f15adebbccb870ea7cf94d59e9c
1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from soc
.regfile
.regfiles
import XERRegs
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from soc
.experiment
.mem_types
import LDSTException
19 from soc
.decoder
.power_regspec_map
import regspec_decode_read
20 from soc
.decoder
.power_regspec_map
import regspec_decode_write
21 from soc
.decoder
.power_decoder
import create_pdecode
22 from soc
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
24 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
25 OutSel
, SPR
, RC
, LDSTMode
,
27 from soc
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
29 from soc
.sv
.svp64
import SVP64Rec
30 from soc
.consts
import MSR
32 from soc
.regfile
.regfiles
import FastRegs
33 from soc
.consts
import TT
34 from soc
.config
.state
import CoreState
35 from soc
.regfile
.util
import spr_to_fast
38 def decode_spr_num(spr
):
39 return Cat(spr
[5:10], spr
[0:5])
42 def instr_is_priv(m
, op
, insn
):
43 """determines if the instruction is privileged or not
46 is_priv_insn
= Signal(reset_less
=True)
48 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
49 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
50 comb
+= is_priv_insn
.eq(1)
52 #with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
53 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
54 with m
.If(insn
[20]): # field XFX.spr[-1] i think
55 comb
+= is_priv_insn
.eq(1)
59 class SPRMap(Elaboratable
):
60 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
64 self
.spr_i
= Signal(10, reset_less
=True)
65 self
.spr_o
= Data(SPR
, name
="spr_o")
66 self
.fast_o
= Data(3, name
="fast_o")
68 def elaborate(self
, platform
):
70 with m
.Switch(self
.spr_i
):
71 for i
, x
in enumerate(SPR
):
73 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
74 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
75 for x
, v
in spr_to_fast
.items():
77 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
78 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
82 class SVP64ExtraSpec(Elaboratable
):
83 """SVP64ExtraSpec - decodes SVP64 Extra specification.
85 selects the required EXTRA2/3 field.
87 see https://libre-soc.org/openpower/sv/svp64/
90 self
.extra
= Signal(10, reset_less
=True)
91 self
.etype
= Signal(SVEtype
, reset_less
=True) # 2 or 3 bits
92 self
.idx
= Signal(SVEXTRA
, reset_less
=True) # which part of extra
93 self
.spec
= Signal(3) # EXTRA spec for the register
95 def elaborate(self
, platform
):
100 # back in the LDSTRM-* and RM-* files generated by sv_analysis.py
101 # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
102 # which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
103 # the register-extension information. extract those now
104 with m
.Switch(self
.etype
):
105 # 2-bit index selection mode
106 with m
.Case(SVEtype
.EXTRA2
):
107 with m
.Switch(self
.idx
):
108 with m
.Case(SVEXTRA
.Idx0
): # 1st 2 bits
109 comb
+= spec
[1:3].eq(self
.extra
[0:2])
110 with m
.Case(SVEXTRA
.Idx1
): # 2nd 2 bits
111 comb
+= spec
[1:3].eq(self
.extra
[2:4])
112 with m
.Case(SVEXTRA
.Idx2
): # 3rd 2 bits
113 comb
+= spec
[1:3].eq(self
.extra
[4:6])
114 with m
.Case(SVEXTRA
.Idx3
): # 4th 2 bits
115 comb
+= spec
[1:3].eq(self
.extra
[6:8])
116 # 3-bit index selection mode
117 with m
.Case(SVEtype
.EXTRA3
):
118 with m
.Switch(self
.idx
):
119 with m
.Case(SVEXTRA
.Idx0
): # 1st 3 bits
120 comb
+= spec
.eq(self
.extra
[0:3])
121 with m
.Case(SVEXTRA
.Idx1
): # 2nd 3 bits
122 comb
+= spec
.eq(self
.extra
[3:6])
123 with m
.Case(SVEXTRA
.Idx2
): # 3rd 3 bits
124 comb
+= spec
.eq(self
.extra
[6:9])
125 # cannot fit more than 9 bits so there is no 4th thing
130 class SVP64RegExtra(SVP64ExtraSpec
):
131 """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
133 incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
134 depending on info in one of the positions in the EXTRA field.
136 designed so that "no change" to the 5-bit register number occurs if
137 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
139 see https://libre-soc.org/openpower/sv/svp64/
142 SVP64ExtraSpec
.__init
__(self
)
143 self
.reg_in
= Signal(5) # incoming reg number (5 bits, RA, RB)
144 self
.reg_out
= Signal(7) # extra-augmented output (7 bits)
145 self
.isvec
= Signal(1) # reg is marked as vector if true
147 def elaborate(self
, platform
):
148 m
= super().elaborate(platform
) # select required EXTRA2/3
151 # first get the spec. if not changed it's "scalar identity behaviour"
152 # which is zero which is ok.
155 # now decode it. bit 2 is "scalar/vector". note that spec could be zero
156 # from above, which (by design) has the effect of "no change", below.
158 # simple: isvec is top bit of spec
159 comb
+= self
.isvec
.eq(spec
[2])
161 # decode vector differently from scalar
162 with m
.If(self
.isvec
):
163 # Vector: shifted up, extra in LSBs (RA << 2) | spec[0:1]
164 comb
+= self
.reg_out
.eq(Cat(spec
[:2], self
.reg_in
))
166 # Scalar: not shifted up, extra in MSBs RA | (spec[0:1] << 5)
167 comb
+= self
.reg_out
.eq(Cat(self
.reg_in
, spec
[:2]))
172 class SVP64CRExtra(SVP64ExtraSpec
):
173 """SVP64CRExtra - decodes SVP64 Extra fields to determine CR extension
175 incoming 3-bit CR is turned into a 7-bit and marked as scalar/vector
176 depending on info in one of the positions in the EXTRA field.
178 yes, really, 128 CRs. INT is 128, FP is 128, therefore CRs are 128.
180 designed so that "no change" to the 3-bit CR register number occurs if
181 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
183 see https://libre-soc.org/openpower/sv/svp64/appendix
186 SVP64ExtraSpec
.__init
__(self
)
187 self
.cr_in
= Signal(3) # incoming CR number (3 bits, BA[2:5], BFA)
188 self
.cr_out
= Signal(7) # extra-augmented CR output (7 bits)
189 self
.isvec
= Signal(1) # reg is marked as vector if true
191 def elaborate(self
, platform
):
192 m
= super().elaborate(platform
) # select required EXTRA2/3
195 # first get the spec. if not changed it's "scalar identity behaviour"
196 # which is zero which is ok.
199 # now decode it. bit 2 is "scalar/vector". note that spec could be zero
200 # from above, which (by design) has the effect of "no change", below.
202 # simple: isvec is top bit of spec
203 comb
+= self
.isvec
.eq(spec
[2])
205 # decode vector differently from scalar, insert bits 0 and 1 accordingly
206 with m
.If(self
.isvec
):
207 # Vector: shifted up, extra in LSBs (CR << 4) | (spec[0:1] << 2)
208 comb
+= self
.cr_out
.eq(Cat(Const(0, 2), spec
[:2], self
.cr_in
))
210 # Scalar: not shifted up, extra in MSBs CR | (spec[0:1] << 3)
211 comb
+= self
.cr_out
.eq(Cat(self
.cr_in
, spec
[:2]))
216 class DecodeA(Elaboratable
):
217 """DecodeA from instruction
219 decodes register RA, implicit and explicit CSRs
222 def __init__(self
, dec
):
224 self
.sv_rm
= SVP64Rec() # SVP64 RM field
225 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
226 self
.insn_in
= Signal(32, reset_less
=True)
227 self
.reg_out
= Data(7, name
="reg_a")
228 self
.reg_isvec
= Signal(1, name
="reg_a_isvec") # TODO: in reg_out
229 self
.spr_out
= Data(SPR
, "spr_a")
230 self
.fast_out
= Data(3, "fast_a")
232 def elaborate(self
, platform
):
236 m
.submodules
.sprmap
= sprmap
= SPRMap()
237 m
.submodules
.svdec
= svdec
= SVP64RegExtra()
239 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
240 reg
= Signal(5, reset_less
=True)
242 # select Register A field
243 ra
= Signal(5, reset_less
=True)
244 comb
+= ra
.eq(self
.dec
.RA
)
245 with m
.If((self
.sel_in
== In1Sel
.RA
) |
246 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
247 (ra
!= Const(0, 5)))):
249 comb
+= self
.reg_out
.ok
.eq(1)
251 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
252 # moved it to 1st position (in1_sel)... because
253 rs
= Signal(5, reset_less
=True)
254 comb
+= rs
.eq(self
.dec
.RS
)
255 with m
.If(self
.sel_in
== In1Sel
.RS
):
257 comb
+= self
.reg_out
.ok
.eq(1)
259 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
260 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
261 # which in turn were auto-generated by sv_analysis.py
263 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
264 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
265 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
266 comb
+= svdec
.idx
.eq(op
.sv_in1
) # SVP64 reg #1 (matches in1_sel)
267 comb
+= svdec
.reg_in
.eq(reg
) # 5-bit (RA, RS)
269 # outputs: 7-bit reg number and whether it's vectorised
270 comb
+= self
.reg_out
.data
.eq(svdec
.reg_out
)
271 comb
+= self
.reg_isvec
.eq(svdec
.isvec
)
273 # decode Fast-SPR based on instruction type
274 with m
.Switch(op
.internal_op
):
276 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
277 with m
.Case(MicrOp
.OP_BC
):
278 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
280 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
281 comb
+= self
.fast_out
.ok
.eq(1)
282 with m
.Case(MicrOp
.OP_BCREG
):
283 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
284 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
285 with m
.If(xo9
& ~xo5
):
287 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
288 comb
+= self
.fast_out
.ok
.eq(1)
290 # MFSPR move from SPRs
291 with m
.Case(MicrOp
.OP_MFSPR
):
292 spr
= Signal(10, reset_less
=True)
293 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
294 comb
+= sprmap
.spr_i
.eq(spr
)
295 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
296 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
301 class DecodeAImm(Elaboratable
):
302 """DecodeA immediate from instruction
304 decodes register RA, whether immediate-zero, implicit and
308 def __init__(self
, dec
):
310 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
311 self
.immz_out
= Signal(reset_less
=True)
313 def elaborate(self
, platform
):
317 # zero immediate requested
318 ra
= Signal(5, reset_less
=True)
319 comb
+= ra
.eq(self
.dec
.RA
)
320 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) & (ra
== Const(0, 5))):
321 comb
+= self
.immz_out
.eq(1)
326 class DecodeB(Elaboratable
):
327 """DecodeB from instruction
329 decodes register RB, different forms of immediate (signed, unsigned),
330 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
331 by industry-standard convention, "lane 2" is where fully-decoded
332 immediates are muxed in.
335 def __init__(self
, dec
):
337 self
.sv_rm
= SVP64Rec() # SVP64 RM field
338 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
339 self
.insn_in
= Signal(32, reset_less
=True)
340 self
.reg_out
= Data(7, "reg_b")
341 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
342 self
.fast_out
= Data(3, "fast_b")
344 def elaborate(self
, platform
):
348 m
.submodules
.svdec
= svdec
= SVP64RegExtra()
350 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
351 reg
= Signal(5, reset_less
=True)
353 # select Register B field
354 with m
.Switch(self
.sel_in
):
355 with m
.Case(In2Sel
.RB
):
356 comb
+= reg
.eq(self
.dec
.RB
)
357 comb
+= self
.reg_out
.ok
.eq(1)
358 with m
.Case(In2Sel
.RS
):
359 # for M-Form shiftrot
360 comb
+= reg
.eq(self
.dec
.RS
)
361 comb
+= self
.reg_out
.ok
.eq(1)
363 # now do the SVP64 munging. different from DecodeA only by sv_in2
365 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
366 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
367 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
368 comb
+= svdec
.idx
.eq(op
.sv_in2
) # SVP64 reg #2 (matches in2_sel)
369 comb
+= svdec
.reg_in
.eq(reg
) # 5-bit (RA, RS)
371 # outputs: 7-bit reg number and whether it's vectorised
372 comb
+= self
.reg_out
.data
.eq(svdec
.reg_out
)
373 comb
+= self
.reg_isvec
.eq(svdec
.isvec
)
375 # decode SPR2 based on instruction type
376 # BCREG implicitly uses LR or TAR for 2nd reg
377 # CTR however is already in fast_spr1 *not* 2.
378 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
379 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
380 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
382 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
383 comb
+= self
.fast_out
.ok
.eq(1)
385 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
386 comb
+= self
.fast_out
.ok
.eq(1)
391 class DecodeBImm(Elaboratable
):
392 """DecodeB immediate from instruction
394 def __init__(self
, dec
):
396 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
397 self
.imm_out
= Data(64, "imm_b")
399 def elaborate(self
, platform
):
403 # select Register B Immediate
404 with m
.Switch(self
.sel_in
):
405 with m
.Case(In2Sel
.CONST_UI
): # unsigned
406 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
407 comb
+= self
.imm_out
.ok
.eq(1)
408 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
409 si
= Signal(16, reset_less
=True)
410 comb
+= si
.eq(self
.dec
.SI
)
411 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
412 comb
+= self
.imm_out
.ok
.eq(1)
413 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
414 si_hi
= Signal(32, reset_less
=True)
415 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
416 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
417 comb
+= self
.imm_out
.ok
.eq(1)
418 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
419 ui
= Signal(16, reset_less
=True)
420 comb
+= ui
.eq(self
.dec
.UI
)
421 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
422 comb
+= self
.imm_out
.ok
.eq(1)
423 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
424 li
= Signal(26, reset_less
=True)
425 comb
+= li
.eq(self
.dec
.LI
<< 2)
426 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
427 comb
+= self
.imm_out
.ok
.eq(1)
428 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
429 bd
= Signal(16, reset_less
=True)
430 comb
+= bd
.eq(self
.dec
.BD
<< 2)
431 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
432 comb
+= self
.imm_out
.ok
.eq(1)
433 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
434 ds
= Signal(16, reset_less
=True)
435 comb
+= ds
.eq(self
.dec
.DS
<< 2)
436 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
437 comb
+= self
.imm_out
.ok
.eq(1)
438 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
439 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
440 comb
+= self
.imm_out
.ok
.eq(1)
441 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
442 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
443 comb
+= self
.imm_out
.ok
.eq(1)
444 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
445 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
446 comb
+= self
.imm_out
.ok
.eq(1)
451 class DecodeC(Elaboratable
):
452 """DecodeC from instruction
454 decodes register RC. this is "lane 3" into some CompUnits (not many)
457 def __init__(self
, dec
):
459 self
.sv_rm
= SVP64Rec() # SVP64 RM field
460 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
461 self
.insn_in
= Signal(32, reset_less
=True)
462 self
.reg_out
= Data(7, "reg_c")
463 self
.reg_isvec
= Signal(1, name
="reg_c_isvec") # TODO: in reg_out
465 def elaborate(self
, platform
):
469 m
.submodules
.svdec
= svdec
= SVP64RegExtra()
471 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
472 reg
= Signal(5, reset_less
=True)
474 # select Register C field
475 with m
.Switch(self
.sel_in
):
476 with m
.Case(In3Sel
.RB
):
477 # for M-Form shiftrot
478 comb
+= reg
.eq(self
.dec
.RB
)
479 comb
+= self
.reg_out
.ok
.eq(1)
480 with m
.Case(In3Sel
.RS
):
481 comb
+= reg
.eq(self
.dec
.RS
)
482 comb
+= self
.reg_out
.ok
.eq(1)
484 # now do the SVP64 munging. different from DecodeA only by sv_in3
486 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
487 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
488 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
489 comb
+= svdec
.idx
.eq(op
.sv_in3
) # SVP64 reg #3 (matches in3_sel)
490 comb
+= svdec
.reg_in
.eq(reg
) # 5-bit (RA, RS)
492 # outputs: 7-bit reg number and whether it's vectorised
493 comb
+= self
.reg_out
.data
.eq(svdec
.reg_out
)
494 comb
+= self
.reg_isvec
.eq(svdec
.isvec
)
499 class DecodeOut(Elaboratable
):
500 """DecodeOut from instruction
502 decodes output register RA, RT or SPR
505 def __init__(self
, dec
):
507 self
.sv_rm
= SVP64Rec() # SVP64 RM field
508 self
.sel_in
= Signal(OutSel
, reset_less
=True)
509 self
.insn_in
= Signal(32, reset_less
=True)
510 self
.reg_out
= Data(7, "reg_o")
511 self
.reg_isvec
= Signal(1, name
="reg_o_isvec") # TODO: in reg_out
512 self
.spr_out
= Data(SPR
, "spr_o")
513 self
.fast_out
= Data(3, "fast_o")
515 def elaborate(self
, platform
):
518 m
.submodules
.sprmap
= sprmap
= SPRMap()
520 m
.submodules
.svdec
= svdec
= SVP64RegExtra()
522 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
523 reg
= Signal(5, reset_less
=True)
525 # select Register out field
526 with m
.Switch(self
.sel_in
):
527 with m
.Case(OutSel
.RT
):
528 comb
+= reg
.eq(self
.dec
.RT
)
529 comb
+= self
.reg_out
.ok
.eq(1)
530 with m
.Case(OutSel
.RA
):
531 comb
+= reg
.eq(self
.dec
.RA
)
532 comb
+= self
.reg_out
.ok
.eq(1)
533 with m
.Case(OutSel
.SPR
):
534 spr
= Signal(10, reset_less
=True)
535 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
536 # MFSPR move to SPRs - needs mapping
537 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
538 comb
+= sprmap
.spr_i
.eq(spr
)
539 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
540 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
542 # now do the SVP64 munging. different from DecodeA only by sv_out
544 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
545 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
546 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
547 comb
+= svdec
.idx
.eq(op
.sv_out
) # SVP64 reg out1 (matches out_sel)
548 comb
+= svdec
.reg_in
.eq(reg
) # 5-bit (RA, RS)
550 # outputs: 7-bit reg number and whether it's vectorised
551 comb
+= self
.reg_out
.data
.eq(svdec
.reg_out
)
552 comb
+= self
.reg_isvec
.eq(svdec
.isvec
)
555 with m
.Switch(op
.internal_op
):
557 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
558 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
559 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
561 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
562 comb
+= self
.fast_out
.ok
.eq(1)
564 # RFID 1st spr (fast)
565 with m
.Case(MicrOp
.OP_RFID
):
566 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
567 comb
+= self
.fast_out
.ok
.eq(1)
572 class DecodeOut2(Elaboratable
):
573 """DecodeOut2 from instruction
575 decodes output registers (2nd one). note that RA is *implicit* below,
576 which now causes problems with SVP64
578 TODO: SVP64 is a little more complex, here. svp64 allows extending
579 by one more destination by having one more EXTRA field. RA-as-src
580 is not the same as RA-as-dest. limited in that it's the same first
581 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
582 for operations that have src-as-dest: mostly this is LD/ST-with-update
583 but there are others.
586 def __init__(self
, dec
):
588 self
.sv_rm
= SVP64Rec() # SVP64 RM field
589 self
.sel_in
= Signal(OutSel
, reset_less
=True)
590 self
.lk
= Signal(reset_less
=True)
591 self
.insn_in
= Signal(32, reset_less
=True)
592 self
.reg_out
= Data(7, "reg_o2")
593 #self.reg_isvec = Signal(1, name="reg_o2_isvec") # TODO: in reg_out
594 self
.fast_out
= Data(3, "fast_o2")
596 def elaborate(self
, platform
):
600 #m.submodules.svdec = svdec = SVP64RegExtra()
602 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
603 #reg = Signal(5, reset_less=True)
605 if hasattr(self
.dec
.op
, "upd"):
606 # update mode LD/ST uses read-reg A also as an output
607 with m
.If(self
.dec
.op
.upd
== LDSTMode
.update
):
608 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
609 comb
+= self
.reg_out
.ok
.eq(1)
611 # B, BC or BCREG: potential implicit register (LR) output
612 # these give bl, bcl, bclrl, etc.
613 with m
.Switch(op
.internal_op
):
615 # BC* implicit register (LR)
616 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
617 with m
.If(self
.lk
): # "link" mode
618 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
) # constant: LR
619 comb
+= self
.fast_out
.ok
.eq(1)
621 # RFID 2nd spr (fast)
622 with m
.Case(MicrOp
.OP_RFID
):
623 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
624 comb
+= self
.fast_out
.ok
.eq(1)
629 class DecodeRC(Elaboratable
):
630 """DecodeRc from instruction
632 decodes Record bit Rc
635 def __init__(self
, dec
):
637 self
.sel_in
= Signal(RC
, reset_less
=True)
638 self
.insn_in
= Signal(32, reset_less
=True)
639 self
.rc_out
= Data(1, "rc")
641 def elaborate(self
, platform
):
645 # select Record bit out field
646 with m
.Switch(self
.sel_in
):
648 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
649 comb
+= self
.rc_out
.ok
.eq(1)
651 comb
+= self
.rc_out
.data
.eq(1)
652 comb
+= self
.rc_out
.ok
.eq(1)
653 with m
.Case(RC
.NONE
):
654 comb
+= self
.rc_out
.data
.eq(0)
655 comb
+= self
.rc_out
.ok
.eq(1)
660 class DecodeOE(Elaboratable
):
661 """DecodeOE from instruction
663 decodes OE field: uses RC decode detection which might not be good
665 -- For now, use "rc" in the decode table to decide whether oe exists.
666 -- This is not entirely correct architecturally: For mulhd and
667 -- mulhdu, the OE field is reserved. It remains to be seen what an
668 -- actual POWER9 does if we set it on those instructions, for now we
669 -- test that further down when assigning to the multiplier oe input.
672 def __init__(self
, dec
):
674 self
.sel_in
= Signal(RC
, reset_less
=True)
675 self
.insn_in
= Signal(32, reset_less
=True)
676 self
.oe_out
= Data(1, "oe")
678 def elaborate(self
, platform
):
683 with m
.Switch(op
.internal_op
):
685 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
687 # XXX ARGH! ignoring OE causes incompatibility with microwatt
688 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
689 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
690 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
691 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
692 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
693 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
697 # all other ops decode OE field
699 # select OE bit out field
700 with m
.Switch(self
.sel_in
):
702 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
703 comb
+= self
.oe_out
.ok
.eq(1)
708 class DecodeCRIn(Elaboratable
):
709 """Decodes input CR from instruction
711 CR indices - insn fields - (not the data *in* the CR) require only 3
712 bits because they refer to CR0-CR7
715 def __init__(self
, dec
):
717 self
.sv_rm
= SVP64Rec() # SVP64 RM field
718 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
719 self
.insn_in
= Signal(32, reset_less
=True)
720 self
.cr_bitfield
= Data(3, "cr_bitfield")
721 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
722 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
723 self
.cr_isvec
= Signal(1, name
="cr_isvec")
724 self
.cr_b_isvec
= Signal(1, name
="cr_b_isvec")
725 self
.cr_o_isvec
= Signal(1, name
="cr_o_isvec")
726 self
.whole_reg
= Data(8, "cr_fxm")
728 def elaborate(self
, platform
):
732 m
.submodules
.svdec
= svdec
= SVP64CRExtra()
733 m
.submodules
.svdec_b
= svdec_b
= SVP64CRExtra()
734 m
.submodules
.svdec_o
= svdec_o
= SVP64CRExtra()
735 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
739 # get the 3-bit reg data before svp64-munging it into 7-bit plus isvec
740 cr_bf
= Signal(3, reset_less
=True)
741 cr_bf_b
= Signal(3, reset_less
=True)
742 cr_bf_o
= Signal(3, reset_less
=True)
744 # index selection slightly different due to shared CR field sigh
745 cr_a_idx
= Signal(SVEXTRA
)
746 cr_b_idx
= Signal(SVEXTRA
)
748 # zero-initialisation
749 comb
+= self
.cr_bitfield
.ok
.eq(0)
750 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
751 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
752 comb
+= self
.whole_reg
.ok
.eq(0)
754 # these change slighly, when decoding BA/BB. really should have
755 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
756 comb
+= cr_a_idx
.eq(op
.sv_cr_in
)
757 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
758 with m
.If(op
.sv_cr_in
== SVEXTRA
.Idx_1_2
.value
):
759 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
760 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
762 # select the relevant CR bitfields
763 with m
.Switch(self
.sel_in
):
764 with m
.Case(CRInSel
.NONE
):
765 pass # No bitfield activated
766 with m
.Case(CRInSel
.CR0
):
767 comb
+= cr_bf
.eq(0) # CR0 (MSB0 numbering)
768 comb
+= self
.cr_bitfield
.ok
.eq(1)
769 with m
.Case(CRInSel
.BI
):
770 comb
+= cr_bf
.eq(self
.dec
.BI
[2:5])
771 comb
+= self
.cr_bitfield
.ok
.eq(1)
772 with m
.Case(CRInSel
.BFA
):
773 comb
+= cr_bf
.eq(self
.dec
.FormX
.BFA
)
774 comb
+= self
.cr_bitfield
.ok
.eq(1)
775 with m
.Case(CRInSel
.BA_BB
):
776 comb
+= cr_bf
.eq(self
.dec
.BA
[2:5])
777 comb
+= self
.cr_bitfield
.ok
.eq(1)
778 comb
+= cr_bf_b
.eq(self
.dec
.BB
[2:5])
779 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
780 comb
+= cr_bf_o
.eq(self
.dec
.BT
[2:5])
781 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
782 with m
.Case(CRInSel
.BC
):
783 comb
+= cr_bf
.eq(self
.dec
.BC
[2:5])
784 comb
+= self
.cr_bitfield
.ok
.eq(1)
785 with m
.Case(CRInSel
.WHOLE_REG
):
786 comb
+= self
.whole_reg
.ok
.eq(1)
787 move_one
= Signal(reset_less
=True)
788 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
789 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
790 # must one-hot the FXM field
791 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
792 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
794 # otherwise use all of it
795 comb
+= self
.whole_reg
.data
.eq(0xff)
797 # now do the SVP64 munging.
798 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
800 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
801 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
802 comb
+= svdec
.cr_in
.eq(cr_bf
) # 3-bit (BFA)
804 comb
+= svdec_b
.extra
.eq(extra
) # EXTRA field of SVP64 RM
805 comb
+= svdec_b
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
806 comb
+= svdec_b
.cr_in
.eq(cr_bf_b
) # 3-bit (BB[2:5])
808 comb
+= svdec_o
.extra
.eq(extra
) # EXTRA field of SVP64 RM
809 comb
+= svdec_o
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
810 comb
+= svdec_o
.cr_in
.eq(cr_bf_o
) # 3-bit (BT[2:5])
812 # indices are slightly different, BA/BB mess sorted above
813 comb
+= svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
814 comb
+= svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
815 comb
+= svdec_o
.idx
.eq(op
.sv_cr_out
) # SVP64 CR out
817 # outputs: 7-bit reg number and whether it's vectorised
818 comb
+= self
.cr_bitfield
.data
.eq(svdec
.cr_out
)
819 comb
+= self
.cr_isvec
.eq(svdec
.isvec
)
820 comb
+= self
.cr_bitfield_b
.data
.eq(svdec_b
.cr_out
)
821 comb
+= self
.cr_b_isvec
.eq(svdec_b
.isvec
)
822 comb
+= self
.cr_bitfield_o
.data
.eq(svdec_o
.cr_out
)
823 comb
+= self
.cr_o_isvec
.eq(svdec_o
.isvec
)
828 class DecodeCROut(Elaboratable
):
829 """Decodes input CR from instruction
831 CR indices - insn fields - (not the data *in* the CR) require only 3
832 bits because they refer to CR0-CR7
835 def __init__(self
, dec
):
837 self
.sv_rm
= SVP64Rec() # SVP64 RM field
838 self
.rc_in
= Signal(reset_less
=True)
839 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
840 self
.insn_in
= Signal(32, reset_less
=True)
841 self
.cr_bitfield
= Data(3, "cr_bitfield")
842 self
.whole_reg
= Data(8, "cr_fxm")
844 def elaborate(self
, platform
):
848 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
851 comb
+= self
.cr_bitfield
.ok
.eq(0)
852 comb
+= self
.whole_reg
.ok
.eq(0)
853 with m
.Switch(self
.sel_in
):
854 with m
.Case(CROutSel
.NONE
):
855 pass # No bitfield activated
856 with m
.Case(CROutSel
.CR0
):
857 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
858 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
859 with m
.Case(CROutSel
.BF
):
860 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
861 comb
+= self
.cr_bitfield
.ok
.eq(1)
862 with m
.Case(CROutSel
.BT
):
863 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
864 comb
+= self
.cr_bitfield
.ok
.eq(1)
865 with m
.Case(CROutSel
.WHOLE_REG
):
866 comb
+= self
.whole_reg
.ok
.eq(1)
867 move_one
= Signal(reset_less
=True)
868 comb
+= move_one
.eq(self
.insn_in
[20])
869 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
871 # must one-hot the FXM field
872 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
873 with m
.If(ppick
.en_o
):
874 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
876 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
878 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
880 # otherwise use all of it
881 comb
+= self
.whole_reg
.data
.eq(0xff)
885 # dictionary of Input Record field names that, if they exist,
886 # will need a corresponding CSV Decoder file column (actually, PowerOp)
887 # to be decoded (this includes the single bit names)
888 record_names
= {'insn_type': 'internal_op',
889 'fn_unit': 'function_unit',
893 'imm_data': 'in2_sel',
894 'invert_in': 'inv_a',
895 'invert_out': 'inv_out',
898 'output_carry': 'cry_out',
899 'input_carry': 'cry_in',
900 'is_32bit': 'is_32b',
903 'data_len': 'ldst_len',
904 'byte_reverse': 'br',
905 'sign_extend': 'sgn_ext',
910 class PowerDecodeSubset(Elaboratable
):
911 """PowerDecodeSubset: dynamic subset decoder
913 only fields actually requested are copied over. hence, "subset" (duh).
915 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
917 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
920 self
.fn_name
= fn_name
922 opkls
= Decode2ToOperand
923 self
.do
= opkls(fn_name
)
924 col_subset
= self
.get_col_subset(self
.do
)
926 # only needed for "main" PowerDecode2
928 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
)
930 # create decoder if one not already given
932 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
933 row_subset
=self
.rowsubsetfn
)
936 # state information needed by the Decoder
938 state
= CoreState("dec2")
941 def get_col_subset(self
, do
):
942 subset
= {'sv_cr_in', 'sv_cr_out', 'SV_Etype',
943 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
944 for k
, v
in record_names
.items():
947 print ("get_col_subset", self
.fn_name
, do
.fields
, subset
)
950 def rowsubsetfn(self
, opcode
, row
):
951 return row
['unit'] == self
.fn_name
954 return self
.dec
.ports() + self
.e
.ports() + self
.sv_rm
.ports()
956 def needs_field(self
, field
, op_field
):
961 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
963 def do_copy(self
, field
, val
, final
=False):
964 if final
or self
.final
:
968 if hasattr(do
, field
) and val
is not None:
969 return getattr(do
, field
).eq(val
)
972 def op_get(self
, op_field
):
973 return getattr(self
.dec
.op
, op_field
, None)
975 def elaborate(self
, platform
):
979 op
, do
= self
.dec
.op
, self
.do
980 msr
, cia
= state
.msr
, state
.pc
982 # fill in for a normal instruction (not an exception)
983 # copy over if non-exception, non-privileged etc. is detected
985 if self
.fn_name
is None:
988 name
= self
.fn_name
+ "tmp"
989 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
)
991 # set up submodule decoders
992 m
.submodules
.dec
= self
.dec
993 m
.submodules
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
994 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
995 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
)
996 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
)
998 # copy instruction through...
1000 dec_rc
.insn_in
, dec_oe
.insn_in
,
1001 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
]:
1002 comb
+= i
.eq(self
.dec
.opcode_in
)
1004 # ...and subdecoders' input fields
1005 comb
+= dec_rc
.sel_in
.eq(op
.rc_sel
)
1006 comb
+= dec_oe
.sel_in
.eq(op
.rc_sel
) # XXX should be OE sel
1007 comb
+= self
.dec_cr_in
.sel_in
.eq(op
.cr_in
)
1008 comb
+= self
.dec_cr_in
.sv_rm
.eq(self
.sv_rm
)
1009 comb
+= self
.dec_cr_out
.sv_rm
.eq(self
.sv_rm
)
1010 comb
+= self
.dec_cr_out
.sel_in
.eq(op
.cr_out
)
1011 comb
+= self
.dec_cr_out
.rc_in
.eq(dec_rc
.rc_out
.data
)
1014 comb
+= self
.do_copy("msr", msr
)
1015 comb
+= self
.do_copy("cia", cia
)
1017 # set up instruction type
1018 # no op: defaults to OP_ILLEGAL
1019 comb
+= self
.do_copy("insn_type", self
.op_get("internal_op"))
1021 # function unit for decoded instruction: requires minor redirect
1023 fn
= self
.op_get("function_unit")
1024 spr
= Signal(10, reset_less
=True)
1025 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
1027 # for first test only forward SPRs 18 and 19 to MMU, when
1028 # operation is MTSPR or MFSPR. TODO: add other MMU SPRs
1029 with m
.If(((self
.dec
.op
.internal_op
== MicrOp
.OP_MTSPR
) |
1030 (self
.dec
.op
.internal_op
== MicrOp
.OP_MFSPR
)) &
1031 ((spr
== SPR
.DSISR
) |
(spr
== SPR
.DAR
))):
1032 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
1034 comb
+= self
.do_copy("fn_unit",fn
)
1037 if self
.needs_field("zero_a", "in1_sel"):
1038 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
1039 comb
+= dec_ai
.sel_in
.eq(op
.in1_sel
)
1040 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
1041 if self
.needs_field("imm_data", "in2_sel"):
1042 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
1043 comb
+= dec_bi
.sel_in
.eq(op
.in2_sel
)
1044 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
1047 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
1048 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
1051 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1052 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1053 comb
+= self
.do_copy("write_cr0", self
.dec_cr_out
.cr_bitfield
.ok
)
1055 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
1056 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
1058 # decoded/selected instruction flags
1059 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
1060 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
1061 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
1062 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
1063 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
1064 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
1065 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
1066 lk
= self
.op_get("lk")
1069 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
1071 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
1072 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
1073 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
1078 class PowerDecode2(PowerDecodeSubset
):
1079 """PowerDecode2: the main instruction decoder.
1081 whilst PowerDecode is responsible for decoding the actual opcode, this
1082 module encapsulates further specialist, sparse information and
1083 expansion of fields that is inconvenient to have in the CSV files.
1084 for example: the encoding of the immediates, which are detected
1085 and expanded out to their full value from an annotated (enum)
1088 implicit register usage is also set up, here. for example: OP_BC
1089 requires implicitly reading CTR, OP_RFID requires implicitly writing
1092 in addition, PowerDecoder2 is responsible for detecting whether
1093 instructions are illegal (or privileged) or not, and instead of
1094 just leaving at that, *replacing* the instruction to execute with
1095 a suitable alternative (trap).
1097 LDSTExceptions are done the cycle _after_ they're detected (after
1098 they come out of LDSTCompUnit). basically despite the instruction
1099 being decoded, the results of the decode are completely ignored
1100 and "exception.happened" used to set the "actual" instruction to
1101 "OP_TRAP". the LDSTException data structure gets filled in,
1102 in the CompTrapOpSubset and that's what it fills in SRR.
1104 to make this work, TestIssuer must notice "exception.happened"
1105 after the (failed) LD/ST and copies the LDSTException info from
1106 the output, into here (PowerDecoder2). without incrementing PC.
1109 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
1110 super().__init
__(dec
, opkls
, fn_name
, final
, state
)
1111 self
.exc
= LDSTException("dec2_exc")
1113 def get_col_subset(self
, opkls
):
1114 subset
= super().get_col_subset(opkls
)
1115 subset
.add("asmcode")
1116 subset
.add("in1_sel")
1117 subset
.add("in2_sel")
1118 subset
.add("in3_sel")
1119 subset
.add("out_sel")
1120 subset
.add("sv_in1")
1121 subset
.add("sv_in2")
1122 subset
.add("sv_in3")
1123 subset
.add("sv_out")
1124 subset
.add("sv_cr_in")
1125 subset
.add("sv_cr_out")
1126 subset
.add("SV_Etype")
1127 subset
.add("SV_Ptype")
1129 subset
.add("internal_op")
1133 def elaborate(self
, platform
):
1134 m
= super().elaborate(platform
)
1137 e_out
, op
, do_out
= self
.e
, self
.dec
.op
, self
.e
.do
1138 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1142 # fill in for a normal instruction (not an exception)
1143 # copy over if non-exception, non-privileged etc. is detected
1145 # set up submodule decoders
1146 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
1147 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
1148 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
1149 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
1150 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
)
1152 # copy instruction through...
1153 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1154 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1155 comb
+= i
.eq(self
.dec
.opcode_in
)
1158 for i
in [dec_a
.insn_in
, dec_b
.insn_in
,
1159 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1160 comb
+= i
.eq(self
.sv_rm
)
1162 # ...and subdecoders' input fields
1163 comb
+= dec_a
.sel_in
.eq(op
.in1_sel
)
1164 comb
+= dec_b
.sel_in
.eq(op
.in2_sel
)
1165 comb
+= dec_c
.sel_in
.eq(op
.in3_sel
)
1166 comb
+= dec_o
.sel_in
.eq(op
.out_sel
)
1167 comb
+= dec_o2
.sel_in
.eq(op
.out_sel
)
1168 if hasattr(do
, "lk"):
1169 comb
+= dec_o2
.lk
.eq(do
.lk
)
1171 # registers a, b, c and out and out2 (LD/ST EA)
1172 for to_reg
, fromreg
in (
1173 (e
.read_reg1
, dec_a
.reg_out
),
1174 (e
.read_reg2
, dec_b
.reg_out
),
1175 (e
.read_reg3
, dec_c
.reg_out
),
1176 (e
.write_reg
, dec_o
.reg_out
),
1177 (e
.write_ea
, dec_o2
.reg_out
)):
1178 comb
+= to_reg
.data
.eq(fromreg
.data
)
1179 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1182 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1183 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1186 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1187 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1188 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
)
1189 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
)
1191 # condition registers (CR)
1192 for to_reg
, fromreg
in (
1193 (e
.read_cr1
, self
.dec_cr_in
.cr_bitfield
),
1194 (e
.read_cr2
, self
.dec_cr_in
.cr_bitfield_b
),
1195 (e
.read_cr3
, self
.dec_cr_in
.cr_bitfield_o
),
1196 (e
.write_cr
, self
.dec_cr_out
.cr_bitfield
)):
1197 comb
+= to_reg
.data
.eq(fromreg
.data
)
1198 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1200 # sigh this is exactly the sort of thing for which the
1201 # decoder is designed to not need. MTSPR, MFSPR and others need
1202 # access to the XER bits. however setting e.oe is not appropriate
1203 with m
.If(op
.internal_op
== MicrOp
.OP_MFSPR
):
1204 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1205 with m
.If(op
.internal_op
== MicrOp
.OP_CMP
):
1206 comb
+= e
.xer_in
.eq(1<<XERRegs
.SO
) # SO
1207 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
1208 comb
+= e
.xer_out
.eq(1)
1210 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1211 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1212 # *DO NOT* call self.trap here. that would reset absolutely
1213 # everything including destroying read of RA and RB.
1214 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1216 ####################
1217 # ok so the instruction's been decoded, blah blah, however
1218 # now we need to determine if it's actually going to go ahead...
1219 # *or* if in fact it's a privileged operation, whether there's
1220 # an external interrupt, etc. etc. this is a simple priority
1221 # if-elif-elif sequence. decrement takes highest priority,
1222 # EINT next highest, privileged operation third.
1224 # check if instruction is privileged
1225 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1227 # different IRQ conditions
1228 ext_irq_ok
= Signal()
1229 dec_irq_ok
= Signal()
1234 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1235 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1236 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1237 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1239 # LD/ST exceptions. TestIssuer copies the exception info at us
1240 # after a failed LD/ST.
1241 with m
.If(exc
.happened
):
1242 with m
.If(exc
.alignment
):
1243 self
.trap(m
, TT
.PRIV
, 0x600)
1244 with m
.Elif(exc
.instr_fault
):
1245 with m
.If(exc
.segment_fault
):
1246 self
.trap(m
, TT
.PRIV
, 0x480)
1248 # pass exception info to trap to create SRR1
1249 self
.trap(m
, TT
.MEMEXC
, 0x400, exc
)
1251 with m
.If(exc
.segment_fault
):
1252 self
.trap(m
, TT
.PRIV
, 0x380)
1254 self
.trap(m
, TT
.PRIV
, 0x300)
1256 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1257 with m
.Elif(dec_irq_ok
):
1258 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1260 # external interrupt? only if MSR.EE set
1261 with m
.Elif(ext_irq_ok
):
1262 self
.trap(m
, TT
.EINT
, 0x500)
1264 # privileged instruction trap
1265 with m
.Elif(priv_ok
):
1266 self
.trap(m
, TT
.PRIV
, 0x700)
1268 # illegal instruction must redirect to trap. this is done by
1269 # *overwriting* the decoded instruction and starting again.
1270 # (note: the same goes for interrupts and for privileged operations,
1271 # just with different trapaddr and traptype)
1272 with m
.Elif(illeg_ok
):
1273 # illegal instruction trap
1274 self
.trap(m
, TT
.ILLEG
, 0x700)
1276 # no exception, just copy things to the output
1280 ####################
1281 # follow-up after trap/irq to set up SRR0/1
1283 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1284 # Note: OP_SC could actually be modified to just be a trap
1285 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1286 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1287 # TRAP write fast1 = SRR0
1288 comb
+= e_out
.write_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1289 comb
+= e_out
.write_fast1
.ok
.eq(1)
1290 # TRAP write fast2 = SRR1
1291 comb
+= e_out
.write_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1292 comb
+= e_out
.write_fast2
.ok
.eq(1)
1294 # RFID: needs to read SRR0/1
1295 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1296 # TRAP read fast1 = SRR0
1297 comb
+= e_out
.read_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1298 comb
+= e_out
.read_fast1
.ok
.eq(1)
1299 # TRAP read fast2 = SRR1
1300 comb
+= e_out
.read_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1301 comb
+= e_out
.read_fast2
.ok
.eq(1)
1303 # annoying simulator bug
1304 if hasattr(e_out
, "asmcode") and hasattr(self
.dec
.op
, "asmcode"):
1305 comb
+= e_out
.asmcode
.eq(self
.dec
.op
.asmcode
)
1309 def trap(self
, m
, traptype
, trapaddr
, exc
=None):
1310 """trap: this basically "rewrites" the decoded instruction as a trap
1313 op
, e
= self
.dec
.op
, self
.e
1314 comb
+= e
.eq(0) # reset eeeeeverything
1317 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1318 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1319 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1320 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1321 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1322 comb
+= self
.do_copy("ldst_exc", exc
, True) # request type
1323 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # copy of MSR "state"
1324 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1327 def get_rdflags(e
, cu
):
1329 for idx
in range(cu
.n_src
):
1330 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1331 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
1333 print("rdflags", rdl
)
1337 if __name__
== '__main__':
1338 pdecode
= create_pdecode()
1339 dec2
= PowerDecode2(pdecode
)
1340 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1341 with
open("dec2.il", "w") as f
: