src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
   7 from nmigen.cli import rtlil
   8
   9 from nmutil.iocontrol import RecordObject
  10 from nmutil.extend import exts
  11
  12 from soc.decoder.power_regspec_map import regspec_decode
  13 from soc.decoder.power_decoder import create_pdecode
  14 from soc.decoder.power_enums import (InternalOp, CryIn, Function,
  15                                      CRInSel, CROutSel,
  16                                      LdstLen, In1Sel, In2Sel, In3Sel,
  17                                      OutSel, SPR, RC)
  18
  19 from soc.regfile.regfiles import FastRegs
  20
  21 class DecodeA(Elaboratable):
  22     """DecodeA from instruction
  23
  24     decodes register RA, whether immediate-zero, implicit and
  25     explicit CSRs
  26     """
  27
  28     def __init__(self, dec):
  29         self.dec = dec
  30         self.sel_in = Signal(In1Sel, reset_less=True)
  31         self.insn_in = Signal(32, reset_less=True)
  32         self.reg_out = Data(5, name="reg_a")
  33         self.immz_out = Signal(reset_less=True)
  34         self.spr_out = Data(10, "spr_a")
  35         self.fast_out = Data(3, "fast_a")
  36
  37     def elaborate(self, platform):
  38         m = Module()
  39         comb = m.d.comb
  40
  41         # select Register A field
  42         ra = Signal(5, reset_less=True)
  43         comb += ra.eq(self.dec.RA)
  44         with m.If((self.sel_in == In1Sel.RA) |
  45                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  46                    (ra != Const(0, 5)))):
  47             comb += self.reg_out.data.eq(ra)
  48             comb += self.reg_out.ok.eq(1)
  49
  50         # zero immediate requested
  51         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
  52                   (self.reg_out.data == Const(0, 5))):
  53             comb += self.immz_out.eq(1)
  54
  55         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
  56         with m.If(self.sel_in == In1Sel.RS):
  57             comb += self.reg_out.data.eq(self.dec.RS)
  58             comb += self.reg_out.ok.eq(1)
  59
  60         # decode Fast-SPR based on instruction type
  61         op = self.dec.op
  62         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
  63         with m.If((op.internal_op == InternalOp.OP_BC) |
  64                   (op.internal_op == InternalOp.OP_BCREG)):
  65             with m.If(~self.dec.BO[2] |        # 3.0B p38 BO2=0, use CTR reg
  66                        self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO
  67                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
  68                 comb += self.fast_out.ok.eq(1)
  69
  70         # MFSPR or MTSPR: move-from / move-to SPRs
  71         with m.If((op.internal_op == InternalOp.OP_MFSPR) |
  72                   (op.internal_op == InternalOp.OP_MTSPR)):
  73             # XXX TODO: fast/slow SPR decoding and mapping
  74             comb += self.spr_out.data.eq(self.dec.SPR) # SPR field, XFX
  75             comb += self.spr_out.ok.eq(1)
  76
  77         return m
  78
  79
  80 class Data(Record):
  81
  82     def __init__(self, width, name):
  83         name_ok = "%s_ok" % name
  84         layout = ((name, width), (name_ok, 1))
  85         Record.__init__(self, layout)
  86         self.data = getattr(self, name) # convenience
  87         self.ok = getattr(self, name_ok) # convenience
  88         self.data.reset_less = True # grrr
  89         self.reset_less = True # grrr
  90
  91     def ports(self):
  92         return [self.data, self.ok]
  93
  94
  95 class DecodeB(Elaboratable):
  96     """DecodeB from instruction
  97
  98     decodes register RB, different forms of immediate (signed, unsigned),
  99     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 100     by industry-standard convention, "lane 2" is where fully-decoded
 101     immediates are muxed in.
 102     """
 103
 104     def __init__(self, dec):
 105         self.dec = dec
 106         self.sel_in = Signal(In2Sel, reset_less=True)
 107         self.insn_in = Signal(32, reset_less=True)
 108         self.reg_out = Data(5, "reg_b")
 109         self.imm_out = Data(64, "imm_b")
 110         self.fast_out = Data(3, "fast_b")
 111
 112     def elaborate(self, platform):
 113         m = Module()
 114         comb = m.d.comb
 115
 116         # select Register B field
 117         with m.Switch(self.sel_in):
 118             with m.Case(In2Sel.RB):
 119                 comb += self.reg_out.data.eq(self.dec.RB)
 120                 comb += self.reg_out.ok.eq(1)
 121             with m.Case(In2Sel.RS):
 122                 comb += self.reg_out.data.eq(self.dec.RS) # for M-Form shiftrot
 123                 comb += self.reg_out.ok.eq(1)
 124             with m.Case(In2Sel.CONST_UI):
 125                 comb += self.imm_out.data.eq(self.dec.UI)
 126                 comb += self.imm_out.ok.eq(1)
 127             with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here?
 128                 comb += self.imm_out.data.eq(
 129                     exts(self.dec.SI, 16, 64))
 130                 comb += self.imm_out.ok.eq(1)
 131             with m.Case(In2Sel.CONST_UI_HI):
 132                 comb += self.imm_out.data.eq(self.dec.UI<<16)
 133                 comb += self.imm_out.ok.eq(1)
 134             with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here?
 135                 comb += self.imm_out.data.eq(self.dec.SI<<16)
 136                 comb += self.imm_out.data.eq(
 137                     exts(self.dec.SI << 16, 32, 64))
 138                 comb += self.imm_out.ok.eq(1)
 139             with m.Case(In2Sel.CONST_LI):
 140                 comb += self.imm_out.data.eq(self.dec.LI<<2)
 141                 comb += self.imm_out.ok.eq(1)
 142             with m.Case(In2Sel.CONST_BD):
 143                 comb += self.imm_out.data.eq(self.dec.BD<<2)
 144                 comb += self.imm_out.ok.eq(1)
 145             with m.Case(In2Sel.CONST_DS):
 146                 comb += self.imm_out.data.eq(self.dec.DS<<2)
 147                 comb += self.imm_out.ok.eq(1)
 148             with m.Case(In2Sel.CONST_M1):
 149                 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
 150                 comb += self.imm_out.ok.eq(1)
 151             with m.Case(In2Sel.CONST_SH):
 152                 comb += self.imm_out.data.eq(self.dec.sh)
 153                 comb += self.imm_out.ok.eq(1)
 154             with m.Case(In2Sel.CONST_SH32):
 155                 comb += self.imm_out.data.eq(self.dec.SH32)
 156                 comb += self.imm_out.ok.eq(1)
 157
 158         # decode SPR2 based on instruction type
 159         op = self.dec.op
 160         # BCREG implicitly uses LR or TAR for 2nd reg (TODO: TAR)
 161         # CTR however is already in fast_spr1 *not* 2.
 162         with m.If((op.internal_op == InternalOp.OP_BC) |
 163                  (op.internal_op == InternalOp.OP_BCREG)):
 164             with m.If(~self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO
 165                 comb += self.fast_out.data.eq(FastRegs.LR)
 166                 comb += self.fast_out.ok.eq(1)
 167
 168         return m
 169
 170
 171 class DecodeC(Elaboratable):
 172     """DecodeC from instruction
 173
 174     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 175     """
 176
 177     def __init__(self, dec):
 178         self.dec = dec
 179         self.sel_in = Signal(In3Sel, reset_less=True)
 180         self.insn_in = Signal(32, reset_less=True)
 181         self.reg_out = Data(5, "reg_c")
 182
 183     def elaborate(self, platform):
 184         m = Module()
 185         comb = m.d.comb
 186
 187         # select Register C field
 188         with m.Switch(self.sel_in):
 189             with m.Case(In3Sel.RB):
 190                 comb += self.reg_out.data.eq(self.dec.RB) # for M-Form shiftrot
 191                 comb += self.reg_out.ok.eq(1)
 192             with m.Case(In3Sel.RS):
 193                 comb += self.reg_out.data.eq(self.dec.RS)
 194                 comb += self.reg_out.ok.eq(1)
 195
 196         return m
 197
 198
 199 class DecodeOut(Elaboratable):
 200     """DecodeOut from instruction
 201
 202     decodes output register RA, RT or SPR
 203     """
 204
 205     def __init__(self, dec):
 206         self.dec = dec
 207         self.sel_in = Signal(OutSel, reset_less=True)
 208         self.insn_in = Signal(32, reset_less=True)
 209         self.reg_out = Data(5, "reg_o")
 210         self.spr_out = Data(10, "spr_o")
 211         self.fast_out = Data(3, "fast_o")
 212
 213     def elaborate(self, platform):
 214         m = Module()
 215         comb = m.d.comb
 216
 217         # select Register out field
 218         with m.Switch(self.sel_in):
 219             with m.Case(OutSel.RT):
 220                 comb += self.reg_out.data.eq(self.dec.RT)
 221                 comb += self.reg_out.ok.eq(1)
 222             with m.Case(OutSel.RA):
 223                 comb += self.reg_out.data.eq(self.dec.RA)
 224                 comb += self.reg_out.ok.eq(1)
 225             with m.Case(OutSel.SPR):
 226                 comb += self.spr_out.data.eq(self.dec.SPR) # from XFX
 227                 comb += self.spr_out.ok.eq(1)
 228
 229         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
 230         op = self.dec.op
 231         with m.If((op.internal_op == InternalOp.OP_BC) |
 232                   (op.internal_op == InternalOp.OP_BCREG)):
 233             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
 234                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
 235                 comb += self.fast_out.ok.eq(1)
 236         return m
 237
 238
 239 class DecodeOut2(Elaboratable):
 240     """DecodeOut2 from instruction
 241
 242     decodes output registers
 243     """
 244
 245     def __init__(self, dec):
 246         self.dec = dec
 247         self.sel_in = Signal(OutSel, reset_less=True)
 248         self.insn_in = Signal(32, reset_less=True)
 249         self.reg_out = Data(5, "reg_o")
 250         self.fast_out = Data(3, "fast_o")
 251
 252     def elaborate(self, platform):
 253         m = Module()
 254         comb = m.d.comb
 255
 256         # update mode LD/ST uses read-reg A also as an output
 257         with m.If(self.dec.op.upd):
 258             comb += self.reg_out.eq(self.dec.RA)
 259             comb += self.reg_out.ok.eq(1)
 260
 261         # BC or BCREG: potential implicit register (LR) output
 262         op = self.dec.op
 263         with m.If((op.internal_op == InternalOp.OP_BC) |
 264                   (op.internal_op == InternalOp.OP_BCREG)):
 265             with m.If(self.dec.op.lk & self.dec.LK): # "link" mode
 266                 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
 267                 comb += self.fast_out.ok.eq(1)
 268
 269         return m
 270
 271
 272 class DecodeRC(Elaboratable):
 273     """DecodeRc from instruction
 274
 275     decodes Record bit Rc
 276     """
 277     def __init__(self, dec):
 278         self.dec = dec
 279         self.sel_in = Signal(RC, reset_less=True)
 280         self.insn_in = Signal(32, reset_less=True)
 281         self.rc_out = Data(1, "rc")
 282
 283     def elaborate(self, platform):
 284         m = Module()
 285         comb = m.d.comb
 286
 287         # select Record bit out field
 288         with m.Switch(self.sel_in):
 289             with m.Case(RC.RC):
 290                 comb += self.rc_out.data.eq(self.dec.Rc)
 291                 comb += self.rc_out.ok.eq(1)
 292             with m.Case(RC.ONE):
 293                 comb += self.rc_out.data.eq(1)
 294                 comb += self.rc_out.ok.eq(1)
 295             with m.Case(RC.NONE):
 296                 comb += self.rc_out.data.eq(0)
 297                 comb += self.rc_out.ok.eq(1)
 298
 299         return m
 300
 301
 302 class DecodeOE(Elaboratable):
 303     """DecodeOE from instruction
 304
 305     decodes OE field: uses RC decode detection which might not be good
 306
 307     -- For now, use "rc" in the decode table to decide whether oe exists.
 308     -- This is not entirely correct architecturally: For mulhd and
 309     -- mulhdu, the OE field is reserved. It remains to be seen what an
 310     -- actual POWER9 does if we set it on those instructions, for now we
 311     -- test that further down when assigning to the multiplier oe input.
 312     """
 313     def __init__(self, dec):
 314         self.dec = dec
 315         self.sel_in = Signal(RC, reset_less=True)
 316         self.insn_in = Signal(32, reset_less=True)
 317         self.oe_out = Data(1, "oe")
 318
 319     def elaborate(self, platform):
 320         m = Module()
 321         comb = m.d.comb
 322
 323         # select OE bit out field
 324         with m.Switch(self.sel_in):
 325             with m.Case(RC.RC):
 326                 comb += self.oe_out.data.eq(self.dec.OE)
 327                 comb += self.oe_out.ok.eq(1)
 328
 329         return m
 330
 331 class DecodeCRIn(Elaboratable):
 332     """Decodes input CR from instruction
 333
 334     CR indices - insn fields - (not the data *in* the CR) require only 3
 335     bits because they refer to CR0-CR7
 336     """
 337
 338     def __init__(self, dec):
 339         self.dec = dec
 340         self.sel_in = Signal(CRInSel, reset_less=True)
 341         self.insn_in = Signal(32, reset_less=True)
 342         self.cr_bitfield = Data(3, "cr_bitfield")
 343         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 344         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 345         self.whole_reg = Signal(reset_less=True)
 346
 347     def elaborate(self, platform):
 348         m = Module()
 349         comb = m.d.comb
 350
 351         comb += self.cr_bitfield.ok.eq(0)
 352         comb += self.cr_bitfield_b.ok.eq(0)
 353         comb += self.whole_reg.eq(0)
 354         with m.Switch(self.sel_in):
 355             with m.Case(CRInSel.NONE):
 356                 pass # No bitfield activated
 357             with m.Case(CRInSel.CR0):
 358                 comb += self.cr_bitfield.data.eq(0)
 359                 comb += self.cr_bitfield.ok.eq(1)
 360             with m.Case(CRInSel.BI):
 361                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 362                 comb += self.cr_bitfield.ok.eq(1)
 363             with m.Case(CRInSel.BFA):
 364                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 365                 comb += self.cr_bitfield.ok.eq(1)
 366             with m.Case(CRInSel.BA_BB):
 367                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 368                 comb += self.cr_bitfield.ok.eq(1)
 369                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 370                 comb += self.cr_bitfield_b.ok.eq(1)
 371                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 372                 comb += self.cr_bitfield_o.ok.eq(1)
 373             with m.Case(CRInSel.BC):
 374                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 375                 comb += self.cr_bitfield.ok.eq(1)
 376             with m.Case(CRInSel.WHOLE_REG):
 377                 comb += self.whole_reg.eq(1)
 378
 379         return m
 380
 381
 382 class DecodeCROut(Elaboratable):
 383     """Decodes input CR from instruction
 384
 385     CR indices - insn fields - (not the data *in* the CR) require only 3
 386     bits because they refer to CR0-CR7
 387     """
 388
 389     def __init__(self, dec):
 390         self.dec = dec
 391         self.rc_in = Signal(reset_less=True)
 392         self.sel_in = Signal(CROutSel, reset_less=True)
 393         self.insn_in = Signal(32, reset_less=True)
 394         self.cr_bitfield = Data(3, "cr_bitfield")
 395         self.whole_reg = Signal(reset_less=True)
 396
 397     def elaborate(self, platform):
 398         m = Module()
 399         comb = m.d.comb
 400
 401         comb += self.cr_bitfield.ok.eq(0)
 402         comb += self.whole_reg.eq(0)
 403         with m.Switch(self.sel_in):
 404             with m.Case(CROutSel.NONE):
 405                 pass # No bitfield activated
 406             with m.Case(CROutSel.CR0):
 407                 comb += self.cr_bitfield.data.eq(0)
 408                 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
 409             with m.Case(CROutSel.BF):
 410                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF[0:-1])
 411                 comb += self.cr_bitfield.ok.eq(1)
 412             with m.Case(CROutSel.BT):
 413                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 414                 comb += self.cr_bitfield.ok.eq(1)
 415             with m.Case(CROutSel.WHOLE_REG):
 416                 comb += self.whole_reg.eq(1)
 417
 418         return m
 419
 420
 421 class XerBits:
 422     def __init__(self):
 423         self.ca = Signal(2, reset_less=True)
 424         self.ov = Signal(2, reset_less=True)
 425         self.so = Signal(reset_less=True)
 426
 427     def ports(self):
 428         return [self.ca, self.ov, self.so]
 429
 430
 431 class Decode2ToExecute1Type(RecordObject):
 432
 433     def __init__(self, name=None):
 434
 435         RecordObject.__init__(self, name=name)
 436
 437         self.valid = Signal(reset_less=True)
 438         self.insn_type = Signal(InternalOp, reset_less=True)
 439         self.fn_unit = Signal(Function, reset_less=True)
 440         self.nia = Signal(64, reset_less=True)
 441         self.write_reg = Data(5, name="rego")
 442         self.write_ea = Data(5, name="ea") # for LD/ST in update mode
 443         self.read_reg1 = Data(5, name="reg1")
 444         self.read_reg2 = Data(5, name="reg2")
 445         self.read_reg3 = Data(5, name="reg3")
 446         self.imm_data = Data(64, name="imm")
 447         self.write_spr = Data(10, name="spro")
 448         self.read_spr1 = Data(10, name="spr1")
 449         self.read_spr2 = Data(10, name="spr2")
 450
 451         self.read_fast1 = Data(3, name="fast1")
 452         self.read_fast2 = Data(3, name="fast2")
 453         self.write_fast1 = Data(3, name="fasto1")
 454         self.write_fast2 = Data(3, name="fasto2")
 455
 456         self.read_cr1 = Data(3, name="cr_in1")
 457         self.read_cr2 = Data(3, name="cr_in2")
 458         self.read_cr3 = Data(3, name="cr_in2")
 459         self.read_cr_whole = Signal(reset_less=True)
 460         self.write_cr = Data(3, name="cr_out")
 461         self.write_cr_whole = Signal(reset_less=True)
 462         self.lk = Signal(reset_less=True)
 463         self.rc = Data(1, "rc")
 464         self.oe = Data(1, "oe")
 465         self.invert_a = Signal(reset_less=True)
 466         self.zero_a = Signal(reset_less=True)
 467         self.invert_out = Signal(reset_less=True)
 468         self.input_carry = Signal(CryIn, reset_less=True)
 469         self.output_carry = Signal(reset_less=True)
 470         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
 471         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
 472         self.is_32bit = Signal(reset_less=True)
 473         self.is_signed = Signal(reset_less=True)
 474         self.insn = Signal(32, reset_less=True)
 475         self.data_len = Signal(4, reset_less=True) # bytes
 476         self.byte_reverse  = Signal(reset_less=True)
 477         self.sign_extend  = Signal(reset_less=True)# do we need this?
 478         self.update  = Signal(reset_less=True) # LD/ST is "update" variant
 479
 480
 481 class PowerDecode2(Elaboratable):
 482
 483     def __init__(self, dec):
 484
 485         self.dec = dec
 486         self.e = Decode2ToExecute1Type()
 487
 488     def ports(self):
 489         return self.dec.ports() + self.e.ports()
 490
 491     def elaborate(self, platform):
 492         m = Module()
 493         comb = m.d.comb
 494
 495         # set up submodule decoders
 496         m.submodules.dec = self.dec
 497         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 498         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 499         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 500         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 501         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
 502         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 503         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 504         m.submodules.dec_cr_in = dec_cr_in = DecodeCRIn(self.dec)
 505         m.submodules.dec_cr_out = dec_cr_out = DecodeCROut(self.dec)
 506
 507         # copy instruction through...
 508         for i in [self.e.insn, dec_a.insn_in, dec_b.insn_in,
 509                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in, dec_rc.insn_in,
 510                   dec_oe.insn_in, dec_cr_in.insn_in, dec_cr_out.insn_in]:
 511             comb += i.eq(self.dec.opcode_in)
 512
 513         # ...and subdecoders' input fields
 514         comb += dec_a.sel_in.eq(self.dec.op.in1_sel)
 515         comb += dec_b.sel_in.eq(self.dec.op.in2_sel)
 516         comb += dec_c.sel_in.eq(self.dec.op.in3_sel)
 517         comb += dec_o.sel_in.eq(self.dec.op.out_sel)
 518         comb += dec_o2.sel_in.eq(self.dec.op.out_sel)
 519         comb += dec_rc.sel_in.eq(self.dec.op.rc_sel)
 520         comb += dec_oe.sel_in.eq(self.dec.op.rc_sel) # XXX should be OE sel
 521         comb += dec_cr_in.sel_in.eq(self.dec.op.cr_in)
 522         comb += dec_cr_out.sel_in.eq(self.dec.op.cr_out)
 523         comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
 524
 525         # decode LD/ST length
 526         with m.Switch(self.dec.op.ldst_len):
 527             with m.Case(LdstLen.is1B):
 528                 comb += self.e.data_len.eq(1)
 529             with m.Case(LdstLen.is2B):
 530                 comb += self.e.data_len.eq(2)
 531             with m.Case(LdstLen.is4B):
 532                 comb += self.e.data_len.eq(4)
 533             with m.Case(LdstLen.is8B):
 534                 comb += self.e.data_len.eq(8)
 535
 536         comb += self.e.nia.eq(0)    # XXX TODO
 537         comb += self.e.valid.eq(0)  # XXX TODO
 538         fu = self.dec.op.function_unit
 539         itype = Mux(fu == Function.NONE,
 540                     InternalOp.OP_ILLEGAL,
 541                     self.dec.op.internal_op)
 542         comb += self.e.insn_type.eq(itype)
 543         comb += self.e.fn_unit.eq(fu)
 544
 545         # registers a, b, c and out and out2 (LD/ST EA)
 546         comb += self.e.read_reg1.eq(dec_a.reg_out)
 547         comb += self.e.read_reg2.eq(dec_b.reg_out)
 548         comb += self.e.read_reg3.eq(dec_c.reg_out)
 549         comb += self.e.write_reg.eq(dec_o.reg_out)
 550         comb += self.e.write_ea.eq(dec_o2.reg_out)
 551         comb += self.e.imm_data.eq(dec_b.imm_out) # immediate in RB (usually)
 552         comb += self.e.zero_a.eq(dec_a.immz_out)  # RA==0 detected
 553
 554         # rc and oe out
 555         comb += self.e.rc.eq(dec_rc.rc_out)
 556         comb += self.e.oe.eq(dec_oe.oe_out)
 557
 558         # SPRs out
 559         comb += self.e.read_spr1.eq(dec_a.spr_out)
 560         comb += self.e.write_spr.eq(dec_o.spr_out)
 561
 562         # Fast regs out
 563         comb += self.e.read_fast1.eq(dec_a.fast_out)
 564         comb += self.e.read_fast2.eq(dec_b.fast_out)
 565         comb += self.e.write_fast1.eq(dec_o.fast_out)
 566         comb += self.e.write_fast2.eq(dec_o2.fast_out)
 567
 568         comb += self.e.read_cr1.eq(dec_cr_in.cr_bitfield)
 569         comb += self.e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
 570         comb += self.e.read_cr3.eq(dec_cr_in.cr_bitfield_o)
 571         comb += self.e.read_cr_whole.eq(dec_cr_in.whole_reg)
 572
 573         comb += self.e.write_cr.eq(dec_cr_out.cr_bitfield)
 574         comb += self.e.write_cr_whole.eq(dec_cr_out.whole_reg)
 575
 576         # decoded/selected instruction flags
 577         comb += self.e.invert_a.eq(self.dec.op.inv_a)
 578         comb += self.e.invert_out.eq(self.dec.op.inv_out)
 579         comb += self.e.input_carry.eq(self.dec.op.cry_in)   # carry comes in
 580         comb += self.e.output_carry.eq(self.dec.op.cry_out) # carry goes out
 581         comb += self.e.is_32bit.eq(self.dec.op.is_32b)
 582         comb += self.e.is_signed.eq(self.dec.op.sgn)
 583         with m.If(self.dec.op.lk):
 584             comb += self.e.lk.eq(self.dec.LK) # XXX TODO: accessor
 585
 586         comb += self.e.byte_reverse.eq(self.dec.op.br)
 587         comb += self.e.sign_extend.eq(self.dec.op.sgn_ext)
 588         comb += self.e.update.eq(self.dec.op.upd) # LD/ST "update" mode.
 589
 590
 591         # These should be removed eventually
 592         comb += self.e.input_cr.eq(self.dec.op.cr_in)   # condition reg comes in
 593         comb += self.e.output_cr.eq(self.dec.op.cr_out) # condition reg goes in
 594
 595
 596         return m
 597
 598     def regspecmap(self, regfile, regname):
 599         """regspecmap: provides PowerDecode2 with an encoding relationship
 600         to Function Unit port regfiles (read-enable, read regnum, write regnum)
 601         regfile and regname arguments are fields 1 and 2 from a given regspec.
 602         """
 603         return regspec_decode(self, regfile, regname)
 604
 605
 606 if __name__ == '__main__':
 607     pdecode = create_pdecode()
 608     dec2 = PowerDecode2(pdecode)
 609     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 610     with open("dec2.il", "w") as f:
 611         f.write(vl)
 612