1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
6 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
7 from nmigen
.cli
import rtlil
9 from nmutil
.iocontrol
import RecordObject
10 from nmutil
.extend
import exts
12 from soc
.decoder
.power_regspec_map
import regspec_decode_read
13 from soc
.decoder
.power_regspec_map
import regspec_decode_write
14 from soc
.decoder
.power_decoder
import create_pdecode
15 from soc
.decoder
.power_enums
import (InternalOp
, CryIn
, Function
,
17 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
19 from soc
.decoder
.decode2execute1
import Decode2ToExecute1Type
, Data
21 from soc
.regfile
.regfiles
import FastRegs
23 # see traptype (and trap main_stage.py)
31 def instr_is_priv(m
, op
, insn
):
32 """determines if the instruction is privileged or not
35 Signal
= is_priv_insn(reset_less
=True)
37 with m
.Case(InternalOp
.OP_ATTN
) : comb
+= is_priv_insn
.eq(1)
38 with m
.Case(InternalOp
.OP_MFMSR
) : comb
+= is_priv_insn
.eq(1)
39 with m
.Case(InternalOp
.OP_MTMSRD
): comb
+= is_priv_insn
.eq(1)
40 with m
.Case(InternalOp
.OP_RFID
) : comb
+= is_priv_insn
.eq(1)
41 with m
.Case(InternalOp
.OP_TLBIE
) : comb
+= is_priv_insn
.eq(1)
42 with m
.If(op
== OP_MFSPR | op
== OP_MTSPR
):
43 with m
.If(insn
[20]): # field XFX.spr[-1] i think
44 comb
+= is_priv_insn
.eq(1)
48 class DecodeA(Elaboratable
):
49 """DecodeA from instruction
51 decodes register RA, whether immediate-zero, implicit and
55 def __init__(self
, dec
):
57 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
58 self
.insn_in
= Signal(32, reset_less
=True)
59 self
.reg_out
= Data(5, name
="reg_a")
60 self
.immz_out
= Signal(reset_less
=True)
61 self
.spr_out
= Data(10, "spr_a")
62 self
.fast_out
= Data(3, "fast_a")
64 def elaborate(self
, platform
):
68 # select Register A field
69 ra
= Signal(5, reset_less
=True)
70 comb
+= ra
.eq(self
.dec
.RA
)
71 with m
.If((self
.sel_in
== In1Sel
.RA
) |
72 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
73 (ra
!= Const(0, 5)))):
74 comb
+= self
.reg_out
.data
.eq(ra
)
75 comb
+= self
.reg_out
.ok
.eq(1)
77 # zero immediate requested
78 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
79 (self
.reg_out
.data
== Const(0, 5))):
80 comb
+= self
.immz_out
.eq(1)
82 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
83 with m
.If(self
.sel_in
== In1Sel
.RS
):
84 comb
+= self
.reg_out
.data
.eq(self
.dec
.RS
)
85 comb
+= self
.reg_out
.ok
.eq(1)
87 # decode Fast-SPR based on instruction type
89 # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
90 with m
.If(op
.internal_op
== InternalOp
.OP_BC
):
91 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
92 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
) # constant: CTR
93 comb
+= self
.fast_out
.ok
.eq(1)
94 with m
.Elif(op
.internal_op
== InternalOp
.OP_BCREG
):
95 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
96 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
97 with m
.If(xo9
& ~xo5
):
98 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
) # constant: CTR
99 comb
+= self
.fast_out
.ok
.eq(1)
101 # MFSPR move from SPRs
102 with m
.If(op
.internal_op
== InternalOp
.OP_MFSPR
):
103 # XXX TODO: fast/slow SPR decoding and mapping
104 comb
+= self
.spr_out
.data
.eq(self
.dec
.SPR
) # SPR field, XFX
105 comb
+= self
.spr_out
.ok
.eq(1)
110 class DecodeB(Elaboratable
):
111 """DecodeB from instruction
113 decodes register RB, different forms of immediate (signed, unsigned),
114 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
115 by industry-standard convention, "lane 2" is where fully-decoded
116 immediates are muxed in.
119 def __init__(self
, dec
):
121 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
122 self
.insn_in
= Signal(32, reset_less
=True)
123 self
.reg_out
= Data(5, "reg_b")
124 self
.imm_out
= Data(64, "imm_b")
125 self
.fast_out
= Data(3, "fast_b")
127 def elaborate(self
, platform
):
131 # select Register B field
132 with m
.Switch(self
.sel_in
):
133 with m
.Case(In2Sel
.RB
):
134 comb
+= self
.reg_out
.data
.eq(self
.dec
.RB
)
135 comb
+= self
.reg_out
.ok
.eq(1)
136 with m
.Case(In2Sel
.RS
):
137 comb
+= self
.reg_out
.data
.eq(self
.dec
.RS
) # for M-Form shiftrot
138 comb
+= self
.reg_out
.ok
.eq(1)
139 with m
.Case(In2Sel
.CONST_UI
):
140 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
141 comb
+= self
.imm_out
.ok
.eq(1)
142 with m
.Case(In2Sel
.CONST_SI
): # TODO: sign-extend here?
143 comb
+= self
.imm_out
.data
.eq(
144 exts(self
.dec
.SI
, 16, 64))
145 comb
+= self
.imm_out
.ok
.eq(1)
146 with m
.Case(In2Sel
.CONST_UI_HI
):
147 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
<<16)
148 comb
+= self
.imm_out
.ok
.eq(1)
149 with m
.Case(In2Sel
.CONST_SI_HI
): # TODO: sign-extend here?
150 comb
+= self
.imm_out
.data
.eq(self
.dec
.SI
<<16)
151 comb
+= self
.imm_out
.data
.eq(
152 exts(self
.dec
.SI
<< 16, 32, 64))
153 comb
+= self
.imm_out
.ok
.eq(1)
154 with m
.Case(In2Sel
.CONST_LI
):
155 comb
+= self
.imm_out
.data
.eq(self
.dec
.LI
<<2)
156 comb
+= self
.imm_out
.ok
.eq(1)
157 with m
.Case(In2Sel
.CONST_BD
):
158 comb
+= self
.imm_out
.data
.eq(self
.dec
.BD
<<2)
159 comb
+= self
.imm_out
.ok
.eq(1)
160 with m
.Case(In2Sel
.CONST_DS
):
161 comb
+= self
.imm_out
.data
.eq(self
.dec
.DS
<<2)
162 comb
+= self
.imm_out
.ok
.eq(1)
163 with m
.Case(In2Sel
.CONST_M1
):
164 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
165 comb
+= self
.imm_out
.ok
.eq(1)
166 with m
.Case(In2Sel
.CONST_SH
):
167 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
168 comb
+= self
.imm_out
.ok
.eq(1)
169 with m
.Case(In2Sel
.CONST_SH32
):
170 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
171 comb
+= self
.imm_out
.ok
.eq(1)
173 # decode SPR2 based on instruction type
175 # BCREG implicitly uses LR or TAR for 2nd reg
176 # CTR however is already in fast_spr1 *not* 2.
177 with m
.If(op
.internal_op
== InternalOp
.OP_BCREG
):
178 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
179 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
181 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
182 comb
+= self
.fast_out
.ok
.eq(1)
184 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
185 comb
+= self
.fast_out
.ok
.eq(1)
190 class DecodeC(Elaboratable
):
191 """DecodeC from instruction
193 decodes register RC. this is "lane 3" into some CompUnits (not many)
196 def __init__(self
, dec
):
198 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
199 self
.insn_in
= Signal(32, reset_less
=True)
200 self
.reg_out
= Data(5, "reg_c")
202 def elaborate(self
, platform
):
206 # select Register C field
207 with m
.Switch(self
.sel_in
):
208 with m
.Case(In3Sel
.RB
):
209 comb
+= self
.reg_out
.data
.eq(self
.dec
.RB
) # for M-Form shiftrot
210 comb
+= self
.reg_out
.ok
.eq(1)
211 with m
.Case(In3Sel
.RS
):
212 comb
+= self
.reg_out
.data
.eq(self
.dec
.RS
)
213 comb
+= self
.reg_out
.ok
.eq(1)
218 class DecodeOut(Elaboratable
):
219 """DecodeOut from instruction
221 decodes output register RA, RT or SPR
224 def __init__(self
, dec
):
226 self
.sel_in
= Signal(OutSel
, reset_less
=True)
227 self
.insn_in
= Signal(32, reset_less
=True)
228 self
.reg_out
= Data(5, "reg_o")
229 self
.spr_out
= Data(10, "spr_o")
230 self
.fast_out
= Data(3, "fast_o")
232 def elaborate(self
, platform
):
237 # select Register out field
238 with m
.Switch(self
.sel_in
):
239 with m
.Case(OutSel
.RT
):
240 comb
+= self
.reg_out
.data
.eq(self
.dec
.RT
)
241 comb
+= self
.reg_out
.ok
.eq(1)
242 with m
.Case(OutSel
.RA
):
243 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
244 comb
+= self
.reg_out
.ok
.eq(1)
245 with m
.Case(OutSel
.SPR
):
246 comb
+= self
.spr_out
.data
.eq(self
.dec
.SPR
) # from XFX
247 comb
+= self
.spr_out
.ok
.eq(1)
248 # TODO MTSPR 1st spr (fast)
249 with m
.If(op
.internal_op
== InternalOp
.OP_MTSPR
):
252 sprn := decode_spr_num(f_in.insn);
253 v.ispr1 := fast_spr_num(sprn);
254 -- Make slow SPRs single issue
255 if is_fast_spr(v.ispr1) = '0' then
256 v.decode.sgl_pipe := '1';
257 -- send MMU-related SPRs to loadstore1
259 when SPR_DAR | SPR_DSISR | SPR_PID | SPR_PRTBL =>
260 v.decode.unit := LDST;
267 # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
269 with m
.If((op
.internal_op
== InternalOp
.OP_BC
) |
270 (op
.internal_op
== InternalOp
.OP_BCREG
)):
271 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
272 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
) # constant: CTR
273 comb
+= self
.fast_out
.ok
.eq(1)
275 # RFID 1st spr (fast)
276 with m
.If(op
.internal_op
== InternalOp
.OP_RFID
):
277 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
278 comb
+= self
.fast_out
.ok
.eq(1)
283 class DecodeOut2(Elaboratable
):
284 """DecodeOut2 from instruction
286 decodes output registers
289 def __init__(self
, dec
):
291 self
.sel_in
= Signal(OutSel
, reset_less
=True)
292 self
.lk
= Signal(reset_less
=True)
293 self
.insn_in
= Signal(32, reset_less
=True)
294 self
.reg_out
= Data(5, "reg_o")
295 self
.fast_out
= Data(3, "fast_o")
297 def elaborate(self
, platform
):
301 # update mode LD/ST uses read-reg A also as an output
302 with m
.If(self
.dec
.op
.upd
):
303 comb
+= self
.reg_out
.eq(self
.dec
.RA
)
304 comb
+= self
.reg_out
.ok
.eq(1)
306 # BC or BCREG: potential implicit register (LR) output
308 with m
.If((op
.internal_op
== InternalOp
.OP_BC
) |
309 (op
.internal_op
== InternalOp
.OP_BCREG
)):
310 with m
.If(self
.lk
): # "link" mode
311 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
) # constant: LR
312 comb
+= self
.fast_out
.ok
.eq(1)
314 # RFID 2nd spr (fast)
315 with m
.If(op
.internal_op
== InternalOp
.OP_RFID
):
316 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
317 comb
+= self
.fast_out
.ok
.eq(1)
322 class DecodeRC(Elaboratable
):
323 """DecodeRc from instruction
325 decodes Record bit Rc
327 def __init__(self
, dec
):
329 self
.sel_in
= Signal(RC
, reset_less
=True)
330 self
.insn_in
= Signal(32, reset_less
=True)
331 self
.rc_out
= Data(1, "rc")
333 def elaborate(self
, platform
):
337 # select Record bit out field
338 with m
.Switch(self
.sel_in
):
340 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
341 comb
+= self
.rc_out
.ok
.eq(1)
343 comb
+= self
.rc_out
.data
.eq(1)
344 comb
+= self
.rc_out
.ok
.eq(1)
345 with m
.Case(RC
.NONE
):
346 comb
+= self
.rc_out
.data
.eq(0)
347 comb
+= self
.rc_out
.ok
.eq(1)
352 class DecodeOE(Elaboratable
):
353 """DecodeOE from instruction
355 decodes OE field: uses RC decode detection which might not be good
357 -- For now, use "rc" in the decode table to decide whether oe exists.
358 -- This is not entirely correct architecturally: For mulhd and
359 -- mulhdu, the OE field is reserved. It remains to be seen what an
360 -- actual POWER9 does if we set it on those instructions, for now we
361 -- test that further down when assigning to the multiplier oe input.
363 def __init__(self
, dec
):
365 self
.sel_in
= Signal(RC
, reset_less
=True)
366 self
.insn_in
= Signal(32, reset_less
=True)
367 self
.oe_out
= Data(1, "oe")
369 def elaborate(self
, platform
):
373 # select OE bit out field
374 with m
.Switch(self
.sel_in
):
376 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
377 comb
+= self
.oe_out
.ok
.eq(1)
381 class DecodeCRIn(Elaboratable
):
382 """Decodes input CR from instruction
384 CR indices - insn fields - (not the data *in* the CR) require only 3
385 bits because they refer to CR0-CR7
388 def __init__(self
, dec
):
390 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
391 self
.insn_in
= Signal(32, reset_less
=True)
392 self
.cr_bitfield
= Data(3, "cr_bitfield")
393 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
394 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
395 self
.whole_reg
= Signal(reset_less
=True)
397 def elaborate(self
, platform
):
401 comb
+= self
.cr_bitfield
.ok
.eq(0)
402 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
403 comb
+= self
.whole_reg
.eq(0)
404 with m
.Switch(self
.sel_in
):
405 with m
.Case(CRInSel
.NONE
):
406 pass # No bitfield activated
407 with m
.Case(CRInSel
.CR0
):
408 comb
+= self
.cr_bitfield
.data
.eq(0)
409 comb
+= self
.cr_bitfield
.ok
.eq(1)
410 with m
.Case(CRInSel
.BI
):
411 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
412 comb
+= self
.cr_bitfield
.ok
.eq(1)
413 with m
.Case(CRInSel
.BFA
):
414 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
415 comb
+= self
.cr_bitfield
.ok
.eq(1)
416 with m
.Case(CRInSel
.BA_BB
):
417 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
418 comb
+= self
.cr_bitfield
.ok
.eq(1)
419 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
420 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
421 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
422 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
423 with m
.Case(CRInSel
.BC
):
424 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
425 comb
+= self
.cr_bitfield
.ok
.eq(1)
426 with m
.Case(CRInSel
.WHOLE_REG
):
427 comb
+= self
.whole_reg
.eq(1)
432 class DecodeCROut(Elaboratable
):
433 """Decodes input CR from instruction
435 CR indices - insn fields - (not the data *in* the CR) require only 3
436 bits because they refer to CR0-CR7
439 def __init__(self
, dec
):
441 self
.rc_in
= Signal(reset_less
=True)
442 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
443 self
.insn_in
= Signal(32, reset_less
=True)
444 self
.cr_bitfield
= Data(3, "cr_bitfield")
445 self
.whole_reg
= Signal(reset_less
=True)
447 def elaborate(self
, platform
):
451 comb
+= self
.cr_bitfield
.ok
.eq(0)
452 comb
+= self
.whole_reg
.eq(0)
453 with m
.Switch(self
.sel_in
):
454 with m
.Case(CROutSel
.NONE
):
455 pass # No bitfield activated
456 with m
.Case(CROutSel
.CR0
):
457 comb
+= self
.cr_bitfield
.data
.eq(0)
458 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
459 with m
.Case(CROutSel
.BF
):
460 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
461 comb
+= self
.cr_bitfield
.ok
.eq(1)
462 with m
.Case(CROutSel
.BT
):
463 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
464 comb
+= self
.cr_bitfield
.ok
.eq(1)
465 with m
.Case(CROutSel
.WHOLE_REG
):
466 comb
+= self
.whole_reg
.eq(1)
473 self
.ca
= Signal(2, reset_less
=True)
474 self
.ov
= Signal(2, reset_less
=True)
475 self
.so
= Signal(reset_less
=True)
478 return [self
.ca
, self
.ov
, self
.so
]
481 class PowerDecode2(Elaboratable
):
483 def __init__(self
, dec
):
486 self
.e
= Decode2ToExecute1Type()
489 return self
.dec
.ports() + self
.e
.ports()
491 def elaborate(self
, platform
):
494 e
, op
= self
.e
, self
.dec
.op
496 # set up submodule decoders
497 m
.submodules
.dec
= self
.dec
498 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
499 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
500 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
501 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
502 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
)
503 m
.submodules
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
504 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
505 m
.submodules
.dec_cr_in
= dec_cr_in
= DecodeCRIn(self
.dec
)
506 m
.submodules
.dec_cr_out
= dec_cr_out
= DecodeCROut(self
.dec
)
508 # copy instruction through...
509 for i
in [e
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
510 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
, dec_rc
.insn_in
,
511 dec_oe
.insn_in
, dec_cr_in
.insn_in
, dec_cr_out
.insn_in
]:
512 comb
+= i
.eq(self
.dec
.opcode_in
)
514 # ...and subdecoders' input fields
515 comb
+= dec_a
.sel_in
.eq(op
.in1_sel
)
516 comb
+= dec_b
.sel_in
.eq(op
.in2_sel
)
517 comb
+= dec_c
.sel_in
.eq(op
.in3_sel
)
518 comb
+= dec_o
.sel_in
.eq(op
.out_sel
)
519 comb
+= dec_o2
.sel_in
.eq(op
.out_sel
)
520 comb
+= dec_o2
.lk
.eq(e
.lk
)
521 comb
+= dec_rc
.sel_in
.eq(op
.rc_sel
)
522 comb
+= dec_oe
.sel_in
.eq(op
.rc_sel
) # XXX should be OE sel
523 comb
+= dec_cr_in
.sel_in
.eq(op
.cr_in
)
524 comb
+= dec_cr_out
.sel_in
.eq(op
.cr_out
)
525 comb
+= dec_cr_out
.rc_in
.eq(dec_rc
.rc_out
.data
)
528 comb
+= e
.nia
.eq(0) # XXX TODO (or remove? not sure yet)
529 fu
= op
.function_unit
530 itype
= Mux(fu
== Function
.NONE
, InternalOp
.OP_ILLEGAL
, op
.internal_op
)
531 comb
+= e
.insn_type
.eq(itype
)
532 comb
+= e
.fn_unit
.eq(fu
)
534 # registers a, b, c and out and out2 (LD/ST EA)
535 comb
+= e
.read_reg1
.eq(dec_a
.reg_out
)
536 comb
+= e
.read_reg2
.eq(dec_b
.reg_out
)
537 comb
+= e
.read_reg3
.eq(dec_c
.reg_out
)
538 comb
+= e
.write_reg
.eq(dec_o
.reg_out
)
539 comb
+= e
.write_ea
.eq(dec_o2
.reg_out
)
540 comb
+= e
.imm_data
.eq(dec_b
.imm_out
) # immediate in RB (usually)
541 comb
+= e
.zero_a
.eq(dec_a
.immz_out
) # RA==0 detected
544 comb
+= e
.rc
.eq(dec_rc
.rc_out
)
545 comb
+= e
.oe
.eq(dec_oe
.oe_out
)
548 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
549 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
552 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
553 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
554 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
)
555 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
)
557 comb
+= e
.read_cr1
.eq(dec_cr_in
.cr_bitfield
)
558 comb
+= e
.read_cr2
.eq(dec_cr_in
.cr_bitfield_b
)
559 comb
+= e
.read_cr3
.eq(dec_cr_in
.cr_bitfield_o
)
560 comb
+= e
.read_cr_whole
.eq(dec_cr_in
.whole_reg
)
562 comb
+= e
.write_cr
.eq(dec_cr_out
.cr_bitfield
)
563 comb
+= e
.write_cr_whole
.eq(dec_cr_out
.whole_reg
)
565 # decoded/selected instruction flags
566 comb
+= e
.data_len
.eq(op
.ldst_len
)
567 comb
+= e
.invert_a
.eq(op
.inv_a
)
568 comb
+= e
.invert_out
.eq(op
.inv_out
)
569 comb
+= e
.input_carry
.eq(op
.cry_in
) # carry comes in
570 comb
+= e
.output_carry
.eq(op
.cry_out
) # carry goes out
571 comb
+= e
.is_32bit
.eq(op
.is_32b
)
572 comb
+= e
.is_signed
.eq(op
.sgn
)
574 comb
+= e
.lk
.eq(self
.dec
.LK
) # XXX TODO: accessor
576 comb
+= e
.byte_reverse
.eq(op
.br
)
577 comb
+= e
.sign_extend
.eq(op
.sgn_ext
)
578 comb
+= e
.update
.eq(op
.upd
) # LD/ST "update" mode.
581 # These should be removed eventually
582 comb
+= e
.input_cr
.eq(op
.cr_in
) # condition reg comes in
583 comb
+= e
.output_cr
.eq(op
.cr_out
) # condition reg goes in
586 with m
.If(op
.internal_op
== InternalOp
.OP_TRAP
):
587 comb
+= e
.trapaddr
.eq(0x70) # addr=0x700 (strip first nibble)
591 # privileged instruction
592 with m
.If(instr_is_priv(m
, op
.internal_op
, e
.insn
) & msr
[MSR_PR
]):
593 # don't request registers RA/RT
594 comb
+= e
.read_reg1
.eq(0)
595 comb
+= e
.read_reg2
.eq(0)
596 comb
+= e
.read_reg3
.eq(0)
597 comb
+= e
.write_reg
.eq(0)
598 comb
+= e
.write_ea
.eq(0)
599 # privileged instruction trap
600 comb
+= op
.internal_op
.eq(InternalOp
.OP_TRAP
)
601 comb
+= e
.traptype
.eq(TT_PRIV
) # request privileged instruction
602 comb
+= e
.trapaddr
.eq(0x70) # addr=0x700 (strip first nibble)
605 def regspecmap_read(self
, regfile
, regname
):
606 """regspecmap_read: provides PowerDecode2 with an encoding relationship
607 to Function Unit port regfiles (read-enable, read regnum, write regnum)
608 regfile and regname arguments are fields 1 and 2 from a given regspec.
610 return regspec_decode_read(self
.e
, regfile
, regname
)
612 def regspecmap_write(self
, regfile
, regname
):
613 """regspecmap_write: provides PowerDecode2 with an encoding relationship
614 to Function Unit port regfiles (write port, write regnum)
615 regfile and regname arguments are fields 1 and 2 from a given regspec.
617 return regspec_decode_write(self
.e
, regfile
, regname
)
619 def rdflags(self
, cu
):
621 for idx
in range(cu
.n_src
):
622 regfile
, regname
, _
= cu
.get_in_spec(idx
)
623 rdflag
, read
= self
.regspecmap_read(regfile
, regname
)
625 print ("rdflags", rdl
)
629 if __name__
== '__main__':
630 pdecode
= create_pdecode()
631 dec2
= PowerDecode2(pdecode
)
632 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
633 with
open("dec2.il", "w") as f
: