1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from nmutil
.util
import sel
13 from soc
.regfile
.regfiles
import XERRegs
15 from nmutil
.picker
import PriorityPicker
16 from nmutil
.iocontrol
import RecordObject
17 from nmutil
.extend
import exts
19 from soc
.experiment
.mem_types
import LDSTException
21 from soc
.decoder
.power_svp64_prefix
import SVP64PrefixDecoder
22 from soc
.decoder
.power_svp64_extra
import SVP64CRExtra
, SVP64RegExtra
23 from soc
.decoder
.power_regspec_map
import regspec_decode_read
24 from soc
.decoder
.power_regspec_map
import regspec_decode_write
25 from soc
.decoder
.power_decoder
import create_pdecode
26 from soc
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
28 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
29 OutSel
, SPR
, RC
, LDSTMode
,
30 SVEXTRA
, SVEtype
, SVPtype
)
31 from soc
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
33 from soc
.sv
.svp64
import SVP64Rec
34 from soc
.consts
import (MSR
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
, field
,
35 SPEC_SIZE
, SPECb
, SPEC_AUG_SIZE
, SVP64CROffs
)
37 from soc
.regfile
.regfiles
import FastRegs
38 from soc
.consts
import TT
39 from soc
.config
.state
import CoreState
40 from soc
.regfile
.util
import spr_to_fast
43 def decode_spr_num(spr
):
44 return Cat(spr
[5:10], spr
[0:5])
47 def instr_is_priv(m
, op
, insn
):
48 """determines if the instruction is privileged or not
51 is_priv_insn
= Signal(reset_less
=True)
53 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
54 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
55 comb
+= is_priv_insn
.eq(1)
56 with m
.Case(MicrOp
.OP_TLBIE
) : comb
+= is_priv_insn
.eq(1)
57 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
58 with m
.If(insn
[20]): # field XFX.spr[-1] i think
59 comb
+= is_priv_insn
.eq(1)
63 class SPRMap(Elaboratable
):
64 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
68 self
.spr_i
= Signal(10, reset_less
=True)
69 self
.spr_o
= Data(SPR
, name
="spr_o")
70 self
.fast_o
= Data(3, name
="fast_o")
72 def elaborate(self
, platform
):
74 with m
.Switch(self
.spr_i
):
75 for i
, x
in enumerate(SPR
):
77 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
78 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
79 for x
, v
in spr_to_fast
.items():
81 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
82 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
86 class DecodeA(Elaboratable
):
87 """DecodeA from instruction
89 decodes register RA, implicit and explicit CSRs
92 def __init__(self
, dec
):
94 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
95 self
.insn_in
= Signal(32, reset_less
=True)
96 self
.reg_out
= Data(5, name
="reg_a")
97 self
.spr_out
= Data(SPR
, "spr_a")
98 self
.fast_out
= Data(3, "fast_a")
99 self
.sv_nz
= Signal(1)
101 def elaborate(self
, platform
):
106 m
.submodules
.sprmap
= sprmap
= SPRMap()
108 # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
109 ra
= Signal(5, reset_less
=True)
110 comb
+= ra
.eq(self
.dec
.RA
)
111 with m
.If((self
.sel_in
== In1Sel
.RA
) |
112 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
113 ((ra
!= Const(0, 5)) |
(self
.sv_nz
!= Const(0, 1))))):
114 comb
+= reg
.data
.eq(ra
)
117 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
118 # moved it to 1st position (in1_sel)... because
119 rs
= Signal(5, reset_less
=True)
120 comb
+= rs
.eq(self
.dec
.RS
)
121 with m
.If(self
.sel_in
== In1Sel
.RS
):
122 comb
+= reg
.data
.eq(rs
)
125 # decode Fast-SPR based on instruction type
126 with m
.Switch(op
.internal_op
):
128 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
129 with m
.Case(MicrOp
.OP_BC
):
130 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
132 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
133 comb
+= self
.fast_out
.ok
.eq(1)
134 with m
.Case(MicrOp
.OP_BCREG
):
135 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
136 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
137 with m
.If(xo9
& ~xo5
):
139 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
140 comb
+= self
.fast_out
.ok
.eq(1)
142 # MFSPR move from SPRs
143 with m
.Case(MicrOp
.OP_MFSPR
):
144 spr
= Signal(10, reset_less
=True)
145 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
146 comb
+= sprmap
.spr_i
.eq(spr
)
147 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
148 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
153 class DecodeAImm(Elaboratable
):
154 """DecodeA immediate from instruction
156 decodes register RA, whether immediate-zero, implicit and
157 explicit CSRs. SVP64 mode requires 2 extra bits
160 def __init__(self
, dec
):
162 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
163 self
.immz_out
= Signal(reset_less
=True)
164 self
.sv_nz
= Signal(1) # EXTRA bits from SVP64
166 def elaborate(self
, platform
):
170 # zero immediate requested
171 ra
= Signal(5, reset_less
=True)
172 comb
+= ra
.eq(self
.dec
.RA
)
173 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
174 (ra
== Const(0, 5)) &
175 (self
.sv_nz
== Const(0, 1))):
176 comb
+= self
.immz_out
.eq(1)
181 class DecodeB(Elaboratable
):
182 """DecodeB from instruction
184 decodes register RB, different forms of immediate (signed, unsigned),
185 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
186 by industry-standard convention, "lane 2" is where fully-decoded
187 immediates are muxed in.
190 def __init__(self
, dec
):
192 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
193 self
.insn_in
= Signal(32, reset_less
=True)
194 self
.reg_out
= Data(7, "reg_b")
195 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
196 self
.fast_out
= Data(3, "fast_b")
198 def elaborate(self
, platform
):
204 # select Register B field
205 with m
.Switch(self
.sel_in
):
206 with m
.Case(In2Sel
.RB
):
207 comb
+= reg
.data
.eq(self
.dec
.RB
)
209 with m
.Case(In2Sel
.RS
):
210 # for M-Form shiftrot
211 comb
+= reg
.data
.eq(self
.dec
.RS
)
214 # decode SPR2 based on instruction type
215 # BCREG implicitly uses LR or TAR for 2nd reg
216 # CTR however is already in fast_spr1 *not* 2.
217 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
218 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
219 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
221 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
222 comb
+= self
.fast_out
.ok
.eq(1)
224 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
225 comb
+= self
.fast_out
.ok
.eq(1)
230 class DecodeBImm(Elaboratable
):
231 """DecodeB immediate from instruction
233 def __init__(self
, dec
):
235 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
236 self
.imm_out
= Data(64, "imm_b")
238 def elaborate(self
, platform
):
242 # select Register B Immediate
243 with m
.Switch(self
.sel_in
):
244 with m
.Case(In2Sel
.CONST_UI
): # unsigned
245 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
246 comb
+= self
.imm_out
.ok
.eq(1)
247 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
248 si
= Signal(16, reset_less
=True)
249 comb
+= si
.eq(self
.dec
.SI
)
250 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
251 comb
+= self
.imm_out
.ok
.eq(1)
252 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
253 si_hi
= Signal(32, reset_less
=True)
254 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
255 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
256 comb
+= self
.imm_out
.ok
.eq(1)
257 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
258 ui
= Signal(16, reset_less
=True)
259 comb
+= ui
.eq(self
.dec
.UI
)
260 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
261 comb
+= self
.imm_out
.ok
.eq(1)
262 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
263 li
= Signal(26, reset_less
=True)
264 comb
+= li
.eq(self
.dec
.LI
<< 2)
265 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
266 comb
+= self
.imm_out
.ok
.eq(1)
267 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
268 bd
= Signal(16, reset_less
=True)
269 comb
+= bd
.eq(self
.dec
.BD
<< 2)
270 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
271 comb
+= self
.imm_out
.ok
.eq(1)
272 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
273 ds
= Signal(16, reset_less
=True)
274 comb
+= ds
.eq(self
.dec
.DS
<< 2)
275 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
276 comb
+= self
.imm_out
.ok
.eq(1)
277 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
278 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
279 comb
+= self
.imm_out
.ok
.eq(1)
280 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
281 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
282 comb
+= self
.imm_out
.ok
.eq(1)
283 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
284 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
285 comb
+= self
.imm_out
.ok
.eq(1)
290 class DecodeC(Elaboratable
):
291 """DecodeC from instruction
293 decodes register RC. this is "lane 3" into some CompUnits (not many)
296 def __init__(self
, dec
):
298 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
299 self
.insn_in
= Signal(32, reset_less
=True)
300 self
.reg_out
= Data(5, "reg_c")
302 def elaborate(self
, platform
):
308 # select Register C field
309 with m
.Switch(self
.sel_in
):
310 with m
.Case(In3Sel
.RB
):
311 # for M-Form shiftrot
312 comb
+= reg
.data
.eq(self
.dec
.RB
)
314 with m
.Case(In3Sel
.RS
):
315 comb
+= reg
.data
.eq(self
.dec
.RS
)
321 class DecodeOut(Elaboratable
):
322 """DecodeOut from instruction
324 decodes output register RA, RT or SPR
327 def __init__(self
, dec
):
329 self
.sel_in
= Signal(OutSel
, reset_less
=True)
330 self
.insn_in
= Signal(32, reset_less
=True)
331 self
.reg_out
= Data(5, "reg_o")
332 self
.spr_out
= Data(SPR
, "spr_o")
333 self
.fast_out
= Data(3, "fast_o")
335 def elaborate(self
, platform
):
338 m
.submodules
.sprmap
= sprmap
= SPRMap()
342 # select Register out field
343 with m
.Switch(self
.sel_in
):
344 with m
.Case(OutSel
.RT
):
345 comb
+= reg
.data
.eq(self
.dec
.RT
)
347 with m
.Case(OutSel
.RA
):
348 comb
+= reg
.data
.eq(self
.dec
.RA
)
350 with m
.Case(OutSel
.SPR
):
351 spr
= Signal(10, reset_less
=True)
352 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
353 # MFSPR move to SPRs - needs mapping
354 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
355 comb
+= sprmap
.spr_i
.eq(spr
)
356 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
357 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
360 with m
.Switch(op
.internal_op
):
362 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
363 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
364 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
366 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
367 comb
+= self
.fast_out
.ok
.eq(1)
369 # RFID 1st spr (fast)
370 with m
.Case(MicrOp
.OP_RFID
):
371 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
372 comb
+= self
.fast_out
.ok
.eq(1)
377 class DecodeOut2(Elaboratable
):
378 """DecodeOut2 from instruction
380 decodes output registers (2nd one). note that RA is *implicit* below,
381 which now causes problems with SVP64
383 TODO: SVP64 is a little more complex, here. svp64 allows extending
384 by one more destination by having one more EXTRA field. RA-as-src
385 is not the same as RA-as-dest. limited in that it's the same first
386 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
387 for operations that have src-as-dest: mostly this is LD/ST-with-update
388 but there are others.
391 def __init__(self
, dec
):
393 self
.sel_in
= Signal(OutSel
, reset_less
=True)
394 self
.lk
= Signal(reset_less
=True)
395 self
.insn_in
= Signal(32, reset_less
=True)
396 self
.reg_out
= Data(5, "reg_o2")
397 self
.fast_out
= Data(3, "fast_o2")
399 def elaborate(self
, platform
):
403 #m.submodules.svdec = svdec = SVP64RegExtra()
405 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
406 #reg = Signal(5, reset_less=True)
408 if hasattr(self
.dec
.op
, "upd"):
409 # update mode LD/ST uses read-reg A also as an output
410 with m
.If(self
.dec
.op
.upd
== LDSTMode
.update
):
411 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
412 comb
+= self
.reg_out
.ok
.eq(1)
414 # B, BC or BCREG: potential implicit register (LR) output
415 # these give bl, bcl, bclrl, etc.
416 with m
.Switch(op
.internal_op
):
418 # BC* implicit register (LR)
419 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
420 with m
.If(self
.lk
): # "link" mode
421 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
) # constant: LR
422 comb
+= self
.fast_out
.ok
.eq(1)
424 # RFID 2nd spr (fast)
425 with m
.Case(MicrOp
.OP_RFID
):
426 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
427 comb
+= self
.fast_out
.ok
.eq(1)
432 class DecodeRC(Elaboratable
):
433 """DecodeRc from instruction
435 decodes Record bit Rc
438 def __init__(self
, dec
):
440 self
.sel_in
= Signal(RC
, reset_less
=True)
441 self
.insn_in
= Signal(32, reset_less
=True)
442 self
.rc_out
= Data(1, "rc")
444 def elaborate(self
, platform
):
448 # select Record bit out field
449 with m
.Switch(self
.sel_in
):
451 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
452 comb
+= self
.rc_out
.ok
.eq(1)
454 comb
+= self
.rc_out
.data
.eq(1)
455 comb
+= self
.rc_out
.ok
.eq(1)
456 with m
.Case(RC
.NONE
):
457 comb
+= self
.rc_out
.data
.eq(0)
458 comb
+= self
.rc_out
.ok
.eq(1)
463 class DecodeOE(Elaboratable
):
464 """DecodeOE from instruction
466 decodes OE field: uses RC decode detection which might not be good
468 -- For now, use "rc" in the decode table to decide whether oe exists.
469 -- This is not entirely correct architecturally: For mulhd and
470 -- mulhdu, the OE field is reserved. It remains to be seen what an
471 -- actual POWER9 does if we set it on those instructions, for now we
472 -- test that further down when assigning to the multiplier oe input.
475 def __init__(self
, dec
):
477 self
.sel_in
= Signal(RC
, reset_less
=True)
478 self
.insn_in
= Signal(32, reset_less
=True)
479 self
.oe_out
= Data(1, "oe")
481 def elaborate(self
, platform
):
486 with m
.Switch(op
.internal_op
):
488 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
490 # XXX ARGH! ignoring OE causes incompatibility with microwatt
491 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
492 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
493 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
494 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
495 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
496 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
500 # all other ops decode OE field
502 # select OE bit out field
503 with m
.Switch(self
.sel_in
):
505 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
506 comb
+= self
.oe_out
.ok
.eq(1)
511 class DecodeCRIn(Elaboratable
):
512 """Decodes input CR from instruction
514 CR indices - insn fields - (not the data *in* the CR) require only 3
515 bits because they refer to CR0-CR7
518 def __init__(self
, dec
):
520 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
521 self
.insn_in
= Signal(32, reset_less
=True)
522 self
.cr_bitfield
= Data(3, "cr_bitfield")
523 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
524 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
525 self
.whole_reg
= Data(8, "cr_fxm")
526 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
528 def elaborate(self
, platform
):
532 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
535 # zero-initialisation
536 comb
+= self
.cr_bitfield
.ok
.eq(0)
537 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
538 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
539 comb
+= self
.whole_reg
.ok
.eq(0)
540 comb
+= self
.sv_override
.eq(0)
542 # select the relevant CR bitfields
543 with m
.Switch(self
.sel_in
):
544 with m
.Case(CRInSel
.NONE
):
545 pass # No bitfield activated
546 with m
.Case(CRInSel
.CR0
):
547 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
548 comb
+= self
.cr_bitfield
.ok
.eq(1)
549 comb
+= self
.sv_override
.eq(1)
550 with m
.Case(CRInSel
.CR1
):
551 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
552 comb
+= self
.cr_bitfield
.ok
.eq(1)
553 comb
+= self
.sv_override
.eq(2)
554 with m
.Case(CRInSel
.BI
):
555 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
556 comb
+= self
.cr_bitfield
.ok
.eq(1)
557 with m
.Case(CRInSel
.BFA
):
558 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
559 comb
+= self
.cr_bitfield
.ok
.eq(1)
560 with m
.Case(CRInSel
.BA_BB
):
561 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
562 comb
+= self
.cr_bitfield
.ok
.eq(1)
563 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
564 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
565 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
566 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
567 with m
.Case(CRInSel
.BC
):
568 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
569 comb
+= self
.cr_bitfield
.ok
.eq(1)
570 with m
.Case(CRInSel
.WHOLE_REG
):
571 comb
+= self
.whole_reg
.ok
.eq(1)
572 move_one
= Signal(reset_less
=True)
573 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
574 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
575 # must one-hot the FXM field
576 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
577 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
579 # otherwise use all of it
580 comb
+= self
.whole_reg
.data
.eq(0xff)
585 class DecodeCROut(Elaboratable
):
586 """Decodes input CR from instruction
588 CR indices - insn fields - (not the data *in* the CR) require only 3
589 bits because they refer to CR0-CR7
592 def __init__(self
, dec
):
594 self
.rc_in
= Signal(reset_less
=True)
595 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
596 self
.insn_in
= Signal(32, reset_less
=True)
597 self
.cr_bitfield
= Data(3, "cr_bitfield")
598 self
.whole_reg
= Data(8, "cr_fxm")
599 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
601 def elaborate(self
, platform
):
605 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
608 comb
+= self
.cr_bitfield
.ok
.eq(0)
609 comb
+= self
.whole_reg
.ok
.eq(0)
610 comb
+= self
.sv_override
.eq(0)
612 # please note these MUST match (setting of cr_bitfield.ok) exactly
613 # with write_cr0 below in PowerDecoder2. the reason it's separated
614 # is to avoid having duplicate copies of DecodeCROut in multiple
615 # PowerDecoderSubsets. register decoding should be a one-off in
616 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
618 with m
.Switch(self
.sel_in
):
619 with m
.Case(CROutSel
.NONE
):
620 pass # No bitfield activated
621 with m
.Case(CROutSel
.CR0
):
622 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
623 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
624 comb
+= self
.sv_override
.eq(1)
625 with m
.Case(CROutSel
.CR1
):
626 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
627 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
628 comb
+= self
.sv_override
.eq(2)
629 with m
.Case(CROutSel
.BF
):
630 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
631 comb
+= self
.cr_bitfield
.ok
.eq(1)
632 with m
.Case(CROutSel
.BT
):
633 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
634 comb
+= self
.cr_bitfield
.ok
.eq(1)
635 with m
.Case(CROutSel
.WHOLE_REG
):
636 comb
+= self
.whole_reg
.ok
.eq(1)
637 move_one
= Signal(reset_less
=True)
638 comb
+= move_one
.eq(self
.insn_in
[20])
639 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
641 # must one-hot the FXM field
642 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
643 with m
.If(ppick
.en_o
):
644 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
646 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
648 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
650 # otherwise use all of it
651 comb
+= self
.whole_reg
.data
.eq(0xff)
655 # dictionary of Input Record field names that, if they exist,
656 # will need a corresponding CSV Decoder file column (actually, PowerOp)
657 # to be decoded (this includes the single bit names)
658 record_names
= {'insn_type': 'internal_op',
659 'fn_unit': 'function_unit',
663 'imm_data': 'in2_sel',
664 'invert_in': 'inv_a',
665 'invert_out': 'inv_out',
668 'output_carry': 'cry_out',
669 'input_carry': 'cry_in',
670 'is_32bit': 'is_32b',
673 'data_len': 'ldst_len',
674 'byte_reverse': 'br',
675 'sign_extend': 'sgn_ext',
680 class PowerDecodeSubset(Elaboratable
):
681 """PowerDecodeSubset: dynamic subset decoder
683 only fields actually requested are copied over. hence, "subset" (duh).
685 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None,
688 self
.svp64_en
= svp64_en
690 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
691 self
.sv_a_nz
= Signal(1)
694 self
.fn_name
= fn_name
696 opkls
= Decode2ToOperand
697 self
.do
= opkls(fn_name
)
698 col_subset
= self
.get_col_subset(self
.do
)
700 # only needed for "main" PowerDecode2
702 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
)
704 # create decoder if one not already given
706 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
707 row_subset
=self
.rowsubsetfn
)
710 # state information needed by the Decoder
712 state
= CoreState("dec2")
715 def get_col_subset(self
, do
):
716 subset
= { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
717 for k
, v
in record_names
.items():
720 print ("get_col_subset", self
.fn_name
, do
.fields
, subset
)
723 def rowsubsetfn(self
, opcode
, row
):
724 """select per-Function-Unit subset of opcodes to be processed
726 normally this just looks at the "unit" column. MMU is different
727 in that it processes specific SPR set/get operations that the SPR
730 return (row
['unit'] == self
.fn_name
or
731 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
732 # by the MMU pipeline so we direct those opcodes to MMU **AND**
733 # SPR pipelines, then selectively weed out the SPRs that should
734 # or should not not go to each pipeline, further down.
735 # really this should be done by modifying the CSV syntax
736 # to support multiple tasks (unit column multiple entries)
737 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
738 (self
.fn_name
== 'MMU' and row
['unit'] == 'SPR' and
739 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
743 ports
= self
.dec
.ports() + self
.e
.ports()
745 ports
+= self
.sv_rm
.ports()
748 def needs_field(self
, field
, op_field
):
753 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
755 def do_copy(self
, field
, val
, final
=False):
756 if final
or self
.final
:
760 if hasattr(do
, field
) and val
is not None:
761 return getattr(do
, field
).eq(val
)
764 def op_get(self
, op_field
):
765 return getattr(self
.dec
.op
, op_field
, None)
767 def elaborate(self
, platform
):
771 op
, do
= self
.dec
.op
, self
.do
772 msr
, cia
= state
.msr
, state
.pc
773 # fill in for a normal instruction (not an exception)
774 # copy over if non-exception, non-privileged etc. is detected
776 if self
.fn_name
is None:
779 name
= self
.fn_name
+ "tmp"
780 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
)
782 # set up submodule decoders
783 m
.submodules
.dec
= self
.dec
784 m
.submodules
.dec_rc
= self
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
785 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
787 # copy instruction through...
788 for i
in [do
.insn
, dec_rc
.insn_in
, dec_oe
.insn_in
, ]:
789 comb
+= i
.eq(self
.dec
.opcode_in
)
791 # ...and subdecoders' input fields
792 comb
+= dec_rc
.sel_in
.eq(op
.rc_sel
)
793 comb
+= dec_oe
.sel_in
.eq(op
.rc_sel
) # XXX should be OE sel
796 comb
+= self
.do_copy("msr", msr
)
797 comb
+= self
.do_copy("cia", cia
)
799 # set up instruction type
800 # no op: defaults to OP_ILLEGAL
801 internal_op
= self
.op_get("internal_op")
802 comb
+= self
.do_copy("insn_type", internal_op
)
804 # function unit for decoded instruction: requires minor redirect
806 fn
= self
.op_get("function_unit")
807 spr
= Signal(10, reset_less
=True)
808 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
810 # Microwatt doesn't implement the partition table
811 # instead has PRTBL register (SPR) to point to process table
813 is_mmu_spr
= Signal()
814 comb
+= is_spr_mv
.eq((internal_op
== MicrOp
.OP_MTSPR
) |
815 (internal_op
== MicrOp
.OP_MFSPR
))
816 comb
+= is_mmu_spr
.eq((spr
== SPR
.DSISR
.value
) |
817 (spr
== SPR
.DAR
.value
) |
818 (spr
== SPR
.PRTBL
.value
) |
819 (spr
== SPR
.PIDR
.value
))
820 # MMU must receive MMU SPRs
821 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_mmu_spr
):
822 comb
+= self
.do_copy("fn_unit", Function
.NONE
)
823 comb
+= self
.do_copy("insn_type", MicrOp
.OP_ILLEGAL
)
824 # SPR pipe must *not* receive MMU SPRs
825 with m
.Elif(is_spr_mv
& (fn
== Function
.MMU
) & ~is_mmu_spr
):
826 comb
+= self
.do_copy("fn_unit", Function
.NONE
)
827 comb
+= self
.do_copy("insn_type", MicrOp
.OP_ILLEGAL
)
830 comb
+= self
.do_copy("fn_unit", fn
)
833 if self
.needs_field("zero_a", "in1_sel"):
834 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
835 comb
+= dec_ai
.sv_nz
.eq(self
.sv_a_nz
)
836 comb
+= dec_ai
.sel_in
.eq(op
.in1_sel
)
837 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
838 if self
.needs_field("imm_data", "in2_sel"):
839 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
840 comb
+= dec_bi
.sel_in
.eq(op
.in2_sel
)
841 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
844 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
845 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
847 # CR in/out - note: these MUST match with what happens in
849 rc_out
= self
.dec_rc
.rc_out
.data
850 with m
.Switch(op
.cr_out
):
851 with m
.Case(CROutSel
.CR0
, CROutSel
.CR1
):
852 comb
+= self
.do_copy("write_cr0", rc_out
) # only when RC=1
853 with m
.Case(CROutSel
.BF
, CROutSel
.BT
):
854 comb
+= self
.do_copy("write_cr0", 1)
856 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
857 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
859 # decoded/selected instruction flags
860 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
861 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
862 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
863 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
864 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
865 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
866 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
867 lk
= self
.op_get("lk")
870 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
872 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
873 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
874 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
879 class PowerDecode2(PowerDecodeSubset
):
880 """PowerDecode2: the main instruction decoder.
882 whilst PowerDecode is responsible for decoding the actual opcode, this
883 module encapsulates further specialist, sparse information and
884 expansion of fields that is inconvenient to have in the CSV files.
885 for example: the encoding of the immediates, which are detected
886 and expanded out to their full value from an annotated (enum)
889 implicit register usage is also set up, here. for example: OP_BC
890 requires implicitly reading CTR, OP_RFID requires implicitly writing
893 in addition, PowerDecoder2 is responsible for detecting whether
894 instructions are illegal (or privileged) or not, and instead of
895 just leaving at that, *replacing* the instruction to execute with
896 a suitable alternative (trap).
898 LDSTExceptions are done the cycle _after_ they're detected (after
899 they come out of LDSTCompUnit). basically despite the instruction
900 being decoded, the results of the decode are completely ignored
901 and "exception.happened" used to set the "actual" instruction to
902 "OP_TRAP". the LDSTException data structure gets filled in,
903 in the CompTrapOpSubset and that's what it fills in SRR.
905 to make this work, TestIssuer must notice "exception.happened"
906 after the (failed) LD/ST and copies the LDSTException info from
907 the output, into here (PowerDecoder2). without incrementing PC.
910 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False,
911 state
=None, svp64_en
=True):
912 super().__init
__(dec
, opkls
, fn_name
, final
, state
, svp64_en
)
913 self
.exc
= LDSTException("dec2_exc")
916 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
917 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
918 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
919 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
920 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
921 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
922 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
923 self
.o_isvec
= Signal(1, name
="reg_o_isvec")
924 self
.o2_isvec
= Signal(1, name
="reg_o2_isvec")
925 self
.no_in_vec
= Signal(1, name
="no_in_vec") # no inputs vector
926 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs vector
927 self
.loop_continue
= Signal(1, name
="loop_continue")
929 self
.no_in_vec
= Const(1, 1)
930 self
.no_out_vec
= Const(1, 1)
931 self
.loop_continue
= Const(0, 1)
933 def get_col_subset(self
, opkls
):
934 subset
= super().get_col_subset(opkls
)
935 subset
.add("asmcode")
936 subset
.add("in1_sel")
937 subset
.add("in2_sel")
938 subset
.add("in3_sel")
939 subset
.add("out_sel")
945 subset
.add("sv_cr_in")
946 subset
.add("sv_cr_out")
947 subset
.add("SV_Etype")
948 subset
.add("SV_Ptype")
950 subset
.add("internal_op")
954 def elaborate(self
, platform
):
955 m
= super().elaborate(platform
)
958 e_out
, op
, do_out
= self
.e
, self
.dec
.op
, self
.e
.do
959 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
960 rc_out
= self
.dec_rc
.rc_out
.data
964 # fill in for a normal instruction (not an exception)
965 # copy over if non-exception, non-privileged etc. is detected
967 # set up submodule decoders
968 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
969 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
970 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
971 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
972 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
)
973 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
)
974 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
)
975 comb
+= dec_a
.sv_nz
.eq(self
.sv_a_nz
)
978 # and SVP64 Extra decoders
979 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
980 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
981 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
982 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
983 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
984 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
985 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
986 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
987 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
989 # debug access to crout_svdec (used in get_pdecode_cr_out)
990 self
.crout_svdec
= crout_svdec
992 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
993 reg
= Signal(5, reset_less
=True)
995 # copy instruction through...
996 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
997 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
,
998 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
999 comb
+= i
.eq(self
.dec
.opcode_in
)
1002 comb
+= self
.dec_cr_in
.sel_in
.eq(op
.cr_in
)
1003 comb
+= self
.dec_cr_out
.sel_in
.eq(op
.cr_out
)
1004 comb
+= self
.dec_cr_out
.rc_in
.eq(rc_out
)
1007 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1008 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1010 # ...and subdecoders' input fields
1011 comb
+= dec_a
.sel_in
.eq(op
.in1_sel
)
1012 comb
+= dec_b
.sel_in
.eq(op
.in2_sel
)
1013 comb
+= dec_c
.sel_in
.eq(op
.in3_sel
)
1014 comb
+= dec_o
.sel_in
.eq(op
.out_sel
)
1015 comb
+= dec_o2
.sel_in
.eq(op
.out_sel
)
1016 if hasattr(do
, "lk"):
1017 comb
+= dec_o2
.lk
.eq(do
.lk
)
1020 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1021 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1022 # which in turn were auto-generated by sv_analysis.py
1023 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1027 comb
+= crout_svdec
.idx
.eq(op
.sv_cr_out
) # SVP64 CR out
1028 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1031 # CR in - selection slightly different due to shared CR field sigh
1032 cr_a_idx
= Signal(SVEXTRA
)
1033 cr_b_idx
= Signal(SVEXTRA
)
1035 # these change slightly, when decoding BA/BB. really should have
1036 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1037 comb
+= cr_a_idx
.eq(op
.sv_cr_in
)
1038 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1039 with m
.If(op
.sv_cr_in
== SVEXTRA
.Idx_1_2
.value
):
1040 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1041 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1043 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1044 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1045 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1047 # indices are slightly different, BA/BB mess sorted above
1048 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1049 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1050 comb
+= crin_svdec_o
.idx
.eq(op
.sv_cr_out
) # SVP64 CR out
1052 # get SVSTATE srcstep (TODO: elwidth, dststep etc.) needed below
1053 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1054 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1056 # registers a, b, c and out and out2 (LD/ST EA)
1057 for to_reg
, fromreg
, svdec
in (
1058 (e
.read_reg1
, dec_a
.reg_out
, in1_svdec
),
1059 (e
.read_reg2
, dec_b
.reg_out
, in2_svdec
),
1060 (e
.read_reg3
, dec_c
.reg_out
, in3_svdec
),
1061 (e
.write_reg
, dec_o
.reg_out
, o_svdec
),
1062 (e
.write_ea
, dec_o2
.reg_out
, o2_svdec
)):
1063 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1064 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
1065 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1066 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1067 # detect if Vectorised: add srcstep if yes. TODO: a LOT.
1068 # this trick only holds when elwidth=default and in single-pred
1069 with m
.If(svdec
.isvec
):
1070 comb
+= to_reg
.data
.eq(srcstep
+svdec
.reg_out
) # 7-bit output
1072 comb
+= to_reg
.data
.eq(svdec
.reg_out
) # 7-bit output
1074 comb
+= in1_svdec
.idx
.eq(op
.sv_in1
) # SVP64 reg #1 (in1_sel)
1075 comb
+= in2_svdec
.idx
.eq(op
.sv_in2
) # SVP64 reg #2 (in2_sel)
1076 comb
+= in3_svdec
.idx
.eq(op
.sv_in3
) # SVP64 reg #3 (in3_sel)
1077 comb
+= o_svdec
.idx
.eq(op
.sv_out
) # SVP64 output (out_sel)
1078 # XXX TODO - work out where this should come from. the problem is
1079 # that LD-with-update is implied (computed from "is instruction in
1080 # "update mode" rather than specified cleanly as its own CSV column
1081 #comb += o2_svdec.idx.eq(op.sv_out) # SVP64 output (implicit)
1083 # output reg-is-vectorised (and when no in/out is vectorised)
1084 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1085 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1086 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1087 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1088 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1089 # TODO add SPRs here. must be True when *all* are scalar
1090 l
= map(lambda svdec
: svdec
.isvec
, [in1_svdec
, in2_svdec
, in3_svdec
,
1091 crin_svdec
, crin_svdec_b
, crin_svdec_o
])
1092 comb
+= self
.no_in_vec
.eq(~
Cat(*l
).bool()) # all input scalar
1093 l
= map(lambda svdec
: svdec
.isvec
, [o2_svdec
, o_svdec
, crout_svdec
])
1094 comb
+= self
.no_out_vec
.eq(~
Cat(*l
).bool()) # all output scalar
1095 # now create a general-purpose "test" as to whether looping
1096 # should continue. this doesn't include predication bit-tests
1097 loop
= self
.loop_continue
1098 with m
.Switch(op
.SV_Ptype
):
1099 with m
.Case(SVPtype
.P2
.value
):
1101 # TODO: *and cache-inhibited LD/ST!*
1102 comb
+= loop
.eq(~
(self
.no_in_vec | self
.no_out_vec
))
1103 with m
.Case(SVPtype
.P1
.value
):
1104 # single-predication, test relies on dest only
1105 comb
+= loop
.eq(~self
.no_out_vec
)
1107 # not an SV operation, no looping
1110 # condition registers (CR)
1111 for to_reg
, cr
, name
, svdec
in (
1112 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", crin_svdec
),
1113 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", crin_svdec_b
),
1114 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", crin_svdec_o
),
1115 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", crout_svdec
)):
1116 fromreg
= getattr(cr
, name
)
1117 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1118 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
1119 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1120 with m
.If(svdec
.isvec
):
1121 # check if this is CR0 or CR1: treated differently
1122 # (does not "listen" to EXTRA2/3 spec for a start)
1123 # also: the CRs start from completely different locations
1124 with m
.If(cr
.sv_override
== 1): # CR0
1125 offs
= SVP64CROffs
.CR0
1126 comb
+= to_reg
.data
.eq(srcstep
+offs
)
1127 with m
.Elif(cr
.sv_override
== 2): # CR1
1128 offs
= SVP64CROffs
.CR1
1129 comb
+= to_reg
.data
.eq(srcstep
+1)
1131 comb
+= to_reg
.data
.eq(srcstep
+svdec
.cr_out
) # 7-bit out
1133 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1134 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1136 # sigh must determine if RA is nonzero (7 bit)
1137 comb
+= self
.sv_a_nz
.eq(e
.read_reg1
.data
!= Const(0, 7))
1139 # connect up to/from read/write GPRs
1140 for to_reg
, fromreg
in ((e
.read_reg1
, dec_a
.reg_out
),
1141 (e
.read_reg2
, dec_b
.reg_out
),
1142 (e
.read_reg3
, dec_c
.reg_out
),
1143 (e
.write_reg
, dec_o
.reg_out
),
1144 (e
.write_ea
, dec_o2
.reg_out
)):
1145 comb
+= to_reg
.data
.eq(fromreg
.data
)
1146 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1148 # connect up to/from read/write CRs
1149 for to_reg
, cr
, name
in (
1150 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", ),
1151 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", ),
1152 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", ),
1153 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", )):
1154 fromreg
= getattr(cr
, name
)
1155 comb
+= to_reg
.data
.eq(fromreg
.data
)
1156 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1159 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1160 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1163 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1164 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1165 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
)
1166 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
)
1168 # sigh this is exactly the sort of thing for which the
1169 # decoder is designed to not need. MTSPR, MFSPR and others need
1170 # access to the XER bits. however setting e.oe is not appropriate
1171 with m
.If(op
.internal_op
== MicrOp
.OP_MFSPR
):
1172 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1173 with m
.If(op
.internal_op
== MicrOp
.OP_CMP
):
1174 comb
+= e
.xer_in
.eq(1<<XERRegs
.SO
) # SO
1175 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
1176 comb
+= e
.xer_out
.eq(1)
1178 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1179 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1180 # *DO NOT* call self.trap here. that would reset absolutely
1181 # everything including destroying read of RA and RB.
1182 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1184 ####################
1185 # ok so the instruction's been decoded, blah blah, however
1186 # now we need to determine if it's actually going to go ahead...
1187 # *or* if in fact it's a privileged operation, whether there's
1188 # an external interrupt, etc. etc. this is a simple priority
1189 # if-elif-elif sequence. decrement takes highest priority,
1190 # EINT next highest, privileged operation third.
1192 # check if instruction is privileged
1193 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1195 # different IRQ conditions
1196 ext_irq_ok
= Signal()
1197 dec_irq_ok
= Signal()
1202 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1203 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1204 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1205 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1207 # LD/ST exceptions. TestIssuer copies the exception info at us
1208 # after a failed LD/ST.
1209 with m
.If(exc
.happened
):
1210 with m
.If(exc
.alignment
):
1211 self
.trap(m
, TT
.PRIV
, 0x600)
1212 with m
.Elif(exc
.instr_fault
):
1213 with m
.If(exc
.segment_fault
):
1214 self
.trap(m
, TT
.PRIV
, 0x480)
1216 # pass exception info to trap to create SRR1
1217 self
.trap(m
, TT
.MEMEXC
, 0x400, exc
)
1219 with m
.If(exc
.segment_fault
):
1220 self
.trap(m
, TT
.PRIV
, 0x380)
1222 self
.trap(m
, TT
.PRIV
, 0x300)
1224 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1225 with m
.Elif(dec_irq_ok
):
1226 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1228 # external interrupt? only if MSR.EE set
1229 with m
.Elif(ext_irq_ok
):
1230 self
.trap(m
, TT
.EINT
, 0x500)
1232 # privileged instruction trap
1233 with m
.Elif(priv_ok
):
1234 self
.trap(m
, TT
.PRIV
, 0x700)
1236 # illegal instruction must redirect to trap. this is done by
1237 # *overwriting* the decoded instruction and starting again.
1238 # (note: the same goes for interrupts and for privileged operations,
1239 # just with different trapaddr and traptype)
1240 with m
.Elif(illeg_ok
):
1241 # illegal instruction trap
1242 self
.trap(m
, TT
.ILLEG
, 0x700)
1244 # no exception, just copy things to the output
1248 ####################
1249 # follow-up after trap/irq to set up SRR0/1
1251 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1252 # Note: OP_SC could actually be modified to just be a trap
1253 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1254 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1255 # TRAP write fast1 = SRR0
1256 comb
+= e_out
.write_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1257 comb
+= e_out
.write_fast1
.ok
.eq(1)
1258 # TRAP write fast2 = SRR1
1259 comb
+= e_out
.write_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1260 comb
+= e_out
.write_fast2
.ok
.eq(1)
1262 # RFID: needs to read SRR0/1
1263 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1264 # TRAP read fast1 = SRR0
1265 comb
+= e_out
.read_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1266 comb
+= e_out
.read_fast1
.ok
.eq(1)
1267 # TRAP read fast2 = SRR1
1268 comb
+= e_out
.read_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1269 comb
+= e_out
.read_fast2
.ok
.eq(1)
1271 # annoying simulator bug
1272 if hasattr(e_out
, "asmcode") and hasattr(self
.dec
.op
, "asmcode"):
1273 comb
+= e_out
.asmcode
.eq(self
.dec
.op
.asmcode
)
1277 def trap(self
, m
, traptype
, trapaddr
, exc
=None):
1278 """trap: this basically "rewrites" the decoded instruction as a trap
1281 op
, e
= self
.dec
.op
, self
.e
1282 comb
+= e
.eq(0) # reset eeeeeverything
1285 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1286 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1287 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1288 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1289 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1290 comb
+= self
.do_copy("ldst_exc", exc
, True) # request type
1291 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # copy of MSR "state"
1292 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1296 def get_rdflags(e
, cu
):
1298 for idx
in range(cu
.n_src
):
1299 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1300 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
1302 print("rdflags", rdl
)
1306 if __name__
== '__main__':
1307 pdecode
= create_pdecode()
1308 dec2
= PowerDecode2(pdecode
)
1309 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1310 with
open("dec2.il", "w") as f
: