src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
   6 over-riding the internal opcode when an exception is needed.
   7 """
   8
   9 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
  10 from nmigen.cli import rtlil
  11
  12 from nmutil.iocontrol import RecordObject
  13 from nmutil.extend import exts
  14
  15 from soc.decoder.power_regspec_map import regspec_decode_read
  16 from soc.decoder.power_regspec_map import regspec_decode_write
  17 from soc.decoder.power_decoder import create_pdecode
  18 from soc.decoder.power_enums import (MicrOp, CryIn, Function,
  19                                      CRInSel, CROutSel,
  20                                      LdstLen, In1Sel, In2Sel, In3Sel,
  21                                      OutSel, SPR, RC, LDSTMode)
  22 from soc.decoder.decode2execute1 import Decode2ToExecute1Type, Data
  23 from soc.consts import MSR
  24
  25 from soc.regfile.regfiles import FastRegs
  26 from soc.consts import TT
  27
  28
  29 def decode_spr_num(spr):
  30     return Cat(spr[5:10], spr[0:5])
  31
  32
  33 def instr_is_priv(m, op, insn):
  34     """determines if the instruction is privileged or not
  35     """
  36     comb = m.d.comb
  37     is_priv_insn = Signal(reset_less=True)
  38     with m.Switch(op):
  39         with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
  40                     MicrOp.OP_MTMSR, MicrOp.OP_RFID):
  41             comb += is_priv_insn.eq(1)
  42         # XXX TODO
  43         #with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
  44         with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):
  45             with m.If(insn[20]):  # field XFX.spr[-1] i think
  46                 comb += is_priv_insn.eq(1)
  47     return is_priv_insn
  48
  49
  50 class SPRMap(Elaboratable):
  51     """SPRMap: maps POWER9 SPR numbers to internal enum values
  52     """
  53
  54     def __init__(self):
  55         self.spr_i = Signal(10, reset_less=True)
  56         self.spr_o = Signal(SPR, reset_less=True)
  57
  58     def elaborate(self, platform):
  59         m = Module()
  60         with m.Switch(self.spr_i):
  61             for i, x in enumerate(SPR):
  62                 with m.Case(x.value):
  63                     m.d.comb += self.spr_o.eq(i)
  64         return m
  65
  66
  67 class DecodeA(Elaboratable):
  68     """DecodeA from instruction
  69
  70     decodes register RA, whether immediate-zero, implicit and
  71     explicit CSRs
  72     """
  73
  74     def __init__(self, dec):
  75         self.dec = dec
  76         self.sel_in = Signal(In1Sel, reset_less=True)
  77         self.insn_in = Signal(32, reset_less=True)
  78         self.reg_out = Data(5, name="reg_a")
  79         self.immz_out = Signal(reset_less=True)
  80         self.spr_out = Data(SPR, "spr_a")
  81         self.fast_out = Data(3, "fast_a")
  82
  83     def elaborate(self, platform):
  84         m = Module()
  85         comb = m.d.comb
  86         m.submodules.sprmap = sprmap = SPRMap()
  87
  88         # select Register A field
  89         ra = Signal(5, reset_less=True)
  90         comb += ra.eq(self.dec.RA)
  91         with m.If((self.sel_in == In1Sel.RA) |
  92                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  93                    (ra != Const(0, 5)))):
  94             comb += self.reg_out.data.eq(ra)
  95             comb += self.reg_out.ok.eq(1)
  96
  97         # zero immediate requested
  98         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
  99                   (self.reg_out.data == Const(0, 5))):
 100             comb += self.immz_out.eq(1)
 101
 102         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
 103         with m.If(self.sel_in == In1Sel.RS):
 104             comb += self.reg_out.data.eq(self.dec.RS)
 105             comb += self.reg_out.ok.eq(1)
 106
 107         # decode Fast-SPR based on instruction type
 108         op = self.dec.op
 109         with m.Switch(op.internal_op):
 110
 111             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
 112             with m.Case(MicrOp.OP_BC):
 113                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 114                     # constant: CTR
 115                     comb += self.fast_out.data.eq(FastRegs.CTR)
 116                     comb += self.fast_out.ok.eq(1)
 117             with m.Case(MicrOp.OP_BCREG):
 118                 xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 119                 xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 120                 with m.If(xo9 & ~xo5):
 121                     # constant: CTR
 122                     comb += self.fast_out.data.eq(FastRegs.CTR)
 123                     comb += self.fast_out.ok.eq(1)
 124
 125             # MFSPR move from SPRs
 126             with m.Case(MicrOp.OP_MFSPR):
 127                 spr = Signal(10, reset_less=True)
 128                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 129                 with m.Switch(spr):
 130                     # fast SPRs
 131                     with m.Case(SPR.CTR.value):
 132                         comb += self.fast_out.data.eq(FastRegs.CTR)
 133                         comb += self.fast_out.ok.eq(1)
 134                     with m.Case(SPR.LR.value):
 135                         comb += self.fast_out.data.eq(FastRegs.LR)
 136                         comb += self.fast_out.ok.eq(1)
 137                     with m.Case(SPR.TAR.value):
 138                         comb += self.fast_out.data.eq(FastRegs.TAR)
 139                         comb += self.fast_out.ok.eq(1)
 140                     with m.Case(SPR.SRR0.value):
 141                         comb += self.fast_out.data.eq(FastRegs.SRR0)
 142                         comb += self.fast_out.ok.eq(1)
 143                     with m.Case(SPR.SRR1.value):
 144                         comb += self.fast_out.data.eq(FastRegs.SRR1)
 145                         comb += self.fast_out.ok.eq(1)
 146                     with m.Case(SPR.XER.value):
 147                         pass  # do nothing
 148                     # : map to internal SPR numbers
 149                     # XXX TODO: dec and tb not to go through mapping.
 150                     with m.Default():
 151                         comb += sprmap.spr_i.eq(spr)
 152                         comb += self.spr_out.data.eq(sprmap.spr_o)
 153                         comb += self.spr_out.ok.eq(1)
 154
 155         return m
 156
 157
 158 class DecodeB(Elaboratable):
 159     """DecodeB from instruction
 160
 161     decodes register RB, different forms of immediate (signed, unsigned),
 162     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 163     by industry-standard convention, "lane 2" is where fully-decoded
 164     immediates are muxed in.
 165     """
 166
 167     def __init__(self, dec):
 168         self.dec = dec
 169         self.sel_in = Signal(In2Sel, reset_less=True)
 170         self.insn_in = Signal(32, reset_less=True)
 171         self.reg_out = Data(5, "reg_b")
 172         self.imm_out = Data(64, "imm_b")
 173         self.fast_out = Data(3, "fast_b")
 174
 175     def elaborate(self, platform):
 176         m = Module()
 177         comb = m.d.comb
 178
 179         # select Register B field
 180         with m.Switch(self.sel_in):
 181             with m.Case(In2Sel.RB):
 182                 comb += self.reg_out.data.eq(self.dec.RB)
 183                 comb += self.reg_out.ok.eq(1)
 184             with m.Case(In2Sel.RS):
 185                 # for M-Form shiftrot
 186                 comb += self.reg_out.data.eq(self.dec.RS)
 187                 comb += self.reg_out.ok.eq(1)
 188             with m.Case(In2Sel.CONST_UI):
 189                 comb += self.imm_out.data.eq(self.dec.UI)
 190                 comb += self.imm_out.ok.eq(1)
 191             with m.Case(In2Sel.CONST_SI):  # TODO: sign-extend here?
 192                 comb += self.imm_out.data.eq(
 193                     exts(self.dec.SI, 16, 64))
 194                 comb += self.imm_out.ok.eq(1)
 195             with m.Case(In2Sel.CONST_UI_HI):
 196                 comb += self.imm_out.data.eq(self.dec.UI << 16)
 197                 comb += self.imm_out.ok.eq(1)
 198             with m.Case(In2Sel.CONST_SI_HI):  # TODO: sign-extend here?
 199                 comb += self.imm_out.data.eq(self.dec.SI << 16)
 200                 comb += self.imm_out.data.eq(
 201                     exts(self.dec.SI << 16, 32, 64))
 202                 comb += self.imm_out.ok.eq(1)
 203             with m.Case(In2Sel.CONST_LI):
 204                 comb += self.imm_out.data.eq(self.dec.LI << 2)
 205                 comb += self.imm_out.ok.eq(1)
 206             with m.Case(In2Sel.CONST_BD):
 207                 comb += self.imm_out.data.eq(self.dec.BD << 2)
 208                 comb += self.imm_out.ok.eq(1)
 209             with m.Case(In2Sel.CONST_DS):
 210                 comb += self.imm_out.data.eq(self.dec.DS << 2)
 211                 comb += self.imm_out.ok.eq(1)
 212             with m.Case(In2Sel.CONST_M1):
 213                 comb += self.imm_out.data.eq(~Const(0, 64))  # all 1s
 214                 comb += self.imm_out.ok.eq(1)
 215             with m.Case(In2Sel.CONST_SH):
 216                 comb += self.imm_out.data.eq(self.dec.sh)
 217                 comb += self.imm_out.ok.eq(1)
 218             with m.Case(In2Sel.CONST_SH32):
 219                 comb += self.imm_out.data.eq(self.dec.SH32)
 220                 comb += self.imm_out.ok.eq(1)
 221
 222         # decode SPR2 based on instruction type
 223         op = self.dec.op
 224         # BCREG implicitly uses LR or TAR for 2nd reg
 225         # CTR however is already in fast_spr1 *not* 2.
 226         with m.If(op.internal_op == MicrOp.OP_BCREG):
 227             xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 228             xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 229             with m.If(~xo9):
 230                 comb += self.fast_out.data.eq(FastRegs.LR)
 231                 comb += self.fast_out.ok.eq(1)
 232             with m.Elif(xo5):
 233                 comb += self.fast_out.data.eq(FastRegs.TAR)
 234                 comb += self.fast_out.ok.eq(1)
 235
 236         return m
 237
 238
 239 class DecodeC(Elaboratable):
 240     """DecodeC from instruction
 241
 242     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 243     """
 244
 245     def __init__(self, dec):
 246         self.dec = dec
 247         self.sel_in = Signal(In3Sel, reset_less=True)
 248         self.insn_in = Signal(32, reset_less=True)
 249         self.reg_out = Data(5, "reg_c")
 250
 251     def elaborate(self, platform):
 252         m = Module()
 253         comb = m.d.comb
 254
 255         # select Register C field
 256         with m.Switch(self.sel_in):
 257             with m.Case(In3Sel.RB):
 258                 # for M-Form shiftrot
 259                 comb += self.reg_out.data.eq(self.dec.RB)
 260                 comb += self.reg_out.ok.eq(1)
 261             with m.Case(In3Sel.RS):
 262                 comb += self.reg_out.data.eq(self.dec.RS)
 263                 comb += self.reg_out.ok.eq(1)
 264
 265         return m
 266
 267
 268 class DecodeOut(Elaboratable):
 269     """DecodeOut from instruction
 270
 271     decodes output register RA, RT or SPR
 272     """
 273
 274     def __init__(self, dec):
 275         self.dec = dec
 276         self.sel_in = Signal(OutSel, reset_less=True)
 277         self.insn_in = Signal(32, reset_less=True)
 278         self.reg_out = Data(5, "reg_o")
 279         self.spr_out = Data(SPR, "spr_o")
 280         self.fast_out = Data(3, "fast_o")
 281
 282     def elaborate(self, platform):
 283         m = Module()
 284         comb = m.d.comb
 285         m.submodules.sprmap = sprmap = SPRMap()
 286         op = self.dec.op
 287
 288         # select Register out field
 289         with m.Switch(self.sel_in):
 290             with m.Case(OutSel.RT):
 291                 comb += self.reg_out.data.eq(self.dec.RT)
 292                 comb += self.reg_out.ok.eq(1)
 293             with m.Case(OutSel.RA):
 294                 comb += self.reg_out.data.eq(self.dec.RA)
 295                 comb += self.reg_out.ok.eq(1)
 296             with m.Case(OutSel.SPR):
 297                 spr = Signal(10, reset_less=True)
 298                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 299                 # TODO MTSPR 1st spr (fast)
 300                 with m.If(op.internal_op == MicrOp.OP_MTSPR):
 301                     with m.Switch(spr):
 302                         # fast SPRs
 303                         with m.Case(SPR.CTR.value):
 304                             comb += self.fast_out.data.eq(FastRegs.CTR)
 305                             comb += self.fast_out.ok.eq(1)
 306                         with m.Case(SPR.LR.value):
 307                             comb += self.fast_out.data.eq(FastRegs.LR)
 308                             comb += self.fast_out.ok.eq(1)
 309                         with m.Case(SPR.TAR.value):
 310                             comb += self.fast_out.data.eq(FastRegs.TAR)
 311                             comb += self.fast_out.ok.eq(1)
 312                         with m.Case(SPR.SRR0.value):
 313                             comb += self.fast_out.data.eq(FastRegs.SRR0)
 314                             comb += self.fast_out.ok.eq(1)
 315                         with m.Case(SPR.SRR1.value):
 316                             comb += self.fast_out.data.eq(FastRegs.SRR1)
 317                             comb += self.fast_out.ok.eq(1)
 318                         with m.Case(SPR.XER.value):
 319                             pass  # do nothing
 320                         # : map to internal SPR numbers
 321                         # XXX TODO: dec and tb not to go through mapping.
 322                         with m.Default():
 323                             comb += sprmap.spr_i.eq(spr)
 324                             comb += self.spr_out.data.eq(sprmap.spr_o)
 325                             comb += self.spr_out.ok.eq(1)
 326
 327         with m.Switch(op.internal_op):
 328
 329             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
 330             with m.Case(MicrOp.OP_BC, MicrOp.OP_BCREG):
 331                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 332                     # constant: CTR
 333                     comb += self.fast_out.data.eq(FastRegs.CTR)
 334                     comb += self.fast_out.ok.eq(1)
 335
 336             # RFID 1st spr (fast)
 337             with m.Case(MicrOp.OP_RFID):
 338                 comb += self.fast_out.data.eq(FastRegs.SRR0)  # constant: SRR0
 339                 comb += self.fast_out.ok.eq(1)
 340
 341         return m
 342
 343
 344 class DecodeOut2(Elaboratable):
 345     """DecodeOut2 from instruction
 346
 347     decodes output registers
 348     """
 349
 350     def __init__(self, dec):
 351         self.dec = dec
 352         self.sel_in = Signal(OutSel, reset_less=True)
 353         self.lk = Signal(reset_less=True)
 354         self.insn_in = Signal(32, reset_less=True)
 355         self.reg_out = Data(5, "reg_o")
 356         self.fast_out = Data(3, "fast_o")
 357
 358     def elaborate(self, platform):
 359         m = Module()
 360         comb = m.d.comb
 361
 362         # update mode LD/ST uses read-reg A also as an output
 363         with m.If(self.dec.op.upd == LDSTMode.update):
 364             comb += self.reg_out.eq(self.dec.RA)
 365             comb += self.reg_out.ok.eq(1)
 366
 367         # B, BC or BCREG: potential implicit register (LR) output
 368         # these give bl, bcl, bclrl, etc.
 369         op = self.dec.op
 370         with m.Switch(op.internal_op):
 371
 372             # BC* implicit register (LR)
 373             with m.Case(MicrOp.OP_BC, MicrOp.OP_B, MicrOp.OP_BCREG):
 374                 with m.If(self.lk):  # "link" mode
 375                     comb += self.fast_out.data.eq(FastRegs.LR)  # constant: LR
 376                     comb += self.fast_out.ok.eq(1)
 377
 378             # RFID 2nd spr (fast)
 379             with m.Case(MicrOp.OP_RFID):
 380                 comb += self.fast_out.data.eq(FastRegs.SRR1)  # constant: SRR1
 381                 comb += self.fast_out.ok.eq(1)
 382
 383         return m
 384
 385
 386 class DecodeRC(Elaboratable):
 387     """DecodeRc from instruction
 388
 389     decodes Record bit Rc
 390     """
 391
 392     def __init__(self, dec):
 393         self.dec = dec
 394         self.sel_in = Signal(RC, reset_less=True)
 395         self.insn_in = Signal(32, reset_less=True)
 396         self.rc_out = Data(1, "rc")
 397
 398     def elaborate(self, platform):
 399         m = Module()
 400         comb = m.d.comb
 401
 402         # select Record bit out field
 403         with m.Switch(self.sel_in):
 404             with m.Case(RC.RC):
 405                 comb += self.rc_out.data.eq(self.dec.Rc)
 406                 comb += self.rc_out.ok.eq(1)
 407             with m.Case(RC.ONE):
 408                 comb += self.rc_out.data.eq(1)
 409                 comb += self.rc_out.ok.eq(1)
 410             with m.Case(RC.NONE):
 411                 comb += self.rc_out.data.eq(0)
 412                 comb += self.rc_out.ok.eq(1)
 413
 414         return m
 415
 416
 417 class DecodeOE(Elaboratable):
 418     """DecodeOE from instruction
 419
 420     decodes OE field: uses RC decode detection which might not be good
 421
 422     -- For now, use "rc" in the decode table to decide whether oe exists.
 423     -- This is not entirely correct architecturally: For mulhd and
 424     -- mulhdu, the OE field is reserved. It remains to be seen what an
 425     -- actual POWER9 does if we set it on those instructions, for now we
 426     -- test that further down when assigning to the multiplier oe input.
 427     """
 428
 429     def __init__(self, dec):
 430         self.dec = dec
 431         self.sel_in = Signal(RC, reset_less=True)
 432         self.insn_in = Signal(32, reset_less=True)
 433         self.oe_out = Data(1, "oe")
 434
 435     def elaborate(self, platform):
 436         m = Module()
 437         comb = m.d.comb
 438         op = self.dec.op
 439
 440         with m.Switch(op.internal_op):
 441
 442             # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
 443             with m.Case(MicrOp.OP_MUL_H64, MicrOp.OP_MUL_H32):
 444                 pass
 445
 446             # all other ops decode OE field
 447             with m.Default():
 448                 # select OE bit out field
 449                 with m.Switch(self.sel_in):
 450                     with m.Case(RC.RC):
 451                         comb += self.oe_out.data.eq(self.dec.OE)
 452                         comb += self.oe_out.ok.eq(1)
 453
 454         return m
 455
 456
 457 class DecodeCRIn(Elaboratable):
 458     """Decodes input CR from instruction
 459
 460     CR indices - insn fields - (not the data *in* the CR) require only 3
 461     bits because they refer to CR0-CR7
 462     """
 463
 464     def __init__(self, dec):
 465         self.dec = dec
 466         self.sel_in = Signal(CRInSel, reset_less=True)
 467         self.insn_in = Signal(32, reset_less=True)
 468         self.cr_bitfield = Data(3, "cr_bitfield")
 469         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 470         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 471         self.whole_reg = Signal(reset_less=True)
 472
 473     def elaborate(self, platform):
 474         m = Module()
 475         comb = m.d.comb
 476
 477         comb += self.cr_bitfield.ok.eq(0)
 478         comb += self.cr_bitfield_b.ok.eq(0)
 479         comb += self.whole_reg.eq(0)
 480         with m.Switch(self.sel_in):
 481             with m.Case(CRInSel.NONE):
 482                 pass  # No bitfield activated
 483             with m.Case(CRInSel.CR0):
 484                 comb += self.cr_bitfield.data.eq(0)
 485                 comb += self.cr_bitfield.ok.eq(1)
 486             with m.Case(CRInSel.BI):
 487                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 488                 comb += self.cr_bitfield.ok.eq(1)
 489             with m.Case(CRInSel.BFA):
 490                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 491                 comb += self.cr_bitfield.ok.eq(1)
 492             with m.Case(CRInSel.BA_BB):
 493                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 494                 comb += self.cr_bitfield.ok.eq(1)
 495                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 496                 comb += self.cr_bitfield_b.ok.eq(1)
 497                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 498                 comb += self.cr_bitfield_o.ok.eq(1)
 499             with m.Case(CRInSel.BC):
 500                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 501                 comb += self.cr_bitfield.ok.eq(1)
 502             with m.Case(CRInSel.WHOLE_REG):
 503                 comb += self.whole_reg.eq(1)
 504
 505         return m
 506
 507
 508 class DecodeCROut(Elaboratable):
 509     """Decodes input CR from instruction
 510
 511     CR indices - insn fields - (not the data *in* the CR) require only 3
 512     bits because they refer to CR0-CR7
 513     """
 514
 515     def __init__(self, dec):
 516         self.dec = dec
 517         self.rc_in = Signal(reset_less=True)
 518         self.sel_in = Signal(CROutSel, reset_less=True)
 519         self.insn_in = Signal(32, reset_less=True)
 520         self.cr_bitfield = Data(3, "cr_bitfield")
 521         self.whole_reg = Signal(reset_less=True)
 522
 523     def elaborate(self, platform):
 524         m = Module()
 525         comb = m.d.comb
 526
 527         comb += self.cr_bitfield.ok.eq(0)
 528         comb += self.whole_reg.eq(0)
 529         with m.Switch(self.sel_in):
 530             with m.Case(CROutSel.NONE):
 531                 pass  # No bitfield activated
 532             with m.Case(CROutSel.CR0):
 533                 comb += self.cr_bitfield.data.eq(0)
 534                 comb += self.cr_bitfield.ok.eq(self.rc_in)  # only when RC=1
 535             with m.Case(CROutSel.BF):
 536                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
 537                 comb += self.cr_bitfield.ok.eq(1)
 538             with m.Case(CROutSel.BT):
 539                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 540                 comb += self.cr_bitfield.ok.eq(1)
 541             with m.Case(CROutSel.WHOLE_REG):
 542                 comb += self.whole_reg.eq(1)
 543
 544         return m
 545
 546
 547 class PowerDecode2(Elaboratable):
 548     """PowerDecode2: the main instruction decoder.
 549
 550     whilst PowerDecode is responsible for decoding the actual opcode, this
 551     module encapsulates further specialist, sparse information and
 552     expansion of fields that is inconvenient to have in the CSV files.
 553     for example: the encoding of the immediates, which are detected
 554     and expanded out to their full value from an annotated (enum)
 555     representation.
 556
 557     implicit register usage is also set up, here.  for example: OP_BC
 558     requires implicitly reading CTR, OP_RFID requires implicitly writing
 559     to SRR1 and so on.
 560
 561     in addition, PowerDecoder2 is responsible for detecting whether
 562     instructions are illegal (or privileged) or not, and instead of
 563     just leaving at that, *replacing* the instruction to execute with
 564     a suitable alternative (trap).
 565     """
 566
 567     def __init__(self, dec):
 568
 569         self.dec = dec
 570         self.e = Decode2ToExecute1Type()
 571         self.valid = Signal()  # sync signal
 572
 573         # state information needed by the Decoder (TODO: this as a Record)
 574         self.msr = Signal(64, reset_less=True)  # copy of MSR
 575         self.cia = Signal(64, reset_less=True)  # copy of Program Counter
 576
 577     def ports(self):
 578         return self.dec.ports() + self.e.ports()
 579
 580     def elaborate(self, platform):
 581         m = Module()
 582         comb = m.d.comb
 583         e, op, do, msr, cia = self.e, self.dec.op, self.e.do, self.msr, self.cia
 584
 585         # set up submodule decoders
 586         m.submodules.dec = self.dec
 587         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 588         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 589         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 590         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 591         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
 592         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 593         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 594         m.submodules.dec_cr_in = dec_cr_in = DecodeCRIn(self.dec)
 595         m.submodules.dec_cr_out = dec_cr_out = DecodeCROut(self.dec)
 596
 597         # copy instruction through...
 598         for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
 599                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in, dec_rc.insn_in,
 600                   dec_oe.insn_in, dec_cr_in.insn_in, dec_cr_out.insn_in]:
 601             comb += i.eq(self.dec.opcode_in)
 602
 603         # ...and subdecoders' input fields
 604         comb += dec_a.sel_in.eq(op.in1_sel)
 605         comb += dec_b.sel_in.eq(op.in2_sel)
 606         comb += dec_c.sel_in.eq(op.in3_sel)
 607         comb += dec_o.sel_in.eq(op.out_sel)
 608         comb += dec_o2.sel_in.eq(op.out_sel)
 609         comb += dec_o2.lk.eq(do.lk)
 610         comb += dec_rc.sel_in.eq(op.rc_sel)
 611         comb += dec_oe.sel_in.eq(op.rc_sel)  # XXX should be OE sel
 612         comb += dec_cr_in.sel_in.eq(op.cr_in)
 613         comb += dec_cr_out.sel_in.eq(op.cr_out)
 614         comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
 615
 616         # copy "state" over
 617         comb += do.msr.eq(self.msr)
 618         comb += do.cia.eq(self.cia)
 619
 620         # set up instruction, pick fn unit
 621         # no op: defaults to OP_ILLEGAL
 622         comb += do.insn_type.eq(op.internal_op)
 623         comb += do.fn_unit.eq(op.function_unit)
 624
 625         # registers a, b, c and out and out2 (LD/ST EA)
 626         comb += e.read_reg1.eq(dec_a.reg_out)
 627         comb += e.read_reg2.eq(dec_b.reg_out)
 628         comb += e.read_reg3.eq(dec_c.reg_out)
 629         comb += e.write_reg.eq(dec_o.reg_out)
 630         comb += e.write_ea.eq(dec_o2.reg_out)
 631         comb += do.imm_data.eq(dec_b.imm_out)  # immediate in RB (usually)
 632         comb += do.zero_a.eq(dec_a.immz_out)  # RA==0 detected
 633
 634         # rc and oe out
 635         comb += do.rc.eq(dec_rc.rc_out)
 636         comb += do.oe.eq(dec_oe.oe_out)
 637
 638         # SPRs out
 639         comb += e.read_spr1.eq(dec_a.spr_out)
 640         comb += e.write_spr.eq(dec_o.spr_out)
 641
 642         # Fast regs out
 643         comb += e.read_fast1.eq(dec_a.fast_out)
 644         comb += e.read_fast2.eq(dec_b.fast_out)
 645         comb += e.write_fast1.eq(dec_o.fast_out)
 646         comb += e.write_fast2.eq(dec_o2.fast_out)
 647
 648         # condition registers (CR)
 649         comb += e.read_cr1.eq(dec_cr_in.cr_bitfield)
 650         comb += e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
 651         comb += e.read_cr3.eq(dec_cr_in.cr_bitfield_o)
 652         comb += e.write_cr.eq(dec_cr_out.cr_bitfield)
 653
 654         comb += do.read_cr_whole.eq(dec_cr_in.whole_reg)
 655         comb += do.write_cr_whole.eq(dec_cr_out.whole_reg)
 656         comb += do.write_cr0.eq(dec_cr_out.cr_bitfield.ok)
 657
 658         # decoded/selected instruction flags
 659         comb += do.data_len.eq(op.ldst_len)
 660         comb += do.invert_a.eq(op.inv_a)
 661         comb += do.invert_out.eq(op.inv_out)
 662         comb += do.input_carry.eq(op.cry_in)   # carry comes in
 663         comb += do.output_carry.eq(op.cry_out)  # carry goes out
 664         comb += do.is_32bit.eq(op.is_32b)
 665         comb += do.is_signed.eq(op.sgn)
 666         with m.If(op.lk):
 667             comb += do.lk.eq(self.dec.LK)  # XXX TODO: accessor
 668
 669         comb += do.byte_reverse.eq(op.br)
 670         comb += do.sign_extend.eq(op.sgn_ext)
 671         comb += do.ldst_mode.eq(op.upd)  # LD/ST mode (update, cache-inhibit)
 672
 673         # These should be removed eventually
 674         comb += do.input_cr.eq(op.cr_in)   # condition reg comes in
 675         comb += do.output_cr.eq(op.cr_out)  # condition reg goes in
 676
 677         # sigh this is exactly the sort of thing for which the
 678         # decoder is designed to not need.  MTSPR, MFSPR and others need
 679         # access to the XER bits.  however setting e.oe is not appropriate
 680         with m.If(op.internal_op == MicrOp.OP_MFSPR):
 681             comb += e.xer_in.eq(1)
 682         with m.If(op.internal_op == MicrOp.OP_MTSPR):
 683             comb += e.xer_out.eq(1)
 684
 685         # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
 686         with m.If(op.internal_op == MicrOp.OP_TRAP):
 687             # *DO NOT* call self.trap here.  that would reset absolutely
 688             # rverything including destroying read of RA and RB.
 689             comb += do.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
 690
 691         # TODO: get msr, then can do privileged instruction
 692         with m.If(instr_is_priv(m, op.internal_op, e.do.insn) & msr[MSR.PR]):
 693             # privileged instruction trap
 694             self.trap(m, TT.PRIV, 0x700)
 695
 696         # illegal instruction must redirect to trap. this is done by
 697         # *overwriting* the decoded instruction and starting again.
 698         # (note: the same goes for interrupts and for privileged operations,
 699         # just with different trapaddr and traptype)
 700         with m.Elif(op.internal_op == MicrOp.OP_ILLEGAL):
 701             # illegal instruction trap
 702             self.trap(m, TT.ILLEG, 0x700)
 703
 704         # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
 705         # Note: OP_SC could actually be modified to just be a trap
 706         with m.If((do.insn_type == MicrOp.OP_TRAP) |
 707                   (do.insn_type == MicrOp.OP_SC)):
 708             # TRAP write fast1 = SRR0
 709             comb += e.write_fast1.data.eq(FastRegs.SRR0)  # constant: SRR0
 710             comb += e.write_fast1.ok.eq(1)
 711             # TRAP write fast2 = SRR1
 712             comb += e.write_fast2.data.eq(FastRegs.SRR1)  # constant: SRR1
 713             comb += e.write_fast2.ok.eq(1)
 714
 715         # RFID: needs to read SRR0/1
 716         with m.If(do.insn_type == MicrOp.OP_RFID):
 717             # TRAP read fast1 = SRR0
 718             comb += e.read_fast1.data.eq(FastRegs.SRR0)  # constant: SRR0
 719             comb += e.read_fast1.ok.eq(1)
 720             # TRAP read fast2 = SRR1
 721             comb += e.read_fast2.data.eq(FastRegs.SRR1)  # constant: SRR1
 722             comb += e.read_fast2.ok.eq(1)
 723
 724         return m
 725
 726     def trap(self, m, traptype, trapaddr):
 727         """trap: this basically "rewrites" the decoded instruction as a trap
 728         """
 729         comb = m.d.comb
 730         e, op, do = self.e, self.dec.op, self.e.do
 731         comb += e.eq(0)  # reset eeeeeverything
 732         # start again
 733         comb += do.insn.eq(self.dec.opcode_in)
 734         comb += do.insn_type.eq(MicrOp.OP_TRAP)
 735         comb += do.fn_unit.eq(Function.TRAP)
 736         comb += do.trapaddr.eq(trapaddr >> 4)  # cut bottom 4 bits
 737         comb += do.traptype.eq(traptype)  # request type
 738         comb += do.msr.eq(self.msr)  # copy of MSR "state"
 739         comb += do.cia.eq(self.cia)  # copy of PC "state"
 740
 741     def regspecmap_read(self, regfile, regname):
 742         """regspecmap_read: provides PowerDecode2 with an encoding relationship
 743         to Function Unit port regfiles (read-enable, read regnum, write regnum)
 744         regfile and regname arguments are fields 1 and 2 from a given regspec.
 745         """
 746         return regspec_decode_read(self.e, regfile, regname)
 747
 748     def regspecmap_write(self, regfile, regname):
 749         """regspecmap_write: provides PowerDecode2 with an encoding relationship
 750         to Function Unit port regfiles (write port, write regnum)
 751         regfile and regname arguments are fields 1 and 2 from a given regspec.
 752         """
 753         return regspec_decode_write(self.e, regfile, regname)
 754
 755     def rdflags(self, cu):
 756         rdl = []
 757         for idx in range(cu.n_src):
 758             regfile, regname, _ = cu.get_in_spec(idx)
 759             rdflag, read = self.regspecmap_read(regfile, regname)
 760             rdl.append(rdflag)
 761         print("rdflags", rdl)
 762         return Cat(*rdl)
 763
 764
 765 if __name__ == '__main__':
 766     pdecode = create_pdecode()
 767     dec2 = PowerDecode2(pdecode)
 768     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 769     with open("dec2.il", "w") as f:
 770         f.write(vl)