1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
12 from nmutil
.iocontrol
import RecordObject
13 from nmutil
.extend
import exts
15 from soc
.decoder
.power_regspec_map
import regspec_decode_read
16 from soc
.decoder
.power_regspec_map
import regspec_decode_write
17 from soc
.decoder
.power_decoder
import create_pdecode
18 from soc
.decoder
.power_enums
import (InternalOp
, CryIn
, Function
,
20 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
22 from soc
.decoder
.decode2execute1
import Decode2ToExecute1Type
, Data
24 from soc
.regfile
.regfiles
import FastRegs
26 # see traptype (and trap main_stage.py)
33 def decode_spr_num(spr
):
34 return Cat(spr
[5:10], spr
[0:5])
37 def instr_is_priv(m
, op
, insn
):
38 """determines if the instruction is privileged or not
41 Signal
= is_priv_insn(reset_less
=True)
43 with m
.Case(InternalOp
.OP_ATTN
) : comb
+= is_priv_insn
.eq(1)
44 with m
.Case(InternalOp
.OP_MFMSR
) : comb
+= is_priv_insn
.eq(1)
45 with m
.Case(InternalOp
.OP_MTMSRD
): comb
+= is_priv_insn
.eq(1)
46 with m
.Case(InternalOp
.OP_RFID
) : comb
+= is_priv_insn
.eq(1)
47 with m
.Case(InternalOp
.OP_TLBIE
) : comb
+= is_priv_insn
.eq(1)
48 with m
.If(op
== OP_MFSPR | op
== OP_MTSPR
):
49 with m
.If(insn
[20]): # field XFX.spr[-1] i think
50 comb
+= is_priv_insn
.eq(1)
54 class DecodeA(Elaboratable
):
55 """DecodeA from instruction
57 decodes register RA, whether immediate-zero, implicit and
61 def __init__(self
, dec
):
63 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
64 self
.insn_in
= Signal(32, reset_less
=True)
65 self
.reg_out
= Data(5, name
="reg_a")
66 self
.immz_out
= Signal(reset_less
=True)
67 self
.spr_out
= Data(10, "spr_a")
68 self
.fast_out
= Data(3, "fast_a")
70 def elaborate(self
, platform
):
74 # select Register A field
75 ra
= Signal(5, reset_less
=True)
76 comb
+= ra
.eq(self
.dec
.RA
)
77 with m
.If((self
.sel_in
== In1Sel
.RA
) |
78 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
79 (ra
!= Const(0, 5)))):
80 comb
+= self
.reg_out
.data
.eq(ra
)
81 comb
+= self
.reg_out
.ok
.eq(1)
83 # zero immediate requested
84 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
85 (self
.reg_out
.data
== Const(0, 5))):
86 comb
+= self
.immz_out
.eq(1)
88 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
89 with m
.If(self
.sel_in
== In1Sel
.RS
):
90 comb
+= self
.reg_out
.data
.eq(self
.dec
.RS
)
91 comb
+= self
.reg_out
.ok
.eq(1)
93 # decode Fast-SPR based on instruction type
95 # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
96 with m
.If(op
.internal_op
== InternalOp
.OP_BC
):
97 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
98 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
) # constant: CTR
99 comb
+= self
.fast_out
.ok
.eq(1)
100 with m
.Elif(op
.internal_op
== InternalOp
.OP_BCREG
):
101 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
102 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
103 with m
.If(xo9
& ~xo5
):
104 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
) # constant: CTR
105 comb
+= self
.fast_out
.ok
.eq(1)
107 # MFSPR move from SPRs
108 with m
.If(op
.internal_op
== InternalOp
.OP_MFSPR
):
109 spr
= Signal(10, reset_less
=True)
110 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
113 with m
.Case(SPR
.CTR
.value
):
114 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
115 comb
+= self
.fast_out
.ok
.eq(1)
116 with m
.Case(SPR
.LR
.value
):
117 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
118 comb
+= self
.fast_out
.ok
.eq(1)
119 with m
.Case(SPR
.TAR
.value
):
120 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
121 comb
+= self
.fast_out
.ok
.eq(1)
122 with m
.Case(SPR
.SRR0
.value
):
123 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
)
124 comb
+= self
.fast_out
.ok
.eq(1)
125 with m
.Case(SPR
.SRR1
.value
):
126 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
)
127 comb
+= self
.fast_out
.ok
.eq(1)
128 with m
.Case(SPR
.XER
.value
):
130 # XXX TODO: map to internal SPR numbers
131 # XXX TODO: dec and tb not to go through mapping.
133 comb
+= self
.spr_out
.data
.eq(spr
)
134 comb
+= self
.spr_out
.ok
.eq(1)
140 class DecodeB(Elaboratable
):
141 """DecodeB from instruction
143 decodes register RB, different forms of immediate (signed, unsigned),
144 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
145 by industry-standard convention, "lane 2" is where fully-decoded
146 immediates are muxed in.
149 def __init__(self
, dec
):
151 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
152 self
.insn_in
= Signal(32, reset_less
=True)
153 self
.reg_out
= Data(5, "reg_b")
154 self
.imm_out
= Data(64, "imm_b")
155 self
.fast_out
= Data(3, "fast_b")
157 def elaborate(self
, platform
):
161 # select Register B field
162 with m
.Switch(self
.sel_in
):
163 with m
.Case(In2Sel
.RB
):
164 comb
+= self
.reg_out
.data
.eq(self
.dec
.RB
)
165 comb
+= self
.reg_out
.ok
.eq(1)
166 with m
.Case(In2Sel
.RS
):
167 comb
+= self
.reg_out
.data
.eq(self
.dec
.RS
) # for M-Form shiftrot
168 comb
+= self
.reg_out
.ok
.eq(1)
169 with m
.Case(In2Sel
.CONST_UI
):
170 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
171 comb
+= self
.imm_out
.ok
.eq(1)
172 with m
.Case(In2Sel
.CONST_SI
): # TODO: sign-extend here?
173 comb
+= self
.imm_out
.data
.eq(
174 exts(self
.dec
.SI
, 16, 64))
175 comb
+= self
.imm_out
.ok
.eq(1)
176 with m
.Case(In2Sel
.CONST_UI_HI
):
177 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
<<16)
178 comb
+= self
.imm_out
.ok
.eq(1)
179 with m
.Case(In2Sel
.CONST_SI_HI
): # TODO: sign-extend here?
180 comb
+= self
.imm_out
.data
.eq(self
.dec
.SI
<<16)
181 comb
+= self
.imm_out
.data
.eq(
182 exts(self
.dec
.SI
<< 16, 32, 64))
183 comb
+= self
.imm_out
.ok
.eq(1)
184 with m
.Case(In2Sel
.CONST_LI
):
185 comb
+= self
.imm_out
.data
.eq(self
.dec
.LI
<<2)
186 comb
+= self
.imm_out
.ok
.eq(1)
187 with m
.Case(In2Sel
.CONST_BD
):
188 comb
+= self
.imm_out
.data
.eq(self
.dec
.BD
<<2)
189 comb
+= self
.imm_out
.ok
.eq(1)
190 with m
.Case(In2Sel
.CONST_DS
):
191 comb
+= self
.imm_out
.data
.eq(self
.dec
.DS
<<2)
192 comb
+= self
.imm_out
.ok
.eq(1)
193 with m
.Case(In2Sel
.CONST_M1
):
194 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
195 comb
+= self
.imm_out
.ok
.eq(1)
196 with m
.Case(In2Sel
.CONST_SH
):
197 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
198 comb
+= self
.imm_out
.ok
.eq(1)
199 with m
.Case(In2Sel
.CONST_SH32
):
200 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
201 comb
+= self
.imm_out
.ok
.eq(1)
203 # decode SPR2 based on instruction type
205 # BCREG implicitly uses LR or TAR for 2nd reg
206 # CTR however is already in fast_spr1 *not* 2.
207 with m
.If(op
.internal_op
== InternalOp
.OP_BCREG
):
208 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
209 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
211 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
212 comb
+= self
.fast_out
.ok
.eq(1)
214 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
215 comb
+= self
.fast_out
.ok
.eq(1)
220 class DecodeC(Elaboratable
):
221 """DecodeC from instruction
223 decodes register RC. this is "lane 3" into some CompUnits (not many)
226 def __init__(self
, dec
):
228 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
229 self
.insn_in
= Signal(32, reset_less
=True)
230 self
.reg_out
= Data(5, "reg_c")
232 def elaborate(self
, platform
):
236 # select Register C field
237 with m
.Switch(self
.sel_in
):
238 with m
.Case(In3Sel
.RB
):
239 comb
+= self
.reg_out
.data
.eq(self
.dec
.RB
) # for M-Form shiftrot
240 comb
+= self
.reg_out
.ok
.eq(1)
241 with m
.Case(In3Sel
.RS
):
242 comb
+= self
.reg_out
.data
.eq(self
.dec
.RS
)
243 comb
+= self
.reg_out
.ok
.eq(1)
248 class DecodeOut(Elaboratable
):
249 """DecodeOut from instruction
251 decodes output register RA, RT or SPR
254 def __init__(self
, dec
):
256 self
.sel_in
= Signal(OutSel
, reset_less
=True)
257 self
.insn_in
= Signal(32, reset_less
=True)
258 self
.reg_out
= Data(5, "reg_o")
259 self
.spr_out
= Data(10, "spr_o")
260 self
.fast_out
= Data(3, "fast_o")
262 def elaborate(self
, platform
):
267 # select Register out field
268 with m
.Switch(self
.sel_in
):
269 with m
.Case(OutSel
.RT
):
270 comb
+= self
.reg_out
.data
.eq(self
.dec
.RT
)
271 comb
+= self
.reg_out
.ok
.eq(1)
272 with m
.Case(OutSel
.RA
):
273 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
274 comb
+= self
.reg_out
.ok
.eq(1)
275 with m
.Case(OutSel
.SPR
):
276 spr
= Signal(10, reset_less
=True)
277 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
278 # TODO MTSPR 1st spr (fast)
279 with m
.If(op
.internal_op
== InternalOp
.OP_MTSPR
):
282 with m
.Case(SPR
.CTR
.value
):
283 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
284 comb
+= self
.fast_out
.ok
.eq(1)
285 with m
.Case(SPR
.LR
.value
):
286 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
287 comb
+= self
.fast_out
.ok
.eq(1)
288 with m
.Case(SPR
.TAR
.value
):
289 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
290 comb
+= self
.fast_out
.ok
.eq(1)
291 with m
.Case(SPR
.SRR0
.value
):
292 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
)
293 comb
+= self
.fast_out
.ok
.eq(1)
294 with m
.Case(SPR
.SRR1
.value
):
295 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
)
296 comb
+= self
.fast_out
.ok
.eq(1)
297 with m
.Case(SPR
.XER
.value
):
299 # XXX TODO: map to internal SPR numbers
300 # XXX TODO: dec and tb not to go through mapping.
302 comb
+= self
.spr_out
.data
.eq(spr
)
303 comb
+= self
.spr_out
.ok
.eq(1)
305 # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
307 with m
.If((op
.internal_op
== InternalOp
.OP_BC
) |
308 (op
.internal_op
== InternalOp
.OP_BCREG
)):
309 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
310 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
) # constant: CTR
311 comb
+= self
.fast_out
.ok
.eq(1)
313 # RFID 1st spr (fast)
314 with m
.If(op
.internal_op
== InternalOp
.OP_RFID
):
315 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
316 comb
+= self
.fast_out
.ok
.eq(1)
319 with m
.If(op
.internal_op
== InternalOp
.OP_TRAP
):
320 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
321 comb
+= self
.fast_out
.ok
.eq(1)
326 class DecodeOut2(Elaboratable
):
327 """DecodeOut2 from instruction
329 decodes output registers
332 def __init__(self
, dec
):
334 self
.sel_in
= Signal(OutSel
, reset_less
=True)
335 self
.lk
= Signal(reset_less
=True)
336 self
.insn_in
= Signal(32, reset_less
=True)
337 self
.reg_out
= Data(5, "reg_o")
338 self
.fast_out
= Data(3, "fast_o")
340 def elaborate(self
, platform
):
344 # update mode LD/ST uses read-reg A also as an output
345 with m
.If(self
.dec
.op
.upd
):
346 comb
+= self
.reg_out
.eq(self
.dec
.RA
)
347 comb
+= self
.reg_out
.ok
.eq(1)
349 # BC or BCREG: potential implicit register (LR) output
351 with m
.If((op
.internal_op
== InternalOp
.OP_BC
) |
352 (op
.internal_op
== InternalOp
.OP_BCREG
)):
353 with m
.If(self
.lk
): # "link" mode
354 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
) # constant: LR
355 comb
+= self
.fast_out
.ok
.eq(1)
357 # RFID 2nd spr (fast)
358 with m
.If(op
.internal_op
== InternalOp
.OP_RFID
):
359 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
360 comb
+= self
.fast_out
.ok
.eq(1)
363 with m
.If(op
.internal_op
== InternalOp
.OP_TRAP
):
364 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
365 comb
+= self
.fast_out
.ok
.eq(1)
370 class DecodeRC(Elaboratable
):
371 """DecodeRc from instruction
373 decodes Record bit Rc
375 def __init__(self
, dec
):
377 self
.sel_in
= Signal(RC
, reset_less
=True)
378 self
.insn_in
= Signal(32, reset_less
=True)
379 self
.rc_out
= Data(1, "rc")
381 def elaborate(self
, platform
):
385 # select Record bit out field
386 with m
.Switch(self
.sel_in
):
388 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
389 comb
+= self
.rc_out
.ok
.eq(1)
391 comb
+= self
.rc_out
.data
.eq(1)
392 comb
+= self
.rc_out
.ok
.eq(1)
393 with m
.Case(RC
.NONE
):
394 comb
+= self
.rc_out
.data
.eq(0)
395 comb
+= self
.rc_out
.ok
.eq(1)
400 class DecodeOE(Elaboratable
):
401 """DecodeOE from instruction
403 decodes OE field: uses RC decode detection which might not be good
405 -- For now, use "rc" in the decode table to decide whether oe exists.
406 -- This is not entirely correct architecturally: For mulhd and
407 -- mulhdu, the OE field is reserved. It remains to be seen what an
408 -- actual POWER9 does if we set it on those instructions, for now we
409 -- test that further down when assigning to the multiplier oe input.
411 def __init__(self
, dec
):
413 self
.sel_in
= Signal(RC
, reset_less
=True)
414 self
.insn_in
= Signal(32, reset_less
=True)
415 self
.oe_out
= Data(1, "oe")
417 def elaborate(self
, platform
):
421 # select OE bit out field
422 with m
.Switch(self
.sel_in
):
424 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
425 comb
+= self
.oe_out
.ok
.eq(1)
429 class DecodeCRIn(Elaboratable
):
430 """Decodes input CR from instruction
432 CR indices - insn fields - (not the data *in* the CR) require only 3
433 bits because they refer to CR0-CR7
436 def __init__(self
, dec
):
438 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
439 self
.insn_in
= Signal(32, reset_less
=True)
440 self
.cr_bitfield
= Data(3, "cr_bitfield")
441 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
442 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
443 self
.whole_reg
= Signal(reset_less
=True)
445 def elaborate(self
, platform
):
449 comb
+= self
.cr_bitfield
.ok
.eq(0)
450 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
451 comb
+= self
.whole_reg
.eq(0)
452 with m
.Switch(self
.sel_in
):
453 with m
.Case(CRInSel
.NONE
):
454 pass # No bitfield activated
455 with m
.Case(CRInSel
.CR0
):
456 comb
+= self
.cr_bitfield
.data
.eq(0)
457 comb
+= self
.cr_bitfield
.ok
.eq(1)
458 with m
.Case(CRInSel
.BI
):
459 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
460 comb
+= self
.cr_bitfield
.ok
.eq(1)
461 with m
.Case(CRInSel
.BFA
):
462 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
463 comb
+= self
.cr_bitfield
.ok
.eq(1)
464 with m
.Case(CRInSel
.BA_BB
):
465 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
466 comb
+= self
.cr_bitfield
.ok
.eq(1)
467 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
468 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
469 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
470 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
471 with m
.Case(CRInSel
.BC
):
472 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
473 comb
+= self
.cr_bitfield
.ok
.eq(1)
474 with m
.Case(CRInSel
.WHOLE_REG
):
475 comb
+= self
.whole_reg
.eq(1)
480 class DecodeCROut(Elaboratable
):
481 """Decodes input CR from instruction
483 CR indices - insn fields - (not the data *in* the CR) require only 3
484 bits because they refer to CR0-CR7
487 def __init__(self
, dec
):
489 self
.rc_in
= Signal(reset_less
=True)
490 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
491 self
.insn_in
= Signal(32, reset_less
=True)
492 self
.cr_bitfield
= Data(3, "cr_bitfield")
493 self
.whole_reg
= Signal(reset_less
=True)
495 def elaborate(self
, platform
):
499 comb
+= self
.cr_bitfield
.ok
.eq(0)
500 comb
+= self
.whole_reg
.eq(0)
501 with m
.Switch(self
.sel_in
):
502 with m
.Case(CROutSel
.NONE
):
503 pass # No bitfield activated
504 with m
.Case(CROutSel
.CR0
):
505 comb
+= self
.cr_bitfield
.data
.eq(0)
506 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
507 with m
.Case(CROutSel
.BF
):
508 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
509 comb
+= self
.cr_bitfield
.ok
.eq(1)
510 with m
.Case(CROutSel
.BT
):
511 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
512 comb
+= self
.cr_bitfield
.ok
.eq(1)
513 with m
.Case(CROutSel
.WHOLE_REG
):
514 comb
+= self
.whole_reg
.eq(1)
521 self
.ca
= Signal(2, reset_less
=True)
522 self
.ov
= Signal(2, reset_less
=True)
523 self
.so
= Signal(reset_less
=True)
526 return [self
.ca
, self
.ov
, self
.so
]
529 class PowerDecode2(Elaboratable
):
531 def __init__(self
, dec
):
534 self
.e
= Decode2ToExecute1Type()
537 return self
.dec
.ports() + self
.e
.ports()
539 def elaborate(self
, platform
):
542 e
, op
= self
.e
, self
.dec
.op
544 # set up submodule decoders
545 m
.submodules
.dec
= self
.dec
546 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
547 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
548 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
549 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
550 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
)
551 m
.submodules
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
552 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
553 m
.submodules
.dec_cr_in
= dec_cr_in
= DecodeCRIn(self
.dec
)
554 m
.submodules
.dec_cr_out
= dec_cr_out
= DecodeCROut(self
.dec
)
556 # copy instruction through...
557 for i
in [e
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
558 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
, dec_rc
.insn_in
,
559 dec_oe
.insn_in
, dec_cr_in
.insn_in
, dec_cr_out
.insn_in
]:
560 comb
+= i
.eq(self
.dec
.opcode_in
)
562 # ...and subdecoders' input fields
563 comb
+= dec_a
.sel_in
.eq(op
.in1_sel
)
564 comb
+= dec_b
.sel_in
.eq(op
.in2_sel
)
565 comb
+= dec_c
.sel_in
.eq(op
.in3_sel
)
566 comb
+= dec_o
.sel_in
.eq(op
.out_sel
)
567 comb
+= dec_o2
.sel_in
.eq(op
.out_sel
)
568 comb
+= dec_o2
.lk
.eq(e
.lk
)
569 comb
+= dec_rc
.sel_in
.eq(op
.rc_sel
)
570 comb
+= dec_oe
.sel_in
.eq(op
.rc_sel
) # XXX should be OE sel
571 comb
+= dec_cr_in
.sel_in
.eq(op
.cr_in
)
572 comb
+= dec_cr_out
.sel_in
.eq(op
.cr_out
)
573 comb
+= dec_cr_out
.rc_in
.eq(dec_rc
.rc_out
.data
)
576 comb
+= e
.nia
.eq(0) # XXX TODO (or remove? not sure yet)
577 fu
= op
.function_unit
578 itype
= Mux(fu
== Function
.NONE
, InternalOp
.OP_ILLEGAL
, op
.internal_op
)
579 comb
+= e
.insn_type
.eq(itype
)
580 comb
+= e
.fn_unit
.eq(fu
)
582 # registers a, b, c and out and out2 (LD/ST EA)
583 comb
+= e
.read_reg1
.eq(dec_a
.reg_out
)
584 comb
+= e
.read_reg2
.eq(dec_b
.reg_out
)
585 comb
+= e
.read_reg3
.eq(dec_c
.reg_out
)
586 comb
+= e
.write_reg
.eq(dec_o
.reg_out
)
587 comb
+= e
.write_ea
.eq(dec_o2
.reg_out
)
588 comb
+= e
.imm_data
.eq(dec_b
.imm_out
) # immediate in RB (usually)
589 comb
+= e
.zero_a
.eq(dec_a
.immz_out
) # RA==0 detected
592 comb
+= e
.rc
.eq(dec_rc
.rc_out
)
593 comb
+= e
.oe
.eq(dec_oe
.oe_out
)
596 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
597 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
600 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
601 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
602 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
)
603 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
)
605 comb
+= e
.read_cr1
.eq(dec_cr_in
.cr_bitfield
)
606 comb
+= e
.read_cr2
.eq(dec_cr_in
.cr_bitfield_b
)
607 comb
+= e
.read_cr3
.eq(dec_cr_in
.cr_bitfield_o
)
608 comb
+= e
.read_cr_whole
.eq(dec_cr_in
.whole_reg
)
610 comb
+= e
.write_cr
.eq(dec_cr_out
.cr_bitfield
)
611 comb
+= e
.write_cr_whole
.eq(dec_cr_out
.whole_reg
)
613 # decoded/selected instruction flags
614 comb
+= e
.data_len
.eq(op
.ldst_len
)
615 comb
+= e
.invert_a
.eq(op
.inv_a
)
616 comb
+= e
.invert_out
.eq(op
.inv_out
)
617 comb
+= e
.input_carry
.eq(op
.cry_in
) # carry comes in
618 comb
+= e
.output_carry
.eq(op
.cry_out
) # carry goes out
619 comb
+= e
.is_32bit
.eq(op
.is_32b
)
620 comb
+= e
.is_signed
.eq(op
.sgn
)
622 comb
+= e
.lk
.eq(self
.dec
.LK
) # XXX TODO: accessor
624 comb
+= e
.byte_reverse
.eq(op
.br
)
625 comb
+= e
.sign_extend
.eq(op
.sgn_ext
)
626 comb
+= e
.update
.eq(op
.upd
) # LD/ST "update" mode.
629 # These should be removed eventually
630 comb
+= e
.input_cr
.eq(op
.cr_in
) # condition reg comes in
631 comb
+= e
.output_cr
.eq(op
.cr_out
) # condition reg goes in
633 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
634 with m
.If(op
.internal_op
== InternalOp
.OP_TRAP
):
635 comb
+= e
.trapaddr
.eq(0x70) # addr=0x700 (strip first nibble)
639 # privileged instruction
640 with m
.If(instr_is_priv(m
, op
.internal_op
, e
.insn
) & msr
[MSR_PR
]):
641 # don't request registers RA/RT
642 comb
+= e
.read_reg1
.eq(0)
643 comb
+= e
.read_reg2
.eq(0)
644 comb
+= e
.read_reg3
.eq(0)
645 comb
+= e
.write_reg
.eq(0)
646 comb
+= e
.write_ea
.eq(0)
647 # privileged instruction trap
648 comb
+= op
.internal_op
.eq(InternalOp
.OP_TRAP
)
649 comb
+= e
.traptype
.eq(TT_PRIV
) # request privileged instruction
650 comb
+= e
.trapaddr
.eq(0x70) # addr=0x700 (strip first nibble)
653 def regspecmap_read(self
, regfile
, regname
):
654 """regspecmap_read: provides PowerDecode2 with an encoding relationship
655 to Function Unit port regfiles (read-enable, read regnum, write regnum)
656 regfile and regname arguments are fields 1 and 2 from a given regspec.
658 return regspec_decode_read(self
.e
, regfile
, regname
)
660 def regspecmap_write(self
, regfile
, regname
):
661 """regspecmap_write: provides PowerDecode2 with an encoding relationship
662 to Function Unit port regfiles (write port, write regnum)
663 regfile and regname arguments are fields 1 and 2 from a given regspec.
665 return regspec_decode_write(self
.e
, regfile
, regname
)
667 def rdflags(self
, cu
):
669 for idx
in range(cu
.n_src
):
670 regfile
, regname
, _
= cu
.get_in_spec(idx
)
671 rdflag
, read
= self
.regspecmap_read(regfile
, regname
)
673 print ("rdflags", rdl
)
677 if __name__
== '__main__':
678 pdecode
= create_pdecode()
679 dec2
= PowerDecode2(pdecode
)
680 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
681 with
open("dec2.il", "w") as f
: