1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from soc
.regfile
.regfiles
import XERRegs
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from soc
.experiment
.mem_types
import LDSTException
19 from soc
.decoder
.power_regspec_map
import regspec_decode_read
20 from soc
.decoder
.power_regspec_map
import regspec_decode_write
21 from soc
.decoder
.power_decoder
import create_pdecode
22 from soc
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
24 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
25 OutSel
, SPR
, RC
, LDSTMode
,
27 from soc
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
29 from soc
.sv
.svp64
import SVP64Rec
30 from soc
.consts
import (MSR
, sel
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
)
32 from soc
.regfile
.regfiles
import FastRegs
33 from soc
.consts
import TT
34 from soc
.config
.state
import CoreState
35 from soc
.regfile
.util
import spr_to_fast
38 def decode_spr_num(spr
):
39 return Cat(spr
[5:10], spr
[0:5])
42 def instr_is_priv(m
, op
, insn
):
43 """determines if the instruction is privileged or not
46 is_priv_insn
= Signal(reset_less
=True)
48 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
49 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
50 comb
+= is_priv_insn
.eq(1)
51 with m
.Case(MicrOp
.OP_TLBIE
) : comb
+= is_priv_insn
.eq(1)
52 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
53 with m
.If(insn
[20]): # field XFX.spr[-1] i think
54 comb
+= is_priv_insn
.eq(1)
58 class SPRMap(Elaboratable
):
59 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
63 self
.spr_i
= Signal(10, reset_less
=True)
64 self
.spr_o
= Data(SPR
, name
="spr_o")
65 self
.fast_o
= Data(3, name
="fast_o")
67 def elaborate(self
, platform
):
69 with m
.Switch(self
.spr_i
):
70 for i
, x
in enumerate(SPR
):
72 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
73 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
74 for x
, v
in spr_to_fast
.items():
76 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
77 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
81 class SVP64ExtraSpec(Elaboratable
):
82 """SVP64ExtraSpec - decodes SVP64 Extra specification.
84 selects the required EXTRA2/3 field.
86 see https://libre-soc.org/openpower/sv/svp64/
89 self
.extra
= Signal(9, reset_less
=True)
90 self
.etype
= Signal(SVEtype
, reset_less
=True) # 2 or 3 bits
91 self
.idx
= Signal(SVEXTRA
, reset_less
=True) # which part of extra
92 self
.spec
= Signal(3) # EXTRA spec for the register
94 def elaborate(self
, platform
):
100 # back in the LDSTRM-* and RM-* files generated by sv_analysis.py
101 # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
102 # which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
103 # the register-extension information. extract those now
104 with m
.Switch(self
.etype
):
105 # 2-bit index selection mode
106 with m
.Case(SVEtype
.EXTRA2
):
107 with m
.Switch(self
.idx
):
108 with m
.Case(SVEXTRA
.Idx0
): # 1st 2 bits [0:1]
109 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX0_VEC
])
110 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX0_MSB
])
111 with m
.Case(SVEXTRA
.Idx1
): # 2nd 2 bits [2:3]
112 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX1_VEC
])
113 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX1_MSB
])
114 with m
.Case(SVEXTRA
.Idx2
): # 3rd 2 bits [4:5]
115 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX2_VEC
])
116 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX2_MSB
])
117 with m
.Case(SVEXTRA
.Idx3
): # 4th 2 bits [6:7]
118 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX3_VEC
])
119 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX3_MSB
])
120 # 3-bit index selection mode
121 with m
.Case(SVEtype
.EXTRA3
):
122 with m
.Switch(self
.idx
):
123 with m
.Case(SVEXTRA
.Idx0
): # 1st 3 bits [0:2]
124 comb
+= spec
.eq(sel(extra
, EXTRA3
.IDX0
))
125 with m
.Case(SVEXTRA
.Idx1
): # 2nd 3 bits [3:5]
126 comb
+= spec
.eq(sel(extra
, EXTRA3
.IDX1
))
127 with m
.Case(SVEXTRA
.Idx2
): # 3rd 3 bits [6:8]
128 comb
+= spec
.eq(sel(extra
, EXTRA3
.IDX2
))
129 # cannot fit more than 9 bits so there is no 4th thing
134 class SVP64RegExtra(SVP64ExtraSpec
):
135 """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
137 incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
138 depending on info in one of the positions in the EXTRA field.
140 designed so that "no change" to the 5-bit register number occurs if
141 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
143 see https://libre-soc.org/openpower/sv/svp64/
146 SVP64ExtraSpec
.__init
__(self
)
147 self
.reg_in
= Signal(5) # incoming reg number (5 bits, RA, RB)
148 self
.reg_out
= Signal(7) # extra-augmented output (7 bits)
149 self
.isvec
= Signal(1) # reg is marked as vector if true
151 def elaborate(self
, platform
):
152 m
= super().elaborate(platform
) # select required EXTRA2/3
155 # first get the spec. if not changed it's "scalar identity behaviour"
156 # which is zero which is ok.
159 # now decode it. bit 2 is "scalar/vector". note that spec could be zero
160 # from above, which (by design) has the effect of "no change", below.
162 # simple: isvec is top bit of spec
163 comb
+= self
.isvec
.eq(spec
[2])
165 # decode vector differently from scalar
166 with m
.If(self
.isvec
):
167 # Vector: shifted up, extra in LSBs (RA << 2) | spec[0:1]
168 comb
+= self
.reg_out
.eq(Cat(spec
[:2], self
.reg_in
))
170 # Scalar: not shifted up, extra in MSBs RA | (spec[0:1] << 5)
171 comb
+= self
.reg_out
.eq(Cat(self
.reg_in
, spec
[:2]))
176 class SVP64CRExtra(SVP64ExtraSpec
):
177 """SVP64CRExtra - decodes SVP64 Extra fields to determine CR extension
179 incoming 3-bit CR is turned into a 7-bit and marked as scalar/vector
180 depending on info in one of the positions in the EXTRA field.
182 yes, really, 128 CRs. INT is 128, FP is 128, therefore CRs are 128.
184 designed so that "no change" to the 3-bit CR register number occurs if
185 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
187 see https://libre-soc.org/openpower/sv/svp64/appendix
190 SVP64ExtraSpec
.__init
__(self
)
191 self
.cr_in
= Signal(3) # incoming CR number (3 bits, BA[2:5], BFA)
192 self
.cr_out
= Signal(7) # extra-augmented CR output (7 bits)
193 self
.isvec
= Signal(1) # reg is marked as vector if true
195 def elaborate(self
, platform
):
196 m
= super().elaborate(platform
) # select required EXTRA2/3
199 # first get the spec. if not changed it's "scalar identity behaviour"
200 # which is zero which is ok.
203 # now decode it. bit 2 is "scalar/vector". note that spec could be zero
204 # from above, which (by design) has the effect of "no change", below.
206 # simple: isvec is top bit of spec
207 comb
+= self
.isvec
.eq(spec
[2])
209 # decode vector differently from scalar, insert bits 0 and 1 accordingly
210 with m
.If(self
.isvec
):
211 # Vector: shifted up, extra in LSBs (CR << 4) | (spec[0:1] << 2)
212 comb
+= self
.cr_out
.eq(Cat(Const(0, 2), spec
[:2], self
.cr_in
))
214 # Scalar: not shifted up, extra in MSBs CR | (spec[0:1] << 3)
215 comb
+= self
.cr_out
.eq(Cat(self
.cr_in
, spec
[:2]))
220 class DecodeA(Elaboratable
):
221 """DecodeA from instruction
223 decodes register RA, implicit and explicit CSRs
226 def __init__(self
, dec
):
228 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
229 self
.insn_in
= Signal(32, reset_less
=True)
230 self
.reg_out
= Data(5, name
="reg_a")
231 self
.spr_out
= Data(SPR
, "spr_a")
232 self
.fast_out
= Data(3, "fast_a")
234 def elaborate(self
, platform
):
239 m
.submodules
.sprmap
= sprmap
= SPRMap()
241 # select Register A field
242 ra
= Signal(5, reset_less
=True)
243 comb
+= ra
.eq(self
.dec
.RA
)
244 with m
.If((self
.sel_in
== In1Sel
.RA
) |
245 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
246 (ra
!= Const(0, 5)))):
247 comb
+= reg
.data
.eq(ra
)
250 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
251 # moved it to 1st position (in1_sel)... because
252 rs
= Signal(5, reset_less
=True)
253 comb
+= rs
.eq(self
.dec
.RS
)
254 with m
.If(self
.sel_in
== In1Sel
.RS
):
255 comb
+= reg
.data
.eq(rs
)
258 # decode Fast-SPR based on instruction type
259 with m
.Switch(op
.internal_op
):
261 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
262 with m
.Case(MicrOp
.OP_BC
):
263 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
265 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
266 comb
+= self
.fast_out
.ok
.eq(1)
267 with m
.Case(MicrOp
.OP_BCREG
):
268 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
269 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
270 with m
.If(xo9
& ~xo5
):
272 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
273 comb
+= self
.fast_out
.ok
.eq(1)
275 # MFSPR move from SPRs
276 with m
.Case(MicrOp
.OP_MFSPR
):
277 spr
= Signal(10, reset_less
=True)
278 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
279 comb
+= sprmap
.spr_i
.eq(spr
)
280 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
281 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
286 class DecodeAImm(Elaboratable
):
287 """DecodeA immediate from instruction
289 decodes register RA, whether immediate-zero, implicit and
293 def __init__(self
, dec
):
295 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
296 self
.immz_out
= Signal(reset_less
=True)
298 def elaborate(self
, platform
):
302 # zero immediate requested
303 ra
= Signal(5, reset_less
=True)
304 comb
+= ra
.eq(self
.dec
.RA
)
305 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) & (ra
== Const(0, 5))):
306 comb
+= self
.immz_out
.eq(1)
311 class DecodeB(Elaboratable
):
312 """DecodeB from instruction
314 decodes register RB, different forms of immediate (signed, unsigned),
315 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
316 by industry-standard convention, "lane 2" is where fully-decoded
317 immediates are muxed in.
320 def __init__(self
, dec
):
322 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
323 self
.insn_in
= Signal(32, reset_less
=True)
324 self
.reg_out
= Data(7, "reg_b")
325 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
326 self
.fast_out
= Data(3, "fast_b")
328 def elaborate(self
, platform
):
334 # select Register B field
335 with m
.Switch(self
.sel_in
):
336 with m
.Case(In2Sel
.RB
):
337 comb
+= reg
.data
.eq(self
.dec
.RB
)
339 with m
.Case(In2Sel
.RS
):
340 # for M-Form shiftrot
341 comb
+= reg
.data
.eq(self
.dec
.RS
)
344 # decode SPR2 based on instruction type
345 # BCREG implicitly uses LR or TAR for 2nd reg
346 # CTR however is already in fast_spr1 *not* 2.
347 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
348 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
349 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
351 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
352 comb
+= self
.fast_out
.ok
.eq(1)
354 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
355 comb
+= self
.fast_out
.ok
.eq(1)
360 class DecodeBImm(Elaboratable
):
361 """DecodeB immediate from instruction
363 def __init__(self
, dec
):
365 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
366 self
.imm_out
= Data(64, "imm_b")
368 def elaborate(self
, platform
):
372 # select Register B Immediate
373 with m
.Switch(self
.sel_in
):
374 with m
.Case(In2Sel
.CONST_UI
): # unsigned
375 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
376 comb
+= self
.imm_out
.ok
.eq(1)
377 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
378 si
= Signal(16, reset_less
=True)
379 comb
+= si
.eq(self
.dec
.SI
)
380 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
381 comb
+= self
.imm_out
.ok
.eq(1)
382 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
383 si_hi
= Signal(32, reset_less
=True)
384 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
385 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
386 comb
+= self
.imm_out
.ok
.eq(1)
387 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
388 ui
= Signal(16, reset_less
=True)
389 comb
+= ui
.eq(self
.dec
.UI
)
390 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
391 comb
+= self
.imm_out
.ok
.eq(1)
392 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
393 li
= Signal(26, reset_less
=True)
394 comb
+= li
.eq(self
.dec
.LI
<< 2)
395 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
396 comb
+= self
.imm_out
.ok
.eq(1)
397 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
398 bd
= Signal(16, reset_less
=True)
399 comb
+= bd
.eq(self
.dec
.BD
<< 2)
400 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
401 comb
+= self
.imm_out
.ok
.eq(1)
402 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
403 ds
= Signal(16, reset_less
=True)
404 comb
+= ds
.eq(self
.dec
.DS
<< 2)
405 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
406 comb
+= self
.imm_out
.ok
.eq(1)
407 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
408 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
409 comb
+= self
.imm_out
.ok
.eq(1)
410 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
411 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
412 comb
+= self
.imm_out
.ok
.eq(1)
413 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
414 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
415 comb
+= self
.imm_out
.ok
.eq(1)
420 class DecodeC(Elaboratable
):
421 """DecodeC from instruction
423 decodes register RC. this is "lane 3" into some CompUnits (not many)
426 def __init__(self
, dec
):
428 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
429 self
.insn_in
= Signal(32, reset_less
=True)
430 self
.reg_out
= Data(5, "reg_c")
432 def elaborate(self
, platform
):
438 # select Register C field
439 with m
.Switch(self
.sel_in
):
440 with m
.Case(In3Sel
.RB
):
441 # for M-Form shiftrot
442 comb
+= reg
.data
.eq(self
.dec
.RB
)
444 with m
.Case(In3Sel
.RS
):
445 comb
+= reg
.data
.eq(self
.dec
.RS
)
451 class DecodeOut(Elaboratable
):
452 """DecodeOut from instruction
454 decodes output register RA, RT or SPR
457 def __init__(self
, dec
):
459 self
.sel_in
= Signal(OutSel
, reset_less
=True)
460 self
.insn_in
= Signal(32, reset_less
=True)
461 self
.reg_out
= Data(5, "reg_o")
462 self
.spr_out
= Data(SPR
, "spr_o")
463 self
.fast_out
= Data(3, "fast_o")
465 def elaborate(self
, platform
):
468 m
.submodules
.sprmap
= sprmap
= SPRMap()
472 # select Register out field
473 with m
.Switch(self
.sel_in
):
474 with m
.Case(OutSel
.RT
):
475 comb
+= reg
.data
.eq(self
.dec
.RT
)
477 with m
.Case(OutSel
.RA
):
478 comb
+= reg
.data
.eq(self
.dec
.RA
)
480 with m
.Case(OutSel
.SPR
):
481 spr
= Signal(10, reset_less
=True)
482 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
483 # MFSPR move to SPRs - needs mapping
484 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
485 comb
+= sprmap
.spr_i
.eq(spr
)
486 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
487 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
490 with m
.Switch(op
.internal_op
):
492 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
493 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
494 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
496 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
497 comb
+= self
.fast_out
.ok
.eq(1)
499 # RFID 1st spr (fast)
500 with m
.Case(MicrOp
.OP_RFID
):
501 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
502 comb
+= self
.fast_out
.ok
.eq(1)
507 class DecodeOut2(Elaboratable
):
508 """DecodeOut2 from instruction
510 decodes output registers (2nd one). note that RA is *implicit* below,
511 which now causes problems with SVP64
513 TODO: SVP64 is a little more complex, here. svp64 allows extending
514 by one more destination by having one more EXTRA field. RA-as-src
515 is not the same as RA-as-dest. limited in that it's the same first
516 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
517 for operations that have src-as-dest: mostly this is LD/ST-with-update
518 but there are others.
521 def __init__(self
, dec
):
523 self
.sel_in
= Signal(OutSel
, reset_less
=True)
524 self
.lk
= Signal(reset_less
=True)
525 self
.insn_in
= Signal(32, reset_less
=True)
526 self
.reg_out
= Data(5, "reg_o2")
527 self
.fast_out
= Data(3, "fast_o2")
529 def elaborate(self
, platform
):
533 #m.submodules.svdec = svdec = SVP64RegExtra()
535 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
536 #reg = Signal(5, reset_less=True)
538 if hasattr(self
.dec
.op
, "upd"):
539 # update mode LD/ST uses read-reg A also as an output
540 with m
.If(self
.dec
.op
.upd
== LDSTMode
.update
):
541 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
542 comb
+= self
.reg_out
.ok
.eq(1)
544 # B, BC or BCREG: potential implicit register (LR) output
545 # these give bl, bcl, bclrl, etc.
546 with m
.Switch(op
.internal_op
):
548 # BC* implicit register (LR)
549 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
550 with m
.If(self
.lk
): # "link" mode
551 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
) # constant: LR
552 comb
+= self
.fast_out
.ok
.eq(1)
554 # RFID 2nd spr (fast)
555 with m
.Case(MicrOp
.OP_RFID
):
556 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
557 comb
+= self
.fast_out
.ok
.eq(1)
562 class DecodeRC(Elaboratable
):
563 """DecodeRc from instruction
565 decodes Record bit Rc
568 def __init__(self
, dec
):
570 self
.sel_in
= Signal(RC
, reset_less
=True)
571 self
.insn_in
= Signal(32, reset_less
=True)
572 self
.rc_out
= Data(1, "rc")
574 def elaborate(self
, platform
):
578 # select Record bit out field
579 with m
.Switch(self
.sel_in
):
581 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
582 comb
+= self
.rc_out
.ok
.eq(1)
584 comb
+= self
.rc_out
.data
.eq(1)
585 comb
+= self
.rc_out
.ok
.eq(1)
586 with m
.Case(RC
.NONE
):
587 comb
+= self
.rc_out
.data
.eq(0)
588 comb
+= self
.rc_out
.ok
.eq(1)
593 class DecodeOE(Elaboratable
):
594 """DecodeOE from instruction
596 decodes OE field: uses RC decode detection which might not be good
598 -- For now, use "rc" in the decode table to decide whether oe exists.
599 -- This is not entirely correct architecturally: For mulhd and
600 -- mulhdu, the OE field is reserved. It remains to be seen what an
601 -- actual POWER9 does if we set it on those instructions, for now we
602 -- test that further down when assigning to the multiplier oe input.
605 def __init__(self
, dec
):
607 self
.sel_in
= Signal(RC
, reset_less
=True)
608 self
.insn_in
= Signal(32, reset_less
=True)
609 self
.oe_out
= Data(1, "oe")
611 def elaborate(self
, platform
):
616 with m
.Switch(op
.internal_op
):
618 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
620 # XXX ARGH! ignoring OE causes incompatibility with microwatt
621 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
622 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
623 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
624 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
625 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
626 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
630 # all other ops decode OE field
632 # select OE bit out field
633 with m
.Switch(self
.sel_in
):
635 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
636 comb
+= self
.oe_out
.ok
.eq(1)
641 class DecodeCRIn(Elaboratable
):
642 """Decodes input CR from instruction
644 CR indices - insn fields - (not the data *in* the CR) require only 3
645 bits because they refer to CR0-CR7
648 def __init__(self
, dec
):
650 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
651 self
.insn_in
= Signal(32, reset_less
=True)
652 self
.cr_bitfield
= Data(3, "cr_bitfield")
653 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
654 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
655 self
.whole_reg
= Data(8, "cr_fxm")
657 def elaborate(self
, platform
):
661 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
664 # zero-initialisation
665 comb
+= self
.cr_bitfield
.ok
.eq(0)
666 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
667 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
668 comb
+= self
.whole_reg
.ok
.eq(0)
670 # select the relevant CR bitfields
671 with m
.Switch(self
.sel_in
):
672 with m
.Case(CRInSel
.NONE
):
673 pass # No bitfield activated
674 with m
.Case(CRInSel
.CR0
):
675 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
676 comb
+= self
.cr_bitfield
.ok
.eq(1)
677 with m
.Case(CRInSel
.BI
):
678 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
679 comb
+= self
.cr_bitfield
.ok
.eq(1)
680 with m
.Case(CRInSel
.BFA
):
681 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
682 comb
+= self
.cr_bitfield
.ok
.eq(1)
683 with m
.Case(CRInSel
.BA_BB
):
684 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
685 comb
+= self
.cr_bitfield
.ok
.eq(1)
686 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
687 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
688 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
689 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
690 with m
.Case(CRInSel
.BC
):
691 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
692 comb
+= self
.cr_bitfield
.ok
.eq(1)
693 with m
.Case(CRInSel
.WHOLE_REG
):
694 comb
+= self
.whole_reg
.ok
.eq(1)
695 move_one
= Signal(reset_less
=True)
696 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
697 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
698 # must one-hot the FXM field
699 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
700 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
702 # otherwise use all of it
703 comb
+= self
.whole_reg
.data
.eq(0xff)
708 class DecodeCROut(Elaboratable
):
709 """Decodes input CR from instruction
711 CR indices - insn fields - (not the data *in* the CR) require only 3
712 bits because they refer to CR0-CR7
715 def __init__(self
, dec
):
717 self
.rc_in
= Signal(reset_less
=True)
718 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
719 self
.insn_in
= Signal(32, reset_less
=True)
720 self
.cr_bitfield
= Data(3, "cr_bitfield")
721 self
.whole_reg
= Data(8, "cr_fxm")
723 def elaborate(self
, platform
):
727 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
730 comb
+= self
.cr_bitfield
.ok
.eq(0)
731 comb
+= self
.whole_reg
.ok
.eq(0)
733 with m
.Switch(self
.sel_in
):
734 with m
.Case(CROutSel
.NONE
):
735 pass # No bitfield activated
736 with m
.Case(CROutSel
.CR0
):
737 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
738 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
739 with m
.Case(CROutSel
.BF
):
740 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
741 comb
+= self
.cr_bitfield
.ok
.eq(1)
742 with m
.Case(CROutSel
.BT
):
743 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
744 comb
+= self
.cr_bitfield
.ok
.eq(1)
745 with m
.Case(CROutSel
.WHOLE_REG
):
746 comb
+= self
.whole_reg
.ok
.eq(1)
747 move_one
= Signal(reset_less
=True)
748 comb
+= move_one
.eq(self
.insn_in
[20])
749 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
751 # must one-hot the FXM field
752 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
753 with m
.If(ppick
.en_o
):
754 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
756 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
758 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
760 # otherwise use all of it
761 comb
+= self
.whole_reg
.data
.eq(0xff)
765 # dictionary of Input Record field names that, if they exist,
766 # will need a corresponding CSV Decoder file column (actually, PowerOp)
767 # to be decoded (this includes the single bit names)
768 record_names
= {'insn_type': 'internal_op',
769 'fn_unit': 'function_unit',
773 'imm_data': 'in2_sel',
774 'invert_in': 'inv_a',
775 'invert_out': 'inv_out',
778 'output_carry': 'cry_out',
779 'input_carry': 'cry_in',
780 'is_32bit': 'is_32b',
783 'data_len': 'ldst_len',
784 'byte_reverse': 'br',
785 'sign_extend': 'sgn_ext',
790 class PowerDecodeSubset(Elaboratable
):
791 """PowerDecodeSubset: dynamic subset decoder
793 only fields actually requested are copied over. hence, "subset" (duh).
795 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
797 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
800 self
.fn_name
= fn_name
802 opkls
= Decode2ToOperand
803 self
.do
= opkls(fn_name
)
804 col_subset
= self
.get_col_subset(self
.do
)
806 # only needed for "main" PowerDecode2
808 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
)
810 # create decoder if one not already given
812 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
813 row_subset
=self
.rowsubsetfn
)
816 # state information needed by the Decoder
818 state
= CoreState("dec2")
821 def get_col_subset(self
, do
):
822 subset
= { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
823 for k
, v
in record_names
.items():
826 print ("get_col_subset", self
.fn_name
, do
.fields
, subset
)
829 def rowsubsetfn(self
, opcode
, row
):
830 return row
['unit'] == self
.fn_name
833 return self
.dec
.ports() + self
.e
.ports() + self
.sv_rm
.ports()
835 def needs_field(self
, field
, op_field
):
840 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
842 def do_copy(self
, field
, val
, final
=False):
843 if final
or self
.final
:
847 if hasattr(do
, field
) and val
is not None:
848 return getattr(do
, field
).eq(val
)
851 def op_get(self
, op_field
):
852 return getattr(self
.dec
.op
, op_field
, None)
854 def elaborate(self
, platform
):
858 op
, do
= self
.dec
.op
, self
.do
859 msr
, cia
= state
.msr
, state
.pc
861 # fill in for a normal instruction (not an exception)
862 # copy over if non-exception, non-privileged etc. is detected
864 if self
.fn_name
is None:
867 name
= self
.fn_name
+ "tmp"
868 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
)
870 # set up submodule decoders
871 m
.submodules
.dec
= self
.dec
872 m
.submodules
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
873 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
874 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
)
875 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
)
877 # copy instruction through...
879 dec_rc
.insn_in
, dec_oe
.insn_in
,
880 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
]:
881 comb
+= i
.eq(self
.dec
.opcode_in
)
883 # ...and subdecoders' input fields
884 comb
+= dec_rc
.sel_in
.eq(op
.rc_sel
)
885 comb
+= dec_oe
.sel_in
.eq(op
.rc_sel
) # XXX should be OE sel
886 comb
+= self
.dec_cr_in
.sel_in
.eq(op
.cr_in
)
887 comb
+= self
.dec_cr_out
.sel_in
.eq(op
.cr_out
)
888 comb
+= self
.dec_cr_out
.rc_in
.eq(dec_rc
.rc_out
.data
)
891 comb
+= self
.do_copy("msr", msr
)
892 comb
+= self
.do_copy("cia", cia
)
894 # set up instruction type
895 # no op: defaults to OP_ILLEGAL
896 if self
.fn_name
=="MMU":
897 # mmu is special case: needs SPR opcode as well
898 mmu0
= self
.mmu0_spr_dec
899 with m
.If(((mmu0
.dec
.op
.internal_op
== MicrOp
.OP_MTSPR
) |
900 (mmu0
.dec
.op
.internal_op
== MicrOp
.OP_MFSPR
))):
901 comb
+= self
.do_copy("insn_type", mmu0
.op_get("internal_op"))
903 comb
+= self
.do_copy("insn_type", self
.op_get("internal_op"))
905 comb
+= self
.do_copy("insn_type", self
.op_get("internal_op"))
907 # function unit for decoded instruction: requires minor redirect
909 fn
= self
.op_get("function_unit")
910 spr
= Signal(10, reset_less
=True)
911 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
913 SPR_PID
= 48 # TODO read docs for POWER9
914 # Microwatt doesn't implement the partition table
915 # instead has PRTBL register (SPR) to point to process table
916 SPR_PRTBL
= 720 # see common.vhdl in microwatt, not in POWER9
917 with m
.If(((self
.dec
.op
.internal_op
== MicrOp
.OP_MTSPR
) |
918 (self
.dec
.op
.internal_op
== MicrOp
.OP_MFSPR
)) &
919 ((spr
== SPR
.DSISR
) |
(spr
== SPR
.DAR
)
920 |
(spr
==SPR_PRTBL
) |
(spr
==SPR_PID
))):
921 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
923 comb
+= self
.do_copy("fn_unit",fn
)
926 if self
.needs_field("zero_a", "in1_sel"):
927 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
928 comb
+= dec_ai
.sel_in
.eq(op
.in1_sel
)
929 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
930 if self
.needs_field("imm_data", "in2_sel"):
931 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
932 comb
+= dec_bi
.sel_in
.eq(op
.in2_sel
)
933 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
936 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
937 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
940 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
941 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
942 comb
+= self
.do_copy("write_cr0", self
.dec_cr_out
.cr_bitfield
.ok
)
944 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
945 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
947 # decoded/selected instruction flags
948 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
949 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
950 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
951 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
952 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
953 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
954 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
955 lk
= self
.op_get("lk")
958 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
960 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
961 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
962 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
967 class PowerDecode2(PowerDecodeSubset
):
968 """PowerDecode2: the main instruction decoder.
970 whilst PowerDecode is responsible for decoding the actual opcode, this
971 module encapsulates further specialist, sparse information and
972 expansion of fields that is inconvenient to have in the CSV files.
973 for example: the encoding of the immediates, which are detected
974 and expanded out to their full value from an annotated (enum)
977 implicit register usage is also set up, here. for example: OP_BC
978 requires implicitly reading CTR, OP_RFID requires implicitly writing
981 in addition, PowerDecoder2 is responsible for detecting whether
982 instructions are illegal (or privileged) or not, and instead of
983 just leaving at that, *replacing* the instruction to execute with
984 a suitable alternative (trap).
986 LDSTExceptions are done the cycle _after_ they're detected (after
987 they come out of LDSTCompUnit). basically despite the instruction
988 being decoded, the results of the decode are completely ignored
989 and "exception.happened" used to set the "actual" instruction to
990 "OP_TRAP". the LDSTException data structure gets filled in,
991 in the CompTrapOpSubset and that's what it fills in SRR.
993 to make this work, TestIssuer must notice "exception.happened"
994 after the (failed) LD/ST and copies the LDSTException info from
995 the output, into here (PowerDecoder2). without incrementing PC.
998 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
999 super().__init
__(dec
, opkls
, fn_name
, final
, state
)
1000 self
.exc
= LDSTException("dec2_exc")
1002 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
1003 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
1004 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1005 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1006 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1007 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1008 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1009 self
.o_isvec
= Signal(1, name
="reg_o_isvec")
1010 self
.o2_isvec
= Signal(1, name
="reg_o2_isvec")
1011 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs are vectors
1013 def get_col_subset(self
, opkls
):
1014 subset
= super().get_col_subset(opkls
)
1015 subset
.add("asmcode")
1016 subset
.add("in1_sel")
1017 subset
.add("in2_sel")
1018 subset
.add("in3_sel")
1019 subset
.add("out_sel")
1020 subset
.add("sv_in1")
1021 subset
.add("sv_in2")
1022 subset
.add("sv_in3")
1023 subset
.add("sv_out")
1024 subset
.add("sv_cr_in")
1025 subset
.add("sv_cr_out")
1026 subset
.add("SV_Etype")
1027 subset
.add("SV_Ptype")
1029 subset
.add("internal_op")
1033 def elaborate(self
, platform
):
1034 m
= super().elaborate(platform
)
1037 e_out
, op
, do_out
= self
.e
, self
.dec
.op
, self
.e
.do
1038 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1042 # fill in for a normal instruction (not an exception)
1043 # copy over if non-exception, non-privileged etc. is detected
1045 # set up submodule decoders
1046 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
1047 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
1048 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
1049 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
1050 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
)
1052 # and SVP64 Extra decoders
1053 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1054 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1055 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1056 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1057 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1058 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1059 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1060 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1061 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1063 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1064 reg
= Signal(5, reset_less
=True)
1066 # copy instruction through...
1067 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1068 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1069 comb
+= i
.eq(self
.dec
.opcode_in
)
1071 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1072 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1073 # which in turn were auto-generated by sv_analysis.py
1074 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1078 comb
+= crout_svdec
.idx
.eq(op
.sv_cr_out
) # SVP64 CR out
1079 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1082 # CR in - index selection slightly different due to shared CR field sigh
1083 cr_a_idx
= Signal(SVEXTRA
)
1084 cr_b_idx
= Signal(SVEXTRA
)
1086 # these change slightly, when decoding BA/BB. really should have
1087 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1088 comb
+= cr_a_idx
.eq(op
.sv_cr_in
)
1089 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1090 with m
.If(op
.sv_cr_in
== SVEXTRA
.Idx_1_2
.value
):
1091 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1092 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1094 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1095 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1096 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1098 # indices are slightly different, BA/BB mess sorted above
1099 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1100 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1101 comb
+= crin_svdec_o
.idx
.eq(op
.sv_cr_out
) # SVP64 CR out
1103 # ...and subdecoders' input fields
1104 comb
+= dec_a
.sel_in
.eq(op
.in1_sel
)
1105 comb
+= dec_b
.sel_in
.eq(op
.in2_sel
)
1106 comb
+= dec_c
.sel_in
.eq(op
.in3_sel
)
1107 comb
+= dec_o
.sel_in
.eq(op
.out_sel
)
1108 comb
+= dec_o2
.sel_in
.eq(op
.out_sel
)
1109 if hasattr(do
, "lk"):
1110 comb
+= dec_o2
.lk
.eq(do
.lk
)
1112 # get SVSTATE srcstep (TODO: elwidth, dststep etc.) needed below
1113 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1114 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1116 # registers a, b, c and out and out2 (LD/ST EA)
1117 for to_reg
, fromreg
, svdec
in (
1118 (e
.read_reg1
, dec_a
.reg_out
, in1_svdec
),
1119 (e
.read_reg2
, dec_b
.reg_out
, in2_svdec
),
1120 (e
.read_reg3
, dec_c
.reg_out
, in3_svdec
),
1121 (e
.write_reg
, dec_o
.reg_out
, o_svdec
),
1122 (e
.write_ea
, dec_o2
.reg_out
, o2_svdec
)):
1123 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1124 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
1125 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1126 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1127 # detect if Vectorised: add srcstep if yes. TODO: a LOT.
1128 # this trick only holds when elwidth=default and in single-pred
1129 with m
.If(svdec
.isvec
):
1130 comb
+= to_reg
.data
.eq(srcstep
+svdec
.reg_out
) # 7-bit output
1132 comb
+= to_reg
.data
.eq(svdec
.reg_out
) # 7-bit output
1134 comb
+= in1_svdec
.idx
.eq(op
.sv_in1
) # SVP64 reg #1 (matches in1_sel)
1135 comb
+= in2_svdec
.idx
.eq(op
.sv_in2
) # SVP64 reg #2 (matches in2_sel)
1136 comb
+= in3_svdec
.idx
.eq(op
.sv_in3
) # SVP64 reg #3 (matches in3_sel)
1137 comb
+= o_svdec
.idx
.eq(op
.sv_out
) # SVP64 output (matches out_sel)
1138 # XXX TODO - work out where this should come from. the problem is
1139 # that LD-with-update is implied (computed from "is instruction in
1140 # "update mode" rather than specified cleanly as its own CSV column
1141 #comb += o2_svdec.idx.eq(op.sv_out) # SVP64 output (implicit)
1143 # output reg-is-vectorised (and when no output is vectorised)
1144 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1145 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1146 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1147 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1148 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1149 # TODO: include SPRs and CRs here! must be True when *all* are scalar
1150 comb
+= self
.no_out_vec
.eq((~o2_svdec
.isvec
) & (~o_svdec
.isvec
))
1153 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1154 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1157 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1158 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1159 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
)
1160 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
)
1162 # condition registers (CR)
1163 for to_reg
, fromreg
, svdec
in (
1164 (e
.read_cr1
, self
.dec_cr_in
.cr_bitfield
, crin_svdec
),
1165 (e
.read_cr2
, self
.dec_cr_in
.cr_bitfield_b
, crin_svdec_b
),
1166 (e
.read_cr3
, self
.dec_cr_in
.cr_bitfield_o
, crin_svdec_o
),
1167 (e
.write_cr
, self
.dec_cr_out
.cr_bitfield
, crout_svdec
)):
1168 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1169 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
1170 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1171 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1172 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1174 # sigh this is exactly the sort of thing for which the
1175 # decoder is designed to not need. MTSPR, MFSPR and others need
1176 # access to the XER bits. however setting e.oe is not appropriate
1177 with m
.If(op
.internal_op
== MicrOp
.OP_MFSPR
):
1178 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1179 with m
.If(op
.internal_op
== MicrOp
.OP_CMP
):
1180 comb
+= e
.xer_in
.eq(1<<XERRegs
.SO
) # SO
1181 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
1182 comb
+= e
.xer_out
.eq(1)
1184 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1185 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1186 # *DO NOT* call self.trap here. that would reset absolutely
1187 # everything including destroying read of RA and RB.
1188 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1190 ####################
1191 # ok so the instruction's been decoded, blah blah, however
1192 # now we need to determine if it's actually going to go ahead...
1193 # *or* if in fact it's a privileged operation, whether there's
1194 # an external interrupt, etc. etc. this is a simple priority
1195 # if-elif-elif sequence. decrement takes highest priority,
1196 # EINT next highest, privileged operation third.
1198 # check if instruction is privileged
1199 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1201 # different IRQ conditions
1202 ext_irq_ok
= Signal()
1203 dec_irq_ok
= Signal()
1208 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1209 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1210 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1211 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1213 # LD/ST exceptions. TestIssuer copies the exception info at us
1214 # after a failed LD/ST.
1215 with m
.If(exc
.happened
):
1216 with m
.If(exc
.alignment
):
1217 self
.trap(m
, TT
.PRIV
, 0x600)
1218 with m
.Elif(exc
.instr_fault
):
1219 with m
.If(exc
.segment_fault
):
1220 self
.trap(m
, TT
.PRIV
, 0x480)
1222 # pass exception info to trap to create SRR1
1223 self
.trap(m
, TT
.MEMEXC
, 0x400, exc
)
1225 with m
.If(exc
.segment_fault
):
1226 self
.trap(m
, TT
.PRIV
, 0x380)
1228 self
.trap(m
, TT
.PRIV
, 0x300)
1230 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1231 with m
.Elif(dec_irq_ok
):
1232 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1234 # external interrupt? only if MSR.EE set
1235 with m
.Elif(ext_irq_ok
):
1236 self
.trap(m
, TT
.EINT
, 0x500)
1238 # privileged instruction trap
1239 with m
.Elif(priv_ok
):
1240 self
.trap(m
, TT
.PRIV
, 0x700)
1242 # illegal instruction must redirect to trap. this is done by
1243 # *overwriting* the decoded instruction and starting again.
1244 # (note: the same goes for interrupts and for privileged operations,
1245 # just with different trapaddr and traptype)
1246 with m
.Elif(illeg_ok
):
1247 # illegal instruction trap
1248 self
.trap(m
, TT
.ILLEG
, 0x700)
1250 # no exception, just copy things to the output
1254 ####################
1255 # follow-up after trap/irq to set up SRR0/1
1257 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1258 # Note: OP_SC could actually be modified to just be a trap
1259 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1260 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1261 # TRAP write fast1 = SRR0
1262 comb
+= e_out
.write_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1263 comb
+= e_out
.write_fast1
.ok
.eq(1)
1264 # TRAP write fast2 = SRR1
1265 comb
+= e_out
.write_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1266 comb
+= e_out
.write_fast2
.ok
.eq(1)
1268 # RFID: needs to read SRR0/1
1269 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1270 # TRAP read fast1 = SRR0
1271 comb
+= e_out
.read_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1272 comb
+= e_out
.read_fast1
.ok
.eq(1)
1273 # TRAP read fast2 = SRR1
1274 comb
+= e_out
.read_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1275 comb
+= e_out
.read_fast2
.ok
.eq(1)
1277 # annoying simulator bug
1278 if hasattr(e_out
, "asmcode") and hasattr(self
.dec
.op
, "asmcode"):
1279 comb
+= e_out
.asmcode
.eq(self
.dec
.op
.asmcode
)
1283 def trap(self
, m
, traptype
, trapaddr
, exc
=None):
1284 """trap: this basically "rewrites" the decoded instruction as a trap
1287 op
, e
= self
.dec
.op
, self
.e
1288 comb
+= e
.eq(0) # reset eeeeeverything
1291 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1292 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1293 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1294 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1295 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1296 comb
+= self
.do_copy("ldst_exc", exc
, True) # request type
1297 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # copy of MSR "state"
1298 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1301 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
1302 # identifies if an instruction is a SVP64-encoded prefix, and extracts
1303 # the 24-bit SVP64 context (RM) if it is
1304 class SVP64PrefixDecoder(Elaboratable
):
1307 self
.opcode_in
= Signal(32, reset_less
=True)
1308 self
.raw_opcode_in
= Signal
.like(self
.opcode_in
, reset_less
=True)
1309 self
.is_svp64_mode
= Signal(1, reset_less
=True)
1310 self
.svp64_rm
= Signal(24, reset_less
=True)
1311 self
.bigendian
= Signal(reset_less
=True)
1313 def elaborate(self
, platform
):
1315 opcode_in
= self
.opcode_in
1317 # sigh copied this from TopPowerDecoder
1318 # raw opcode in assumed to be in LE order: byte-reverse it to get BE
1319 raw_le
= self
.raw_opcode_in
1321 for i
in range(0, 32, 8):
1322 l
.append(raw_le
[i
:i
+8])
1325 comb
+= opcode_in
.eq(Mux(self
.bigendian
, raw_be
, raw_le
))
1327 # start identifying if the incoming opcode is SVP64 prefix)
1328 major
= Signal(6, reset_less
=True)
1329 ident
= Signal(2, reset_less
=True)
1331 comb
+= major
.eq(sel(opcode_in
, SVP64P
.OPC
))
1332 comb
+= ident
.eq(sel(opcode_in
, SVP64P
.SVP64_7_9
))
1334 comb
+= self
.is_svp64_mode
.eq(
1335 (major
== Const(1, 6)) & # EXT01
1336 (ident
== Const(0b11, 2)) # identifier bits
1339 with m
.If(self
.is_svp64_mode
):
1340 # now grab the 24-bit ReMap context bits,
1341 comb
+= self
.svp64_rm
.eq(sel(opcode_in
, SVP64P
.RM
))
1346 return [self
.opcode_in
, self
.raw_opcode_in
, self
.is_svp64_mode
,
1347 self
.svp64_rm
, self
.bigendian
]
1349 def get_rdflags(e
, cu
):
1351 for idx
in range(cu
.n_src
):
1352 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1353 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
1355 print("rdflags", rdl
)
1359 if __name__
== '__main__':
1360 svp64
= SVP64PowerDecoder()
1361 vl
= rtlil
.convert(svp64
, ports
=svp64
.ports())
1362 with
open("svp64_dec.il", "w") as f
:
1364 pdecode
= create_pdecode()
1365 dec2
= PowerDecode2(pdecode
)
1366 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1367 with
open("dec2.il", "w") as f
: