src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
   6 over-riding the internal opcode when an exception is needed.
   7 """
   8
   9 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
  10 from nmigen.cli import rtlil
  11 from nmutil.util import sel
  12
  13 from soc.regfile.regfiles import XERRegs
  14
  15 from nmutil.picker import PriorityPicker
  16 from nmutil.iocontrol import RecordObject
  17 from nmutil.extend import exts
  18
  19 from soc.experiment.mem_types import LDSTException
  20
  21 from soc.decoder.power_svp64_prefix import SVP64PrefixDecoder
  22 from soc.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
  23 from soc.decoder.power_svp64_rm import SVP64RMModeDecode
  24 from soc.decoder.power_regspec_map import regspec_decode_read
  25 from soc.decoder.power_regspec_map import regspec_decode_write
  26 from soc.decoder.power_decoder import create_pdecode
  27 from soc.decoder.power_enums import (MicrOp, CryIn, Function,
  28                                      CRInSel, CROutSel,
  29                                      LdstLen, In1Sel, In2Sel, In3Sel,
  30                                      OutSel, SPR, RC, LDSTMode,
  31                                      SVEXTRA, SVEtype, SVPtype)
  32 from soc.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
  33                                          Decode2ToOperand)
  34 from soc.sv.svp64 import SVP64Rec
  35 from soc.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field,
  36                         SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs)
  37
  38 from soc.regfile.regfiles import FastRegs
  39 from soc.consts import TT
  40 from soc.config.state import CoreState
  41 from soc.regfile.util import spr_to_fast
  42
  43
  44 def decode_spr_num(spr):
  45     return Cat(spr[5:10], spr[0:5])
  46
  47
  48 def instr_is_priv(m, op, insn):
  49     """determines if the instruction is privileged or not
  50     """
  51     comb = m.d.comb
  52     is_priv_insn = Signal(reset_less=True)
  53     with m.Switch(op):
  54         with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
  55                     MicrOp.OP_MTMSR, MicrOp.OP_RFID):
  56             comb += is_priv_insn.eq(1)
  57         with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
  58         with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):
  59             with m.If(insn[20]):  # field XFX.spr[-1] i think
  60                 comb += is_priv_insn.eq(1)
  61     return is_priv_insn
  62
  63
  64 class SPRMap(Elaboratable):
  65     """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
  66     """
  67
  68     def __init__(self):
  69         self.spr_i = Signal(10, reset_less=True)
  70         self.spr_o = Data(SPR, name="spr_o")
  71         self.fast_o = Data(3, name="fast_o")
  72
  73     def elaborate(self, platform):
  74         m = Module()
  75         with m.Switch(self.spr_i):
  76             for i, x in enumerate(SPR):
  77                 with m.Case(x.value):
  78                     m.d.comb += self.spr_o.data.eq(i)
  79                     m.d.comb += self.spr_o.ok.eq(1)
  80             for x, v in spr_to_fast.items():
  81                 with m.Case(x.value):
  82                     m.d.comb += self.fast_o.data.eq(v)
  83                     m.d.comb += self.fast_o.ok.eq(1)
  84         return m
  85
  86
  87 class DecodeA(Elaboratable):
  88     """DecodeA from instruction
  89
  90     decodes register RA, implicit and explicit CSRs
  91     """
  92
  93     def __init__(self, dec):
  94         self.dec = dec
  95         self.sel_in = Signal(In1Sel, reset_less=True)
  96         self.insn_in = Signal(32, reset_less=True)
  97         self.reg_out = Data(5, name="reg_a")
  98         self.spr_out = Data(SPR, "spr_a")
  99         self.fast_out = Data(3, "fast_a")
 100         self.sv_nz = Signal(1)
 101
 102     def elaborate(self, platform):
 103         m = Module()
 104         comb = m.d.comb
 105         op = self.dec.op
 106         reg = self.reg_out
 107         m.submodules.sprmap = sprmap = SPRMap()
 108
 109         # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
 110         ra = Signal(5, reset_less=True)
 111         comb += ra.eq(self.dec.RA)
 112         with m.If((self.sel_in == In1Sel.RA) |
 113                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
 114                    ((ra != Const(0, 5)) | (self.sv_nz != Const(0, 1))))):
 115             comb += reg.data.eq(ra)
 116             comb += reg.ok.eq(1)
 117
 118         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
 119         # moved it to 1st position (in1_sel)... because
 120         rs = Signal(5, reset_less=True)
 121         comb += rs.eq(self.dec.RS)
 122         with m.If(self.sel_in == In1Sel.RS):
 123             comb += reg.data.eq(rs)
 124             comb += reg.ok.eq(1)
 125
 126         # decode Fast-SPR based on instruction type
 127         with m.Switch(op.internal_op):
 128
 129             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
 130             with m.Case(MicrOp.OP_BC):
 131                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 132                     # constant: CTR
 133                     comb += self.fast_out.data.eq(FastRegs.CTR)
 134                     comb += self.fast_out.ok.eq(1)
 135             with m.Case(MicrOp.OP_BCREG):
 136                 xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 137                 xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 138                 with m.If(xo9 & ~xo5):
 139                     # constant: CTR
 140                     comb += self.fast_out.data.eq(FastRegs.CTR)
 141                     comb += self.fast_out.ok.eq(1)
 142
 143             # MFSPR move from SPRs
 144             with m.Case(MicrOp.OP_MFSPR):
 145                 spr = Signal(10, reset_less=True)
 146                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 147                 comb += sprmap.spr_i.eq(spr)
 148                 comb += self.spr_out.eq(sprmap.spr_o)
 149                 comb += self.fast_out.eq(sprmap.fast_o)
 150
 151         return m
 152
 153
 154 class DecodeAImm(Elaboratable):
 155     """DecodeA immediate from instruction
 156
 157     decodes register RA, whether immediate-zero, implicit and
 158     explicit CSRs.  SVP64 mode requires 2 extra bits
 159     """
 160
 161     def __init__(self, dec):
 162         self.dec = dec
 163         self.sel_in = Signal(In1Sel, reset_less=True)
 164         self.immz_out = Signal(reset_less=True)
 165         self.sv_nz = Signal(1) # EXTRA bits from SVP64
 166
 167     def elaborate(self, platform):
 168         m = Module()
 169         comb = m.d.comb
 170
 171         # zero immediate requested
 172         ra = Signal(5, reset_less=True)
 173         comb += ra.eq(self.dec.RA)
 174         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
 175                     (ra == Const(0, 5)) &
 176                     (self.sv_nz == Const(0, 1))):
 177             comb += self.immz_out.eq(1)
 178
 179         return m
 180
 181
 182 class DecodeB(Elaboratable):
 183     """DecodeB from instruction
 184
 185     decodes register RB, different forms of immediate (signed, unsigned),
 186     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 187     by industry-standard convention, "lane 2" is where fully-decoded
 188     immediates are muxed in.
 189     """
 190
 191     def __init__(self, dec):
 192         self.dec = dec
 193         self.sel_in = Signal(In2Sel, reset_less=True)
 194         self.insn_in = Signal(32, reset_less=True)
 195         self.reg_out = Data(7, "reg_b")
 196         self.reg_isvec = Signal(1, name="reg_b_isvec") # TODO: in reg_out
 197         self.fast_out = Data(3, "fast_b")
 198
 199     def elaborate(self, platform):
 200         m = Module()
 201         comb = m.d.comb
 202         op = self.dec.op
 203         reg = self.reg_out
 204
 205         # select Register B field
 206         with m.Switch(self.sel_in):
 207             with m.Case(In2Sel.RB):
 208                 comb += reg.data.eq(self.dec.RB)
 209                 comb += reg.ok.eq(1)
 210             with m.Case(In2Sel.RS):
 211                 # for M-Form shiftrot
 212                 comb += reg.data.eq(self.dec.RS)
 213                 comb += reg.ok.eq(1)
 214
 215         # decode SPR2 based on instruction type
 216         # BCREG implicitly uses LR or TAR for 2nd reg
 217         # CTR however is already in fast_spr1 *not* 2.
 218         with m.If(op.internal_op == MicrOp.OP_BCREG):
 219             xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 220             xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 221             with m.If(~xo9):
 222                 comb += self.fast_out.data.eq(FastRegs.LR)
 223                 comb += self.fast_out.ok.eq(1)
 224             with m.Elif(xo5):
 225                 comb += self.fast_out.data.eq(FastRegs.TAR)
 226                 comb += self.fast_out.ok.eq(1)
 227
 228         return m
 229
 230
 231 class DecodeBImm(Elaboratable):
 232     """DecodeB immediate from instruction
 233     """
 234     def __init__(self, dec):
 235         self.dec = dec
 236         self.sel_in = Signal(In2Sel, reset_less=True)
 237         self.imm_out = Data(64, "imm_b")
 238
 239     def elaborate(self, platform):
 240         m = Module()
 241         comb = m.d.comb
 242
 243         # select Register B Immediate
 244         with m.Switch(self.sel_in):
 245             with m.Case(In2Sel.CONST_UI): # unsigned
 246                 comb += self.imm_out.data.eq(self.dec.UI)
 247                 comb += self.imm_out.ok.eq(1)
 248             with m.Case(In2Sel.CONST_SI):  # sign-extended 16-bit
 249                 si = Signal(16, reset_less=True)
 250                 comb += si.eq(self.dec.SI)
 251                 comb += self.imm_out.data.eq(exts(si, 16, 64))
 252                 comb += self.imm_out.ok.eq(1)
 253             with m.Case(In2Sel.CONST_SI_HI):  # sign-extended 16+16=32 bit
 254                 si_hi = Signal(32, reset_less=True)
 255                 comb += si_hi.eq(self.dec.SI << 16)
 256                 comb += self.imm_out.data.eq(exts(si_hi, 32, 64))
 257                 comb += self.imm_out.ok.eq(1)
 258             with m.Case(In2Sel.CONST_UI_HI): # unsigned
 259                 ui = Signal(16, reset_less=True)
 260                 comb += ui.eq(self.dec.UI)
 261                 comb += self.imm_out.data.eq(ui << 16)
 262                 comb += self.imm_out.ok.eq(1)
 263             with m.Case(In2Sel.CONST_LI): # sign-extend 24+2=26 bit
 264                 li = Signal(26, reset_less=True)
 265                 comb += li.eq(self.dec.LI << 2)
 266                 comb += self.imm_out.data.eq(exts(li, 26, 64))
 267                 comb += self.imm_out.ok.eq(1)
 268             with m.Case(In2Sel.CONST_BD): # sign-extend (14+2)=16 bit
 269                 bd = Signal(16, reset_less=True)
 270                 comb += bd.eq(self.dec.BD << 2)
 271                 comb += self.imm_out.data.eq(exts(bd, 16, 64))
 272                 comb += self.imm_out.ok.eq(1)
 273             with m.Case(In2Sel.CONST_DS): # sign-extended (14+2=16) bit
 274                 ds = Signal(16, reset_less=True)
 275                 comb += ds.eq(self.dec.DS << 2)
 276                 comb += self.imm_out.data.eq(exts(ds, 16, 64))
 277                 comb += self.imm_out.ok.eq(1)
 278             with m.Case(In2Sel.CONST_M1): # signed (-1)
 279                 comb += self.imm_out.data.eq(~Const(0, 64))  # all 1s
 280                 comb += self.imm_out.ok.eq(1)
 281             with m.Case(In2Sel.CONST_SH): # unsigned - for shift
 282                 comb += self.imm_out.data.eq(self.dec.sh)
 283                 comb += self.imm_out.ok.eq(1)
 284             with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
 285                 comb += self.imm_out.data.eq(self.dec.SH32)
 286                 comb += self.imm_out.ok.eq(1)
 287
 288         return m
 289
 290
 291 class DecodeC(Elaboratable):
 292     """DecodeC from instruction
 293
 294     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 295     """
 296
 297     def __init__(self, dec):
 298         self.dec = dec
 299         self.sel_in = Signal(In3Sel, reset_less=True)
 300         self.insn_in = Signal(32, reset_less=True)
 301         self.reg_out = Data(5, "reg_c")
 302
 303     def elaborate(self, platform):
 304         m = Module()
 305         comb = m.d.comb
 306         op = self.dec.op
 307         reg = self.reg_out
 308
 309         # select Register C field
 310         with m.Switch(self.sel_in):
 311             with m.Case(In3Sel.RB):
 312                 # for M-Form shiftrot
 313                 comb += reg.data.eq(self.dec.RB)
 314                 comb += reg.ok.eq(1)
 315             with m.Case(In3Sel.RS):
 316                 comb += reg.data.eq(self.dec.RS)
 317                 comb += reg.ok.eq(1)
 318
 319         return m
 320
 321
 322 class DecodeOut(Elaboratable):
 323     """DecodeOut from instruction
 324
 325     decodes output register RA, RT or SPR
 326     """
 327
 328     def __init__(self, dec):
 329         self.dec = dec
 330         self.sel_in = Signal(OutSel, reset_less=True)
 331         self.insn_in = Signal(32, reset_less=True)
 332         self.reg_out = Data(5, "reg_o")
 333         self.spr_out = Data(SPR, "spr_o")
 334         self.fast_out = Data(3, "fast_o")
 335
 336     def elaborate(self, platform):
 337         m = Module()
 338         comb = m.d.comb
 339         m.submodules.sprmap = sprmap = SPRMap()
 340         op = self.dec.op
 341         reg = self.reg_out
 342
 343         # select Register out field
 344         with m.Switch(self.sel_in):
 345             with m.Case(OutSel.RT):
 346                 comb += reg.data.eq(self.dec.RT)
 347                 comb += reg.ok.eq(1)
 348             with m.Case(OutSel.RA):
 349                 comb += reg.data.eq(self.dec.RA)
 350                 comb += reg.ok.eq(1)
 351             with m.Case(OutSel.SPR):
 352                 spr = Signal(10, reset_less=True)
 353                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 354                 # MFSPR move to SPRs - needs mapping
 355                 with m.If(op.internal_op == MicrOp.OP_MTSPR):
 356                     comb += sprmap.spr_i.eq(spr)
 357                     comb += self.spr_out.eq(sprmap.spr_o)
 358                     comb += self.fast_out.eq(sprmap.fast_o)
 359
 360         # determine Fast Reg
 361         with m.Switch(op.internal_op):
 362
 363             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
 364             with m.Case(MicrOp.OP_BC, MicrOp.OP_BCREG):
 365                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 366                     # constant: CTR
 367                     comb += self.fast_out.data.eq(FastRegs.CTR)
 368                     comb += self.fast_out.ok.eq(1)
 369
 370             # RFID 1st spr (fast)
 371             with m.Case(MicrOp.OP_RFID):
 372                 comb += self.fast_out.data.eq(FastRegs.SRR0)  # constant: SRR0
 373                 comb += self.fast_out.ok.eq(1)
 374
 375         return m
 376
 377
 378 class DecodeOut2(Elaboratable):
 379     """DecodeOut2 from instruction
 380
 381     decodes output registers (2nd one).  note that RA is *implicit* below,
 382     which now causes problems with SVP64
 383
 384     TODO: SVP64 is a little more complex, here.  svp64 allows extending
 385     by one more destination by having one more EXTRA field.  RA-as-src
 386     is not the same as RA-as-dest.  limited in that it's the same first
 387     5 bits (from the v3.0B opcode), but still kinda cool.  mostly used
 388     for operations that have src-as-dest: mostly this is LD/ST-with-update
 389     but there are others.
 390     """
 391
 392     def __init__(self, dec):
 393         self.dec = dec
 394         self.sel_in = Signal(OutSel, reset_less=True)
 395         self.lk = Signal(reset_less=True)
 396         self.insn_in = Signal(32, reset_less=True)
 397         self.reg_out = Data(5, "reg_o2")
 398         self.fast_out = Data(3, "fast_o2")
 399
 400     def elaborate(self, platform):
 401         m = Module()
 402         comb = m.d.comb
 403         op = self.dec.op
 404         #m.submodules.svdec = svdec = SVP64RegExtra()
 405
 406         # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
 407         #reg = Signal(5, reset_less=True)
 408
 409         if hasattr(self.dec.op, "upd"):
 410             # update mode LD/ST uses read-reg A also as an output
 411             with m.If(self.dec.op.upd == LDSTMode.update):
 412                 comb += self.reg_out.data.eq(self.dec.RA)
 413                 comb += self.reg_out.ok.eq(1)
 414
 415         # B, BC or BCREG: potential implicit register (LR) output
 416         # these give bl, bcl, bclrl, etc.
 417         with m.Switch(op.internal_op):
 418
 419             # BC* implicit register (LR)
 420             with m.Case(MicrOp.OP_BC, MicrOp.OP_B, MicrOp.OP_BCREG):
 421                 with m.If(self.lk):  # "link" mode
 422                     comb += self.fast_out.data.eq(FastRegs.LR)  # constant: LR
 423                     comb += self.fast_out.ok.eq(1)
 424
 425             # RFID 2nd spr (fast)
 426             with m.Case(MicrOp.OP_RFID):
 427                 comb += self.fast_out.data.eq(FastRegs.SRR1)  # constant: SRR1
 428                 comb += self.fast_out.ok.eq(1)
 429
 430         return m
 431
 432
 433 class DecodeRC(Elaboratable):
 434     """DecodeRc from instruction
 435
 436     decodes Record bit Rc
 437     """
 438
 439     def __init__(self, dec):
 440         self.dec = dec
 441         self.sel_in = Signal(RC, reset_less=True)
 442         self.insn_in = Signal(32, reset_less=True)
 443         self.rc_out = Data(1, "rc")
 444
 445     def elaborate(self, platform):
 446         m = Module()
 447         comb = m.d.comb
 448
 449         # select Record bit out field
 450         with m.Switch(self.sel_in):
 451             with m.Case(RC.RC):
 452                 comb += self.rc_out.data.eq(self.dec.Rc)
 453                 comb += self.rc_out.ok.eq(1)
 454             with m.Case(RC.ONE):
 455                 comb += self.rc_out.data.eq(1)
 456                 comb += self.rc_out.ok.eq(1)
 457             with m.Case(RC.NONE):
 458                 comb += self.rc_out.data.eq(0)
 459                 comb += self.rc_out.ok.eq(1)
 460
 461         return m
 462
 463
 464 class DecodeOE(Elaboratable):
 465     """DecodeOE from instruction
 466
 467     decodes OE field: uses RC decode detection which might not be good
 468
 469     -- For now, use "rc" in the decode table to decide whether oe exists.
 470     -- This is not entirely correct architecturally: For mulhd and
 471     -- mulhdu, the OE field is reserved. It remains to be seen what an
 472     -- actual POWER9 does if we set it on those instructions, for now we
 473     -- test that further down when assigning to the multiplier oe input.
 474     """
 475
 476     def __init__(self, dec):
 477         self.dec = dec
 478         self.sel_in = Signal(RC, reset_less=True)
 479         self.insn_in = Signal(32, reset_less=True)
 480         self.oe_out = Data(1, "oe")
 481
 482     def elaborate(self, platform):
 483         m = Module()
 484         comb = m.d.comb
 485         op = self.dec.op
 486
 487         with m.Switch(op.internal_op):
 488
 489             # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
 490             # also rotate
 491             # XXX ARGH! ignoring OE causes incompatibility with microwatt
 492             # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
 493             with m.Case(MicrOp.OP_MUL_H64, MicrOp.OP_MUL_H32,
 494                         MicrOp.OP_EXTS, MicrOp.OP_CNTZ,
 495                         MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC,
 496                         MicrOp.OP_LOAD, MicrOp.OP_STORE,
 497                         MicrOp.OP_RLCL, MicrOp.OP_RLCR,
 498                         MicrOp.OP_EXTSWSLI):
 499                 pass
 500
 501             # all other ops decode OE field
 502             with m.Default():
 503                 # select OE bit out field
 504                 with m.Switch(self.sel_in):
 505                     with m.Case(RC.RC):
 506                         comb += self.oe_out.data.eq(self.dec.OE)
 507                         comb += self.oe_out.ok.eq(1)
 508
 509         return m
 510
 511
 512 class DecodeCRIn(Elaboratable):
 513     """Decodes input CR from instruction
 514
 515     CR indices - insn fields - (not the data *in* the CR) require only 3
 516     bits because they refer to CR0-CR7
 517     """
 518
 519     def __init__(self, dec):
 520         self.dec = dec
 521         self.sel_in = Signal(CRInSel, reset_less=True)
 522         self.insn_in = Signal(32, reset_less=True)
 523         self.cr_bitfield = Data(3, "cr_bitfield")
 524         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 525         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 526         self.whole_reg = Data(8,  "cr_fxm")
 527         self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
 528
 529     def elaborate(self, platform):
 530         m = Module()
 531         comb = m.d.comb
 532         op = self.dec.op
 533         m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
 534                                                        reverse_o=True)
 535
 536         # zero-initialisation
 537         comb += self.cr_bitfield.ok.eq(0)
 538         comb += self.cr_bitfield_b.ok.eq(0)
 539         comb += self.cr_bitfield_o.ok.eq(0)
 540         comb += self.whole_reg.ok.eq(0)
 541         comb += self.sv_override.eq(0)
 542
 543         # select the relevant CR bitfields
 544         with m.Switch(self.sel_in):
 545             with m.Case(CRInSel.NONE):
 546                 pass  # No bitfield activated
 547             with m.Case(CRInSel.CR0):
 548                 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
 549                 comb += self.cr_bitfield.ok.eq(1)
 550                 comb += self.sv_override.eq(1)
 551             with m.Case(CRInSel.CR1):
 552                 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
 553                 comb += self.cr_bitfield.ok.eq(1)
 554                 comb += self.sv_override.eq(2)
 555             with m.Case(CRInSel.BI):
 556                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 557                 comb += self.cr_bitfield.ok.eq(1)
 558             with m.Case(CRInSel.BFA):
 559                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 560                 comb += self.cr_bitfield.ok.eq(1)
 561             with m.Case(CRInSel.BA_BB):
 562                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 563                 comb += self.cr_bitfield.ok.eq(1)
 564                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 565                 comb += self.cr_bitfield_b.ok.eq(1)
 566                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 567                 comb += self.cr_bitfield_o.ok.eq(1)
 568             with m.Case(CRInSel.BC):
 569                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 570                 comb += self.cr_bitfield.ok.eq(1)
 571             with m.Case(CRInSel.WHOLE_REG):
 572                 comb += self.whole_reg.ok.eq(1)
 573                 move_one = Signal(reset_less=True)
 574                 comb += move_one.eq(self.insn_in[20]) # MSB0 bit 11
 575                 with m.If((op.internal_op == MicrOp.OP_MFCR) & move_one):
 576                     # must one-hot the FXM field
 577                     comb += ppick.i.eq(self.dec.FXM)
 578                     comb += self.whole_reg.data.eq(ppick.o)
 579                 with m.Else():
 580                     # otherwise use all of it
 581                     comb += self.whole_reg.data.eq(0xff)
 582
 583         return m
 584
 585
 586 class DecodeCROut(Elaboratable):
 587     """Decodes input CR from instruction
 588
 589     CR indices - insn fields - (not the data *in* the CR) require only 3
 590     bits because they refer to CR0-CR7
 591     """
 592
 593     def __init__(self, dec):
 594         self.dec = dec
 595         self.rc_in = Signal(reset_less=True)
 596         self.sel_in = Signal(CROutSel, reset_less=True)
 597         self.insn_in = Signal(32, reset_less=True)
 598         self.cr_bitfield = Data(3, "cr_bitfield")
 599         self.whole_reg = Data(8,  "cr_fxm")
 600         self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
 601
 602     def elaborate(self, platform):
 603         m = Module()
 604         comb = m.d.comb
 605         op = self.dec.op
 606         m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
 607                                                        reverse_o=True)
 608
 609         comb += self.cr_bitfield.ok.eq(0)
 610         comb += self.whole_reg.ok.eq(0)
 611         comb += self.sv_override.eq(0)
 612
 613         # please note these MUST match (setting of cr_bitfield.ok) exactly
 614         # with write_cr0 below in PowerDecoder2.  the reason it's separated
 615         # is to avoid having duplicate copies of DecodeCROut in multiple
 616         # PowerDecoderSubsets.  register decoding should be a one-off in
 617         # PowerDecoder2.  see https://bugs.libre-soc.org/show_bug.cgi?id=606
 618
 619         with m.Switch(self.sel_in):
 620             with m.Case(CROutSel.NONE):
 621                 pass  # No bitfield activated
 622             with m.Case(CROutSel.CR0):
 623                 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
 624                 comb += self.cr_bitfield.ok.eq(self.rc_in)  # only when RC=1
 625                 comb += self.sv_override.eq(1)
 626             with m.Case(CROutSel.CR1):
 627                 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
 628                 comb += self.cr_bitfield.ok.eq(self.rc_in)  # only when RC=1
 629                 comb += self.sv_override.eq(2)
 630             with m.Case(CROutSel.BF):
 631                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
 632                 comb += self.cr_bitfield.ok.eq(1)
 633             with m.Case(CROutSel.BT):
 634                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 635                 comb += self.cr_bitfield.ok.eq(1)
 636             with m.Case(CROutSel.WHOLE_REG):
 637                 comb += self.whole_reg.ok.eq(1)
 638                 move_one = Signal(reset_less=True)
 639                 comb += move_one.eq(self.insn_in[20])
 640                 with m.If((op.internal_op == MicrOp.OP_MTCRF)):
 641                     with m.If(move_one):
 642                         # must one-hot the FXM field
 643                         comb += ppick.i.eq(self.dec.FXM)
 644                         with m.If(ppick.en_o):
 645                             comb += self.whole_reg.data.eq(ppick.o)
 646                         with m.Else():
 647                             comb += self.whole_reg.data.eq(0b00000001) # CR7
 648                     with m.Else():
 649                         comb += self.whole_reg.data.eq(self.dec.FXM)
 650                 with m.Else():
 651                     # otherwise use all of it
 652                     comb += self.whole_reg.data.eq(0xff)
 653
 654         return m
 655
 656 # dictionary of Input Record field names that, if they exist,
 657 # will need a corresponding CSV Decoder file column (actually, PowerOp)
 658 # to be decoded (this includes the single bit names)
 659 record_names = {'insn_type': 'internal_op',
 660                 'fn_unit': 'function_unit',
 661                 'rc': 'rc_sel',
 662                 'oe': 'rc_sel',
 663                 'zero_a': 'in1_sel',
 664                 'imm_data': 'in2_sel',
 665                 'invert_in': 'inv_a',
 666                 'invert_out': 'inv_out',
 667                 'rc': 'cr_out',
 668                 'oe': 'cr_in',
 669                 'output_carry': 'cry_out',
 670                 'input_carry': 'cry_in',
 671                 'is_32bit': 'is_32b',
 672                 'is_signed': 'sgn',
 673                 'lk': 'lk',
 674                 'data_len': 'ldst_len',
 675                 'byte_reverse': 'br',
 676                 'sign_extend': 'sgn_ext',
 677                 'ldst_mode': 'upd',
 678                 }
 679
 680
 681 class PowerDecodeSubset(Elaboratable):
 682     """PowerDecodeSubset: dynamic subset decoder
 683
 684     only fields actually requested are copied over. hence, "subset" (duh).
 685     """
 686     def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None,
 687                             svp64_en=True):
 688
 689         self.svp64_en = svp64_en
 690         if svp64_en:
 691             self.sv_rm = SVP64Rec(name="dec_svp64") # SVP64 RM field
 692         self.sv_a_nz = Signal(1)
 693         self.final = final
 694         self.opkls = opkls
 695         self.fn_name = fn_name
 696         if opkls is None:
 697             opkls = Decode2ToOperand
 698         self.do = opkls(fn_name)
 699         col_subset = self.get_col_subset(self.do)
 700
 701         # only needed for "main" PowerDecode2
 702         if not self.final:
 703             self.e = Decode2ToExecute1Type(name=self.fn_name, do=self.do)
 704
 705         # create decoder if one not already given
 706         if dec is None:
 707             dec = create_pdecode(name=fn_name, col_subset=col_subset,
 708                                       row_subset=self.rowsubsetfn)
 709         self.dec = dec
 710
 711         # state information needed by the Decoder
 712         if state is None:
 713             state = CoreState("dec2")
 714         self.state = state
 715
 716     def get_col_subset(self, do):
 717         subset = { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
 718         for k, v in record_names.items():
 719             if hasattr(do, k):
 720                 subset.add(v)
 721         print ("get_col_subset", self.fn_name, do.fields, subset)
 722         return subset
 723
 724     def rowsubsetfn(self, opcode, row):
 725         """select per-Function-Unit subset of opcodes to be processed
 726
 727         normally this just looks at the "unit" column.  MMU is different
 728         in that it processes specific SPR set/get operations that the SPR
 729         pipeline should not.
 730         """
 731         return (row['unit'] == self.fn_name or
 732                 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
 733                 # by the MMU pipeline so we direct those opcodes to MMU **AND**
 734                 # SPR pipelines, then selectively weed out the SPRs that should
 735                 # or should not not go to each pipeline, further down.
 736                 # really this should be done by modifying the CSV syntax
 737                 # to support multiple tasks (unit column multiple entries)
 738                 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
 739                (self.fn_name == 'MMU' and row['unit'] == 'SPR' and
 740                 row['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
 741                 )
 742
 743     def ports(self):
 744         ports = self.dec.ports() + self.e.ports()
 745         if self.svp64_en:
 746             ports += self.sv_rm.ports()
 747         return ports
 748
 749     def needs_field(self, field, op_field):
 750         if self.final:
 751             do = self.do
 752         else:
 753             do = self.e_tmp.do
 754         return hasattr(do, field) and self.op_get(op_field) is not None
 755
 756     def do_copy(self, field, val, final=False):
 757         if final or self.final:
 758             do = self.do
 759         else:
 760             do = self.e_tmp.do
 761         if hasattr(do, field) and val is not None:
 762             return getattr(do, field).eq(val)
 763         return []
 764
 765     def op_get(self, op_field):
 766         return getattr(self.dec.op, op_field, None)
 767
 768     def elaborate(self, platform):
 769         m = Module()
 770         comb = m.d.comb
 771         state = self.state
 772         op, do = self.dec.op, self.do
 773         msr, cia = state.msr, state.pc
 774         # fill in for a normal instruction (not an exception)
 775         # copy over if non-exception, non-privileged etc. is detected
 776         if not self.final:
 777             if self.fn_name is None:
 778                 name = "tmp"
 779             else:
 780                 name = self.fn_name + "tmp"
 781             self.e_tmp = Decode2ToExecute1Type(name=name, opkls=self.opkls)
 782
 783         # set up submodule decoders
 784         m.submodules.dec = self.dec
 785         m.submodules.dec_rc = self.dec_rc = dec_rc = DecodeRC(self.dec)
 786         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 787
 788         # copy instruction through...
 789         for i in [do.insn, dec_rc.insn_in, dec_oe.insn_in, ]:
 790             comb += i.eq(self.dec.opcode_in)
 791
 792         # ...and subdecoders' input fields
 793         comb += dec_rc.sel_in.eq(op.rc_sel)
 794         comb += dec_oe.sel_in.eq(op.rc_sel)  # XXX should be OE sel
 795
 796         # copy "state" over
 797         comb += self.do_copy("msr", msr)
 798         comb += self.do_copy("cia", cia)
 799
 800         # set up instruction type
 801         # no op: defaults to OP_ILLEGAL
 802         internal_op = self.op_get("internal_op")
 803         comb += self.do_copy("insn_type", internal_op)
 804
 805         # function unit for decoded instruction: requires minor redirect
 806         # for SPR set/get
 807         fn = self.op_get("function_unit")
 808         spr = Signal(10, reset_less=True)
 809         comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
 810
 811         # Microwatt doesn't implement the partition table
 812         # instead has PRTBL register (SPR) to point to process table
 813         is_spr_mv = Signal()
 814         is_mmu_spr = Signal()
 815         comb += is_spr_mv.eq((internal_op == MicrOp.OP_MTSPR) |
 816                              (internal_op == MicrOp.OP_MFSPR))
 817         comb += is_mmu_spr.eq((spr == SPR.DSISR.value) |
 818                               (spr == SPR.DAR.value) |
 819                               (spr == SPR.PRTBL.value) |
 820                               (spr == SPR.PIDR.value))
 821         # MMU must receive MMU SPRs
 822         with m.If(is_spr_mv & (fn == Function.SPR) & is_mmu_spr):
 823             comb += self.do_copy("fn_unit", Function.NONE)
 824             comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)
 825         # SPR pipe must *not* receive MMU SPRs
 826         with m.Elif(is_spr_mv & (fn == Function.MMU) & ~is_mmu_spr):
 827             comb += self.do_copy("fn_unit", Function.NONE)
 828             comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)
 829         # all others ok
 830         with m.Else():
 831             comb += self.do_copy("fn_unit", fn)
 832
 833         # immediates
 834         if self.needs_field("zero_a", "in1_sel"):
 835             m.submodules.dec_ai = dec_ai = DecodeAImm(self.dec)
 836             comb += dec_ai.sv_nz.eq(self.sv_a_nz)
 837             comb += dec_ai.sel_in.eq(op.in1_sel)
 838             comb += self.do_copy("zero_a", dec_ai.immz_out)  # RA==0 detected
 839         if self.needs_field("imm_data", "in2_sel"):
 840             m.submodules.dec_bi = dec_bi = DecodeBImm(self.dec)
 841             comb += dec_bi.sel_in.eq(op.in2_sel)
 842             comb += self.do_copy("imm_data", dec_bi.imm_out) # imm in RB
 843
 844         # rc and oe out
 845         comb += self.do_copy("rc", dec_rc.rc_out)
 846         comb += self.do_copy("oe", dec_oe.oe_out)
 847
 848         # CR in/out - note: these MUST match with what happens in
 849         # DecodeCROut!
 850         rc_out = self.dec_rc.rc_out.data
 851         with m.Switch(op.cr_out):
 852             with m.Case(CROutSel.CR0, CROutSel.CR1):
 853                 comb += self.do_copy("write_cr0", rc_out) # only when RC=1
 854             with m.Case(CROutSel.BF, CROutSel.BT):
 855                 comb += self.do_copy("write_cr0", 1)
 856
 857         comb += self.do_copy("input_cr", self.op_get("cr_in"))   # CR in
 858         comb += self.do_copy("output_cr", self.op_get("cr_out"))  # CR out
 859
 860         # decoded/selected instruction flags
 861         comb += self.do_copy("data_len", self.op_get("ldst_len"))
 862         comb += self.do_copy("invert_in", self.op_get("inv_a"))
 863         comb += self.do_copy("invert_out", self.op_get("inv_out"))
 864         comb += self.do_copy("input_carry", self.op_get("cry_in"))
 865         comb += self.do_copy("output_carry", self.op_get("cry_out"))
 866         comb += self.do_copy("is_32bit", self.op_get("is_32b"))
 867         comb += self.do_copy("is_signed", self.op_get("sgn"))
 868         lk = self.op_get("lk")
 869         if lk is not None:
 870             with m.If(lk):
 871                 comb += self.do_copy("lk", self.dec.LK)  # XXX TODO: accessor
 872
 873         comb += self.do_copy("byte_reverse", self.op_get("br"))
 874         comb += self.do_copy("sign_extend", self.op_get("sgn_ext"))
 875         comb += self.do_copy("ldst_mode", self.op_get("upd"))  # LD/ST mode
 876
 877         return m
 878
 879
 880 class PowerDecode2(PowerDecodeSubset):
 881     """PowerDecode2: the main instruction decoder.
 882
 883     whilst PowerDecode is responsible for decoding the actual opcode, this
 884     module encapsulates further specialist, sparse information and
 885     expansion of fields that is inconvenient to have in the CSV files.
 886     for example: the encoding of the immediates, which are detected
 887     and expanded out to their full value from an annotated (enum)
 888     representation.
 889
 890     implicit register usage is also set up, here.  for example: OP_BC
 891     requires implicitly reading CTR, OP_RFID requires implicitly writing
 892     to SRR1 and so on.
 893
 894     in addition, PowerDecoder2 is responsible for detecting whether
 895     instructions are illegal (or privileged) or not, and instead of
 896     just leaving at that, *replacing* the instruction to execute with
 897     a suitable alternative (trap).
 898
 899     LDSTExceptions are done the cycle _after_ they're detected (after
 900     they come out of LDSTCompUnit).  basically despite the instruction
 901     being decoded, the results of the decode are completely ignored
 902     and "exception.happened" used to set the "actual" instruction to
 903     "OP_TRAP".  the LDSTException data structure gets filled in,
 904     in the CompTrapOpSubset and that's what it fills in SRR.
 905
 906     to make this work, TestIssuer must notice "exception.happened"
 907     after the (failed) LD/ST and copies the LDSTException info from
 908     the output, into here (PowerDecoder2).  without incrementing PC.
 909     """
 910
 911     def __init__(self, dec, opkls=None, fn_name=None, final=False,
 912                             state=None, svp64_en=True):
 913         super().__init__(dec, opkls, fn_name, final, state, svp64_en)
 914         self.exc = LDSTException("dec2_exc")
 915
 916         if self.svp64_en:
 917             self.cr_out_isvec = Signal(1, name="cr_out_isvec")
 918             self.cr_in_isvec = Signal(1, name="cr_in_isvec")
 919             self.cr_in_b_isvec = Signal(1, name="cr_in_b_isvec")
 920             self.cr_in_o_isvec = Signal(1, name="cr_in_o_isvec")
 921             self.in1_isvec = Signal(1, name="reg_a_isvec")
 922             self.in2_isvec = Signal(1, name="reg_b_isvec")
 923             self.in3_isvec = Signal(1, name="reg_c_isvec")
 924             self.o_isvec = Signal(1, name="reg_o_isvec")
 925             self.o2_isvec = Signal(1, name="reg_o2_isvec")
 926             self.no_in_vec = Signal(1, name="no_in_vec") # no inputs vector
 927             self.no_out_vec = Signal(1, name="no_out_vec") # no outputs vector
 928             self.loop_continue = Signal(1, name="loop_continue")
 929             self.rm_dec = SVP64RMModeDecode("svp64_rm_dec")
 930         else:
 931             self.no_in_vec = Const(1, 1)
 932             self.no_out_vec = Const(1, 1)
 933             self.loop_continue = Const(0, 1)
 934
 935     def get_col_subset(self, opkls):
 936         subset = super().get_col_subset(opkls)
 937         subset.add("asmcode")
 938         subset.add("in1_sel")
 939         subset.add("in2_sel")
 940         subset.add("in3_sel")
 941         subset.add("out_sel")
 942         if self.svp64_en:
 943             subset.add("sv_in1")
 944             subset.add("sv_in2")
 945             subset.add("sv_in3")
 946             subset.add("sv_out")
 947             subset.add("sv_cr_in")
 948             subset.add("sv_cr_out")
 949             subset.add("SV_Etype")
 950             subset.add("SV_Ptype")
 951         subset.add("lk")
 952         subset.add("internal_op")
 953         subset.add("form")
 954         return subset
 955
 956     def elaborate(self, platform):
 957         m = super().elaborate(platform)
 958         comb = m.d.comb
 959         state = self.state
 960         e_out, op, do_out = self.e, self.dec.op, self.e.do
 961         dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
 962         rc_out = self.dec_rc.rc_out.data
 963         e = self.e_tmp
 964         do = e.do
 965
 966         # fill in for a normal instruction (not an exception)
 967         # copy over if non-exception, non-privileged etc. is detected
 968
 969         # set up submodule decoders
 970         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 971         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 972         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 973         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 974         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
 975         m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec)
 976         m.submodules.dec_cr_out = self.dec_cr_out = DecodeCROut(self.dec)
 977         comb += dec_a.sv_nz.eq(self.sv_a_nz)
 978
 979         if self.svp64_en:
 980             # and SVP64 Extra decoders
 981             m.submodules.crout_svdec = crout_svdec = SVP64CRExtra()
 982             m.submodules.crin_svdec = crin_svdec = SVP64CRExtra()
 983             m.submodules.crin_svdec_b = crin_svdec_b = SVP64CRExtra()
 984             m.submodules.crin_svdec_o = crin_svdec_o = SVP64CRExtra()
 985             m.submodules.in1_svdec = in1_svdec = SVP64RegExtra()
 986             m.submodules.in2_svdec = in2_svdec = SVP64RegExtra()
 987             m.submodules.in3_svdec = in3_svdec = SVP64RegExtra()
 988             m.submodules.o_svdec = o_svdec = SVP64RegExtra()
 989             m.submodules.o2_svdec = o2_svdec = SVP64RegExtra()
 990
 991             # debug access to crout_svdec (used in get_pdecode_cr_out)
 992             self.crout_svdec = crout_svdec
 993
 994             # and SVP64 RM mode decoder
 995             m.submodules.sv_rm_dec = rm_dec = self.rm_dec
 996
 997         # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
 998         reg = Signal(5, reset_less=True)
 999
1000         # copy instruction through...
1001         for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
1002                   self.dec_cr_in.insn_in, self.dec_cr_out.insn_in,
1003                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]:
1004             comb += i.eq(self.dec.opcode_in)
1005
1006         # CR setup
1007         comb += self.dec_cr_in.sel_in.eq(op.cr_in)
1008         comb += self.dec_cr_out.sel_in.eq(op.cr_out)
1009         comb += self.dec_cr_out.rc_in.eq(rc_out)
1010
1011         # CR register info
1012         comb += self.do_copy("read_cr_whole", self.dec_cr_in.whole_reg)
1013         comb += self.do_copy("write_cr_whole", self.dec_cr_out.whole_reg)
1014
1015         # ...and subdecoders' input fields
1016         comb += dec_a.sel_in.eq(op.in1_sel)
1017         comb += dec_b.sel_in.eq(op.in2_sel)
1018         comb += dec_c.sel_in.eq(op.in3_sel)
1019         comb += dec_o.sel_in.eq(op.out_sel)
1020         comb += dec_o2.sel_in.eq(op.out_sel)
1021         if hasattr(do, "lk"):
1022             comb += dec_o2.lk.eq(do.lk)
1023
1024         if self.svp64_en:
1025             # now do the SVP64 munging.  op.SV_Etype and op.sv_in1 comes from
1026             # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1027             # which in turn were auto-generated by sv_analysis.py
1028             extra = self.sv_rm.extra            # SVP64 extra bits 10:18
1029
1030             #######
1031             # CR out
1032             comb += crout_svdec.idx.eq(op.sv_cr_out)  # SVP64 CR out
1033             comb += self.cr_out_isvec.eq(crout_svdec.isvec)
1034
1035             #######
1036             # CR in - selection slightly different due to shared CR field sigh
1037             cr_a_idx = Signal(SVEXTRA)
1038             cr_b_idx = Signal(SVEXTRA)
1039
1040             # these change slightly, when decoding BA/BB.  really should have
1041             # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1042             comb += cr_a_idx.eq(op.sv_cr_in)
1043             comb += cr_b_idx.eq(SVEXTRA.NONE)
1044             with m.If(op.sv_cr_in == SVEXTRA.Idx_1_2.value):
1045                 comb += cr_a_idx.eq(SVEXTRA.Idx1)
1046                 comb += cr_b_idx.eq(SVEXTRA.Idx2)
1047
1048             comb += self.cr_in_isvec.eq(crin_svdec.isvec)
1049             comb += self.cr_in_b_isvec.eq(crin_svdec_b.isvec)
1050             comb += self.cr_in_o_isvec.eq(crin_svdec_o.isvec)
1051
1052             # indices are slightly different, BA/BB mess sorted above
1053             comb += crin_svdec.idx.eq(cr_a_idx)       # SVP64 CR in A
1054             comb += crin_svdec_b.idx.eq(cr_b_idx)     # SVP64 CR in B
1055             comb += crin_svdec_o.idx.eq(op.sv_cr_out) # SVP64 CR out
1056
1057             # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1058             srcstep = Signal.like(self.state.svstate.srcstep)
1059             dststep = Signal.like(self.state.svstate.dststep)
1060             comb += srcstep.eq(self.state.svstate.srcstep)
1061             comb += dststep.eq(self.state.svstate.dststep)
1062
1063             # registers a, b, c and out and out2 (LD/ST EA)
1064             for to_reg, fromreg, svdec, out in (
1065                 (e.read_reg1, dec_a.reg_out, in1_svdec, False),
1066                 (e.read_reg2, dec_b.reg_out, in2_svdec, False),
1067                 (e.read_reg3, dec_c.reg_out, in3_svdec, False),
1068                 (e.write_reg, dec_o.reg_out, o_svdec, True),
1069                 (e.write_ea, dec_o2.reg_out, o2_svdec, True)):
1070                 comb += svdec.extra.eq(extra)        # EXTRA field of SVP64 RM
1071                 comb += svdec.etype.eq(op.SV_Etype)  # EXTRA2/3 for this insn
1072                 comb += svdec.reg_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1073                 comb += to_reg.ok.eq(fromreg.ok)
1074                 # detect if Vectorised: add srcstep/dststep if yes.
1075                 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1076                 with m.If(svdec.isvec):
1077                     step = dststep if out else srcstep
1078                     comb += to_reg.data.eq(step+svdec.reg_out)
1079                 with m.Else():
1080                     comb += to_reg.data.eq(svdec.reg_out)
1081
1082             comb += in1_svdec.idx.eq(op.sv_in1)  # SVP64 reg #1 (in1_sel)
1083             comb += in2_svdec.idx.eq(op.sv_in2)  # SVP64 reg #2 (in2_sel)
1084             comb += in3_svdec.idx.eq(op.sv_in3)  # SVP64 reg #3 (in3_sel)
1085             comb += o_svdec.idx.eq(op.sv_out)    # SVP64 output (out_sel)
1086             # XXX TODO - work out where this should come from.  the problem is
1087             # that LD-with-update is implied (computed from "is instruction in
1088             # "update mode" rather than specified cleanly as its own CSV column
1089             #comb += o2_svdec.idx.eq(op.sv_out)    # SVP64 output (implicit)
1090
1091             # output reg-is-vectorised (and when no in/out is vectorised)
1092             comb += self.in1_isvec.eq(in1_svdec.isvec)
1093             comb += self.in2_isvec.eq(in2_svdec.isvec)
1094             comb += self.in3_isvec.eq(in3_svdec.isvec)
1095             comb += self.o_isvec.eq(o_svdec.isvec)
1096             comb += self.o2_isvec.eq(o2_svdec.isvec)
1097             # TODO add SPRs here.  must be True when *all* are scalar
1098             l = map(lambda svdec: svdec.isvec, [in1_svdec, in2_svdec, in3_svdec,
1099                                         crin_svdec, crin_svdec_b, crin_svdec_o])
1100             comb += self.no_in_vec.eq(~Cat(*l).bool()) # all input scalar
1101             l = map(lambda svdec: svdec.isvec, [o2_svdec, o_svdec, crout_svdec])
1102             comb += self.no_out_vec.eq(~Cat(*l).bool()) # all output scalar
1103             # now create a general-purpose "test" as to whether looping
1104             # should continue.  this doesn't include predication bit-tests
1105             loop = self.loop_continue
1106             with m.Switch(op.SV_Ptype):
1107                 with m.Case(SVPtype.P2.value):
1108                     # twin-predication
1109                     # TODO: *and cache-inhibited LD/ST!*
1110                     comb += loop.eq(~(self.no_in_vec | self.no_out_vec))
1111                 with m.Case(SVPtype.P1.value):
1112                     # single-predication, test relies on dest only
1113                     comb += loop.eq(~self.no_out_vec)
1114                 with m.Default():
1115                     # not an SV operation, no looping
1116                     comb += loop.eq(0)
1117
1118             # condition registers (CR)
1119             for to_reg, cr, name, svdec, out in (
1120                 (e.read_cr1, self.dec_cr_in, "cr_bitfield", crin_svdec, 0),
1121                 (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", crin_svdec_b, 0),
1122                 (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", crin_svdec_o, 0),
1123                 (e.write_cr, self.dec_cr_out, "cr_bitfield", crout_svdec, 1)):
1124                 fromreg = getattr(cr, name)
1125                 comb += svdec.extra.eq(extra)        # EXTRA field of SVP64 RM
1126                 comb += svdec.etype.eq(op.SV_Etype)  # EXTRA2/3 for this insn
1127                 comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1128                 with m.If(svdec.isvec):
1129                     # check if this is CR0 or CR1: treated differently
1130                     # (does not "listen" to EXTRA2/3 spec for a start)
1131                     # also: the CRs start from completely different locations
1132                     step = dststep if out else srcstep
1133                     with m.If(cr.sv_override == 1): # CR0
1134                         offs = SVP64CROffs.CR0
1135                         comb += to_reg.data.eq(step+offs)
1136                     with m.Elif(cr.sv_override == 2): # CR1
1137                         offs = SVP64CROffs.CR1
1138                         comb += to_reg.data.eq(step+1)
1139                     with m.Else():
1140                         comb += to_reg.data.eq(step+svdec.cr_out) # 7-bit out
1141                 with m.Else():
1142                     comb += to_reg.data.eq(svdec.cr_out) # 7-bit output
1143                 comb += to_reg.ok.eq(fromreg.ok)
1144
1145             # sigh must determine if RA is nonzero (7 bit)
1146             comb += self.sv_a_nz.eq(e.read_reg1.data != Const(0, 7))
1147         else:
1148             # connect up to/from read/write GPRs
1149             for to_reg, fromreg in ((e.read_reg1, dec_a.reg_out),
1150                                     (e.read_reg2, dec_b.reg_out),
1151                                     (e.read_reg3, dec_c.reg_out),
1152                                     (e.write_reg, dec_o.reg_out),
1153                                     (e.write_ea, dec_o2.reg_out)):
1154                 comb += to_reg.data.eq(fromreg.data)
1155                 comb += to_reg.ok.eq(fromreg.ok)
1156
1157             # connect up to/from read/write CRs
1158             for to_reg, cr, name in (
1159                         (e.read_cr1, self.dec_cr_in, "cr_bitfield", ),
1160                         (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", ),
1161                         (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", ),
1162                         (e.write_cr, self.dec_cr_out, "cr_bitfield", )):
1163                 fromreg = getattr(cr, name)
1164                 comb += to_reg.data.eq(fromreg.data)
1165                 comb += to_reg.ok.eq(fromreg.ok)
1166
1167         # SPRs out
1168         comb += e.read_spr1.eq(dec_a.spr_out)
1169         comb += e.write_spr.eq(dec_o.spr_out)
1170
1171         # Fast regs out
1172         comb += e.read_fast1.eq(dec_a.fast_out)
1173         comb += e.read_fast2.eq(dec_b.fast_out)
1174         comb += e.write_fast1.eq(dec_o.fast_out)
1175         comb += e.write_fast2.eq(dec_o2.fast_out)
1176
1177         if self.svp64_en:
1178             # connect up SVP64 RM Mode decoding
1179             fn = self.op_get("function_unit")
1180             comb += rm_dec.fn_in.eq(fn) # decode needs to know if LD/ST type
1181             comb += rm_dec.ptype_in.eq(op.SV_Ptype) # Single/Twin predicated
1182             comb += rm_dec.rc_in.eq(rc_out) # Rc=1
1183             comb += rm_dec.rm_in.eq(self.sv_rm) # SVP64 RM mode
1184
1185         # sigh this is exactly the sort of thing for which the
1186         # decoder is designed to not need.  MTSPR, MFSPR and others need
1187         # access to the XER bits.  however setting e.oe is not appropriate
1188         with m.If(op.internal_op == MicrOp.OP_MFSPR):
1189             comb += e.xer_in.eq(0b111) # SO, CA, OV
1190         with m.If(op.internal_op == MicrOp.OP_CMP):
1191             comb += e.xer_in.eq(1<<XERRegs.SO) # SO
1192         with m.If(op.internal_op == MicrOp.OP_MTSPR):
1193             comb += e.xer_out.eq(1)
1194
1195         # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1196         with m.If(op.internal_op == MicrOp.OP_TRAP):
1197             # *DO NOT* call self.trap here.  that would reset absolutely
1198             # everything including destroying read of RA and RB.
1199             comb += self.do_copy("trapaddr", 0x70) # strip first nibble
1200
1201         ####################
1202         # ok so the instruction's been decoded, blah blah, however
1203         # now we need to determine if it's actually going to go ahead...
1204         # *or* if in fact it's a privileged operation, whether there's
1205         # an external interrupt, etc. etc.  this is a simple priority
1206         # if-elif-elif sequence.  decrement takes highest priority,
1207         # EINT next highest, privileged operation third.
1208
1209         # check if instruction is privileged
1210         is_priv_insn = instr_is_priv(m, op.internal_op, e.do.insn)
1211
1212         # different IRQ conditions
1213         ext_irq_ok = Signal()
1214         dec_irq_ok = Signal()
1215         priv_ok = Signal()
1216         illeg_ok = Signal()
1217         exc = self.exc
1218
1219         comb += ext_irq_ok.eq(ext_irq & msr[MSR.EE]) # v3.0B p944 (MSR.EE)
1220         comb += dec_irq_ok.eq(dec_spr[63] & msr[MSR.EE]) # 6.5.11 p1076
1221         comb += priv_ok.eq(is_priv_insn & msr[MSR.PR])
1222         comb += illeg_ok.eq(op.internal_op == MicrOp.OP_ILLEGAL)
1223
1224         # LD/ST exceptions.  TestIssuer copies the exception info at us
1225         # after a failed LD/ST.
1226         with m.If(exc.happened):
1227             with m.If(exc.alignment):
1228                 self.trap(m, TT.PRIV, 0x600)
1229             with m.Elif(exc.instr_fault):
1230                 with m.If(exc.segment_fault):
1231                     self.trap(m, TT.PRIV, 0x480)
1232                 with m.Else():
1233                     # pass exception info to trap to create SRR1
1234                     self.trap(m, TT.MEMEXC, 0x400, exc)
1235             with m.Else():
1236                 with m.If(exc.segment_fault):
1237                     self.trap(m, TT.PRIV, 0x380)
1238                 with m.Else():
1239                     self.trap(m, TT.PRIV, 0x300)
1240
1241         # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1242         with m.Elif(dec_irq_ok):
1243             self.trap(m, TT.DEC, 0x900)   # v3.0B 6.5 p1065
1244
1245         # external interrupt? only if MSR.EE set
1246         with m.Elif(ext_irq_ok):
1247             self.trap(m, TT.EINT, 0x500)
1248
1249         # privileged instruction trap
1250         with m.Elif(priv_ok):
1251             self.trap(m, TT.PRIV, 0x700)
1252
1253         # illegal instruction must redirect to trap. this is done by
1254         # *overwriting* the decoded instruction and starting again.
1255         # (note: the same goes for interrupts and for privileged operations,
1256         # just with different trapaddr and traptype)
1257         with m.Elif(illeg_ok):
1258             # illegal instruction trap
1259             self.trap(m, TT.ILLEG, 0x700)
1260
1261         # no exception, just copy things to the output
1262         with m.Else():
1263             comb += e_out.eq(e)
1264
1265         ####################
1266         # follow-up after trap/irq to set up SRR0/1
1267
1268         # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1269         # Note: OP_SC could actually be modified to just be a trap
1270         with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
1271                   (do_out.insn_type == MicrOp.OP_SC)):
1272             # TRAP write fast1 = SRR0
1273             comb += e_out.write_fast1.data.eq(FastRegs.SRR0)  # constant: SRR0
1274             comb += e_out.write_fast1.ok.eq(1)
1275             # TRAP write fast2 = SRR1
1276             comb += e_out.write_fast2.data.eq(FastRegs.SRR1)  # constant: SRR1
1277             comb += e_out.write_fast2.ok.eq(1)
1278
1279         # RFID: needs to read SRR0/1
1280         with m.If(do_out.insn_type == MicrOp.OP_RFID):
1281             # TRAP read fast1 = SRR0
1282             comb += e_out.read_fast1.data.eq(FastRegs.SRR0)  # constant: SRR0
1283             comb += e_out.read_fast1.ok.eq(1)
1284             # TRAP read fast2 = SRR1
1285             comb += e_out.read_fast2.data.eq(FastRegs.SRR1)  # constant: SRR1
1286             comb += e_out.read_fast2.ok.eq(1)
1287
1288         # annoying simulator bug
1289         if hasattr(e_out, "asmcode") and hasattr(self.dec.op, "asmcode"):
1290             comb += e_out.asmcode.eq(self.dec.op.asmcode)
1291
1292         return m
1293
1294     def trap(self, m, traptype, trapaddr, exc=None):
1295         """trap: this basically "rewrites" the decoded instruction as a trap
1296         """
1297         comb = m.d.comb
1298         op, e = self.dec.op, self.e
1299         comb += e.eq(0)  # reset eeeeeverything
1300
1301         # start again
1302         comb += self.do_copy("insn", self.dec.opcode_in, True)
1303         comb += self.do_copy("insn_type", MicrOp.OP_TRAP, True)
1304         comb += self.do_copy("fn_unit", Function.TRAP, True)
1305         comb += self.do_copy("trapaddr", trapaddr >> 4, True) # bottom 4 bits
1306         comb += self.do_copy("traptype", traptype, True)  # request type
1307         comb += self.do_copy("ldst_exc", exc, True)  # request type
1308         comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state"
1309         comb += self.do_copy("cia", self.state.pc, True)  # copy of PC "state"
1310
1311
1312
1313 def get_rdflags(e, cu):
1314     rdl = []
1315     for idx in range(cu.n_src):
1316         regfile, regname, _ = cu.get_in_spec(idx)
1317         rdflag, read = regspec_decode_read(e, regfile, regname)
1318         rdl.append(rdflag)
1319     print("rdflags", rdl)
1320     return Cat(*rdl)
1321
1322
1323 if __name__ == '__main__':
1324     pdecode = create_pdecode()
1325     dec2 = PowerDecode2(pdecode)
1326     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
1327     with open("dec2.il", "w") as f:
1328         f.write(vl)