src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
   7 from nmigen.cli import rtlil
   8
   9 from nmutil.iocontrol import RecordObject
  10 from nmutil.extend import exts
  11
  12 from soc.decoder.power_regspec_map import regspec_decode
  13 from soc.decoder.power_decoder import create_pdecode
  14 from soc.decoder.power_enums import (InternalOp, CryIn, Function,
  15                                      CRInSel, CROutSel,
  16                                      LdstLen, In1Sel, In2Sel, In3Sel,
  17                                      OutSel, SPR, RC)
  18
  19 from soc.regfile.regfiles import FastRegs
  20
  21 class DecodeA(Elaboratable):
  22     """DecodeA from instruction
  23
  24     decodes register RA, whether immediate-zero, implicit and
  25     explicit CSRs
  26     """
  27
  28     def __init__(self, dec):
  29         self.dec = dec
  30         self.sel_in = Signal(In1Sel, reset_less=True)
  31         self.insn_in = Signal(32, reset_less=True)
  32         self.reg_out = Data(5, name="reg_a")
  33         self.immz_out = Signal(reset_less=True)
  34         self.spr_out = Data(10, "spr_a")
  35         self.fast_out = Data(3, "fast_a")
  36
  37     def elaborate(self, platform):
  38         m = Module()
  39         comb = m.d.comb
  40
  41         # select Register A field
  42         ra = Signal(5, reset_less=True)
  43         comb += ra.eq(self.dec.RA)
  44         with m.If((self.sel_in == In1Sel.RA) |
  45                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  46                    (ra != Const(0, 5)))):
  47             comb += self.reg_out.data.eq(ra)
  48             comb += self.reg_out.ok.eq(1)
  49
  50         # zero immediate requested
  51         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
  52                   (self.reg_out.data == Const(0, 5))):
  53             comb += self.immz_out.eq(1)
  54
  55         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
  56         with m.If(self.sel_in == In1Sel.RS):
  57             comb += self.reg_out.data.eq(self.dec.RS)
  58             comb += self.reg_out.ok.eq(1)
  59
  60         # decode Fast-SPR based on instruction type
  61         op = self.dec.op
  62         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
  63         with m.If((op.internal_op == InternalOp.OP_BC) |
  64                   (op.internal_op == InternalOp.OP_BCREG)):
  65             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
  66                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
  67                 comb += self.fast_out.ok.eq(1)
  68
  69         # MFSPR or MTSPR: move-from / move-to SPRs
  70         with m.If((op.internal_op == InternalOp.OP_MFSPR) |
  71                   (op.internal_op == InternalOp.OP_MTSPR)):
  72             # XXX TODO: fast/slow SPR decoding and mapping
  73             comb += self.spr_out.data.eq(self.dec.SPR) # SPR field, XFX
  74             comb += self.spr_out.ok.eq(1)
  75
  76         return m
  77
  78
  79 class Data(Record):
  80
  81     def __init__(self, width, name):
  82         name_ok = "%s_ok" % name
  83         layout = ((name, width), (name_ok, 1))
  84         Record.__init__(self, layout)
  85         self.data = getattr(self, name) # convenience
  86         self.ok = getattr(self, name_ok) # convenience
  87         self.data.reset_less = True # grrr
  88         self.reset_less = True # grrr
  89
  90     def ports(self):
  91         return [self.data, self.ok]
  92
  93
  94 class DecodeB(Elaboratable):
  95     """DecodeB from instruction
  96
  97     decodes register RB, different forms of immediate (signed, unsigned),
  98     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
  99     by industry-standard convention, "lane 2" is where fully-decoded
 100     immediates are muxed in.
 101     """
 102
 103     def __init__(self, dec):
 104         self.dec = dec
 105         self.sel_in = Signal(In2Sel, reset_less=True)
 106         self.insn_in = Signal(32, reset_less=True)
 107         self.reg_out = Data(5, "reg_b")
 108         self.imm_out = Data(64, "imm_b")
 109         self.fast_out = Data(3, "fast_b")
 110
 111     def elaborate(self, platform):
 112         m = Module()
 113         comb = m.d.comb
 114
 115         # select Register B field
 116         with m.Switch(self.sel_in):
 117             with m.Case(In2Sel.RB):
 118                 comb += self.reg_out.data.eq(self.dec.RB)
 119                 comb += self.reg_out.ok.eq(1)
 120             with m.Case(In2Sel.RS):
 121                 comb += self.reg_out.data.eq(self.dec.RS) # for M-Form shiftrot
 122                 comb += self.reg_out.ok.eq(1)
 123             with m.Case(In2Sel.CONST_UI):
 124                 comb += self.imm_out.data.eq(self.dec.UI)
 125                 comb += self.imm_out.ok.eq(1)
 126             with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here?
 127                 comb += self.imm_out.data.eq(
 128                     exts(self.dec.SI, 16, 64))
 129                 comb += self.imm_out.ok.eq(1)
 130             with m.Case(In2Sel.CONST_UI_HI):
 131                 comb += self.imm_out.data.eq(self.dec.UI<<16)
 132                 comb += self.imm_out.ok.eq(1)
 133             with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here?
 134                 comb += self.imm_out.data.eq(self.dec.SI<<16)
 135                 comb += self.imm_out.data.eq(
 136                     exts(self.dec.SI << 16, 32, 64))
 137                 comb += self.imm_out.ok.eq(1)
 138             with m.Case(In2Sel.CONST_LI):
 139                 comb += self.imm_out.data.eq(self.dec.LI<<2)
 140                 comb += self.imm_out.ok.eq(1)
 141             with m.Case(In2Sel.CONST_BD):
 142                 comb += self.imm_out.data.eq(self.dec.BD<<2)
 143                 comb += self.imm_out.ok.eq(1)
 144             with m.Case(In2Sel.CONST_DS):
 145                 comb += self.imm_out.data.eq(self.dec.DS<<2)
 146                 comb += self.imm_out.ok.eq(1)
 147             with m.Case(In2Sel.CONST_M1):
 148                 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
 149                 comb += self.imm_out.ok.eq(1)
 150             with m.Case(In2Sel.CONST_SH):
 151                 comb += self.imm_out.data.eq(self.dec.sh)
 152                 comb += self.imm_out.ok.eq(1)
 153             with m.Case(In2Sel.CONST_SH32):
 154                 comb += self.imm_out.data.eq(self.dec.SH32)
 155                 comb += self.imm_out.ok.eq(1)
 156
 157         # decode SPR2 based on instruction type
 158         op = self.dec.op
 159         # BCREG implicitly uses CTR or LR for 2nd reg
 160         with m.If(op.internal_op == InternalOp.OP_BCREG):
 161             with m.If(self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO
 162                 comb += self.fast_out.data.eq(FastRegs.CTR)
 163             with m.Else():
 164                 comb += self.fast_out.data.eq(FastRegs.LR)
 165             comb += self.fast_out.ok.eq(1)
 166
 167         return m
 168
 169
 170 class DecodeC(Elaboratable):
 171     """DecodeC from instruction
 172
 173     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 174     """
 175
 176     def __init__(self, dec):
 177         self.dec = dec
 178         self.sel_in = Signal(In3Sel, reset_less=True)
 179         self.insn_in = Signal(32, reset_less=True)
 180         self.reg_out = Data(5, "reg_c")
 181
 182     def elaborate(self, platform):
 183         m = Module()
 184         comb = m.d.comb
 185
 186         # select Register C field
 187         with m.Switch(self.sel_in):
 188             with m.Case(In3Sel.RB):
 189                 comb += self.reg_out.data.eq(self.dec.RB) # for M-Form shiftrot
 190                 comb += self.reg_out.ok.eq(1)
 191             with m.Case(In3Sel.RS):
 192                 comb += self.reg_out.data.eq(self.dec.RS)
 193                 comb += self.reg_out.ok.eq(1)
 194
 195         return m
 196
 197
 198 class DecodeOut(Elaboratable):
 199     """DecodeOut from instruction
 200
 201     decodes output register RA, RT or SPR
 202     """
 203
 204     def __init__(self, dec):
 205         self.dec = dec
 206         self.sel_in = Signal(OutSel, reset_less=True)
 207         self.insn_in = Signal(32, reset_less=True)
 208         self.reg_out = Data(5, "reg_o")
 209         self.spr_out = Data(10, "spr_o")
 210         self.fast_out = Data(3, "fast_o")
 211
 212     def elaborate(self, platform):
 213         m = Module()
 214         comb = m.d.comb
 215
 216         # select Register out field
 217         with m.Switch(self.sel_in):
 218             with m.Case(OutSel.RT):
 219                 comb += self.reg_out.data.eq(self.dec.RT)
 220                 comb += self.reg_out.ok.eq(1)
 221             with m.Case(OutSel.RA):
 222                 comb += self.reg_out.data.eq(self.dec.RA)
 223                 comb += self.reg_out.ok.eq(1)
 224             with m.Case(OutSel.SPR):
 225                 comb += self.spr_out.data.eq(self.dec.SPR) # from XFX
 226                 comb += self.spr_out.ok.eq(1)
 227
 228         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
 229         op = self.dec.op
 230         with m.If((op.internal_op == InternalOp.OP_BC) |
 231                   (op.internal_op == InternalOp.OP_BCREG)):
 232             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
 233                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
 234                 comb += self.fast_out.ok.eq(1)
 235         return m
 236
 237
 238 class DecodeOut2(Elaboratable):
 239     """DecodeOut2 from instruction
 240
 241     decodes output registers
 242     """
 243
 244     def __init__(self, dec):
 245         self.dec = dec
 246         self.sel_in = Signal(OutSel, reset_less=True)
 247         self.insn_in = Signal(32, reset_less=True)
 248         self.reg_out = Data(5, "reg_o")
 249         self.fast_out = Data(3, "fast_o")
 250
 251     def elaborate(self, platform):
 252         m = Module()
 253         comb = m.d.comb
 254
 255         # update mode LD/ST uses read-reg A also as an output
 256         with m.If(self.dec.op.upd):
 257             comb += self.reg_out.eq(self.dec.RA)
 258             comb += self.reg_out.ok.eq(1)
 259
 260         # BC or BCREG: potential implicit register (LR) output
 261         op = self.dec.op
 262         with m.If((op.internal_op == InternalOp.OP_BC) |
 263                   (op.internal_op == InternalOp.OP_BCREG)):
 264             with m.If(self.dec.op.lk & self.dec.LK): # "link" mode
 265                 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
 266                 comb += self.fast_out.ok.eq(1)
 267
 268         return m
 269
 270
 271 class DecodeRC(Elaboratable):
 272     """DecodeRc from instruction
 273
 274     decodes Record bit Rc
 275     """
 276     def __init__(self, dec):
 277         self.dec = dec
 278         self.sel_in = Signal(RC, reset_less=True)
 279         self.insn_in = Signal(32, reset_less=True)
 280         self.rc_out = Data(1, "rc")
 281
 282     def elaborate(self, platform):
 283         m = Module()
 284         comb = m.d.comb
 285
 286         # select Record bit out field
 287         with m.Switch(self.sel_in):
 288             with m.Case(RC.RC):
 289                 comb += self.rc_out.data.eq(self.dec.Rc)
 290                 comb += self.rc_out.ok.eq(1)
 291             with m.Case(RC.ONE):
 292                 comb += self.rc_out.data.eq(1)
 293                 comb += self.rc_out.ok.eq(1)
 294             with m.Case(RC.NONE):
 295                 comb += self.rc_out.data.eq(0)
 296                 comb += self.rc_out.ok.eq(1)
 297
 298         return m
 299
 300
 301 class DecodeOE(Elaboratable):
 302     """DecodeOE from instruction
 303
 304     decodes OE field: uses RC decode detection which might not be good
 305
 306     -- For now, use "rc" in the decode table to decide whether oe exists.
 307     -- This is not entirely correct architecturally: For mulhd and
 308     -- mulhdu, the OE field is reserved. It remains to be seen what an
 309     -- actual POWER9 does if we set it on those instructions, for now we
 310     -- test that further down when assigning to the multiplier oe input.
 311     """
 312     def __init__(self, dec):
 313         self.dec = dec
 314         self.sel_in = Signal(RC, reset_less=True)
 315         self.insn_in = Signal(32, reset_less=True)
 316         self.oe_out = Data(1, "oe")
 317
 318     def elaborate(self, platform):
 319         m = Module()
 320         comb = m.d.comb
 321
 322         # select OE bit out field
 323         with m.Switch(self.sel_in):
 324             with m.Case(RC.RC):
 325                 comb += self.oe_out.data.eq(self.dec.OE)
 326                 comb += self.oe_out.ok.eq(1)
 327
 328         return m
 329
 330 class DecodeCRIn(Elaboratable):
 331     """Decodes input CR from instruction
 332
 333     CR indices - insn fields - (not the data *in* the CR) require only 3
 334     bits because they refer to CR0-CR7
 335     """
 336
 337     def __init__(self, dec):
 338         self.dec = dec
 339         self.sel_in = Signal(CRInSel, reset_less=True)
 340         self.insn_in = Signal(32, reset_less=True)
 341         self.cr_bitfield = Data(3, "cr_bitfield")
 342         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 343         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 344         self.whole_reg = Signal(reset_less=True)
 345
 346     def elaborate(self, platform):
 347         m = Module()
 348         comb = m.d.comb
 349
 350         comb += self.cr_bitfield.ok.eq(0)
 351         comb += self.cr_bitfield_b.ok.eq(0)
 352         comb += self.whole_reg.eq(0)
 353         with m.Switch(self.sel_in):
 354             with m.Case(CRInSel.NONE):
 355                 pass # No bitfield activated
 356             with m.Case(CRInSel.CR0):
 357                 comb += self.cr_bitfield.data.eq(0)
 358                 comb += self.cr_bitfield.ok.eq(1)
 359             with m.Case(CRInSel.BI):
 360                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 361                 comb += self.cr_bitfield.ok.eq(1)
 362             with m.Case(CRInSel.BFA):
 363                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 364                 comb += self.cr_bitfield.ok.eq(1)
 365             with m.Case(CRInSel.BA_BB):
 366                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 367                 comb += self.cr_bitfield.ok.eq(1)
 368                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 369                 comb += self.cr_bitfield_b.ok.eq(1)
 370                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 371                 comb += self.cr_bitfield_o.ok.eq(1)
 372             with m.Case(CRInSel.BC):
 373                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 374                 comb += self.cr_bitfield.ok.eq(1)
 375             with m.Case(CRInSel.WHOLE_REG):
 376                 comb += self.whole_reg.eq(1)
 377
 378         return m
 379
 380
 381 class DecodeCROut(Elaboratable):
 382     """Decodes input CR from instruction
 383
 384     CR indices - insn fields - (not the data *in* the CR) require only 3
 385     bits because they refer to CR0-CR7
 386     """
 387
 388     def __init__(self, dec):
 389         self.dec = dec
 390         self.rc_in = Signal(reset_less=True)
 391         self.sel_in = Signal(CROutSel, reset_less=True)
 392         self.insn_in = Signal(32, reset_less=True)
 393         self.cr_bitfield = Data(3, "cr_bitfield")
 394         self.whole_reg = Signal(reset_less=True)
 395
 396     def elaborate(self, platform):
 397         m = Module()
 398         comb = m.d.comb
 399
 400         comb += self.cr_bitfield.ok.eq(0)
 401         comb += self.whole_reg.eq(0)
 402         with m.Switch(self.sel_in):
 403             with m.Case(CROutSel.NONE):
 404                 pass # No bitfield activated
 405             with m.Case(CROutSel.CR0):
 406                 comb += self.cr_bitfield.data.eq(0)
 407                 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
 408             with m.Case(CROutSel.BF):
 409                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF[0:-1])
 410                 comb += self.cr_bitfield.ok.eq(1)
 411             with m.Case(CROutSel.BT):
 412                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 413                 comb += self.cr_bitfield.ok.eq(1)
 414             with m.Case(CROutSel.WHOLE_REG):
 415                 comb += self.whole_reg.eq(1)
 416
 417         return m
 418
 419
 420 class XerBits:
 421     def __init__(self):
 422         self.ca = Signal(2, reset_less=True)
 423         self.ov = Signal(2, reset_less=True)
 424         self.so = Signal(reset_less=True)
 425
 426     def ports(self):
 427         return [self.ca, self.ov, self.so]
 428
 429
 430 class Decode2ToExecute1Type(RecordObject):
 431
 432     def __init__(self, name=None):
 433
 434         RecordObject.__init__(self, name=name)
 435
 436         self.valid = Signal(reset_less=True)
 437         self.insn_type = Signal(InternalOp, reset_less=True)
 438         self.fn_unit = Signal(Function, reset_less=True)
 439         self.nia = Signal(64, reset_less=True)
 440         self.write_reg = Data(5, name="rego")
 441         self.write_ea = Data(5, name="ea") # for LD/ST in update mode
 442         self.read_reg1 = Data(5, name="reg1")
 443         self.read_reg2 = Data(5, name="reg2")
 444         self.read_reg3 = Data(5, name="reg3")
 445         self.imm_data = Data(64, name="imm")
 446         self.write_spr = Data(10, name="spro")
 447         self.read_spr1 = Data(10, name="spr1")
 448         self.read_spr2 = Data(10, name="spr2")
 449
 450         self.read_fast1 = Data(3, name="fast1")
 451         self.read_fast2 = Data(3, name="fast2")
 452         self.write_fast1 = Data(3, name="fasto1")
 453         self.write_fast2 = Data(3, name="fasto2")
 454
 455         self.read_cr1 = Data(3, name="cr_in1")
 456         self.read_cr2 = Data(3, name="cr_in2")
 457         self.read_cr3 = Data(3, name="cr_in2")
 458         self.read_cr_whole = Signal(reset_less=True)
 459         self.write_cr = Data(3, name="cr_out")
 460         self.write_cr_whole = Signal(reset_less=True)
 461         self.lk = Signal(reset_less=True)
 462         self.rc = Data(1, "rc")
 463         self.oe = Data(1, "oe")
 464         self.invert_a = Signal(reset_less=True)
 465         self.zero_a = Signal(reset_less=True)
 466         self.invert_out = Signal(reset_less=True)
 467         self.input_carry = Signal(CryIn, reset_less=True)
 468         self.output_carry = Signal(reset_less=True)
 469         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
 470         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
 471         self.is_32bit = Signal(reset_less=True)
 472         self.is_signed = Signal(reset_less=True)
 473         self.insn = Signal(32, reset_less=True)
 474         self.data_len = Signal(4, reset_less=True) # bytes
 475         self.byte_reverse  = Signal(reset_less=True)
 476         self.sign_extend  = Signal(reset_less=True)# do we need this?
 477         self.update  = Signal(reset_less=True) # LD/ST is "update" variant
 478
 479
 480 class PowerDecode2(Elaboratable):
 481
 482     def __init__(self, dec):
 483
 484         self.dec = dec
 485         self.e = Decode2ToExecute1Type()
 486
 487     def ports(self):
 488         return self.dec.ports() + self.e.ports()
 489
 490     def elaborate(self, platform):
 491         m = Module()
 492         comb = m.d.comb
 493
 494         # set up submodule decoders
 495         m.submodules.dec = self.dec
 496         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 497         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 498         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 499         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 500         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
 501         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 502         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 503         m.submodules.dec_cr_in = dec_cr_in = DecodeCRIn(self.dec)
 504         m.submodules.dec_cr_out = dec_cr_out = DecodeCROut(self.dec)
 505
 506         # copy instruction through...
 507         for i in [self.e.insn, dec_a.insn_in, dec_b.insn_in,
 508                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in, dec_rc.insn_in,
 509                   dec_oe.insn_in, dec_cr_in.insn_in, dec_cr_out.insn_in]:
 510             comb += i.eq(self.dec.opcode_in)
 511
 512         # ...and subdecoders' input fields
 513         comb += dec_a.sel_in.eq(self.dec.op.in1_sel)
 514         comb += dec_b.sel_in.eq(self.dec.op.in2_sel)
 515         comb += dec_c.sel_in.eq(self.dec.op.in3_sel)
 516         comb += dec_o.sel_in.eq(self.dec.op.out_sel)
 517         comb += dec_o2.sel_in.eq(self.dec.op.out_sel)
 518         comb += dec_rc.sel_in.eq(self.dec.op.rc_sel)
 519         comb += dec_oe.sel_in.eq(self.dec.op.rc_sel) # XXX should be OE sel
 520         comb += dec_cr_in.sel_in.eq(self.dec.op.cr_in)
 521         comb += dec_cr_out.sel_in.eq(self.dec.op.cr_out)
 522         comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
 523
 524         # decode LD/ST length
 525         with m.Switch(self.dec.op.ldst_len):
 526             with m.Case(LdstLen.is1B):
 527                 comb += self.e.data_len.eq(1)
 528             with m.Case(LdstLen.is2B):
 529                 comb += self.e.data_len.eq(2)
 530             with m.Case(LdstLen.is4B):
 531                 comb += self.e.data_len.eq(4)
 532             with m.Case(LdstLen.is8B):
 533                 comb += self.e.data_len.eq(8)
 534
 535         comb += self.e.nia.eq(0)    # XXX TODO
 536         comb += self.e.valid.eq(0)  # XXX TODO
 537         fu = self.dec.op.function_unit
 538         itype = Mux(fu == Function.NONE,
 539                     InternalOp.OP_ILLEGAL,
 540                     self.dec.op.internal_op)
 541         comb += self.e.insn_type.eq(itype)
 542         comb += self.e.fn_unit.eq(fu)
 543
 544         # registers a, b, c and out and out2 (LD/ST EA)
 545         comb += self.e.read_reg1.eq(dec_a.reg_out)
 546         comb += self.e.read_reg2.eq(dec_b.reg_out)
 547         comb += self.e.read_reg3.eq(dec_c.reg_out)
 548         comb += self.e.write_reg.eq(dec_o.reg_out)
 549         comb += self.e.write_ea.eq(dec_o2.reg_out)
 550         comb += self.e.imm_data.eq(dec_b.imm_out) # immediate in RB (usually)
 551         comb += self.e.zero_a.eq(dec_a.immz_out)  # RA==0 detected
 552
 553         # rc and oe out
 554         comb += self.e.rc.eq(dec_rc.rc_out)
 555         comb += self.e.oe.eq(dec_oe.oe_out)
 556
 557         # SPRs out
 558         comb += self.e.read_spr1.eq(dec_a.spr_out)
 559         comb += self.e.write_spr.eq(dec_o.spr_out)
 560
 561         # Fast regs out
 562         comb += self.e.read_fast1.eq(dec_a.fast_out)
 563         comb += self.e.read_fast2.eq(dec_b.fast_out)
 564         comb += self.e.write_fast1.eq(dec_o.fast_out)
 565         comb += self.e.write_fast2.eq(dec_o2.fast_out)
 566
 567         comb += self.e.read_cr1.eq(dec_cr_in.cr_bitfield)
 568         comb += self.e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
 569         comb += self.e.read_cr3.eq(dec_cr_in.cr_bitfield_o)
 570         comb += self.e.read_cr_whole.eq(dec_cr_in.whole_reg)
 571
 572         comb += self.e.write_cr.eq(dec_cr_out.cr_bitfield)
 573         comb += self.e.write_cr_whole.eq(dec_cr_out.whole_reg)
 574
 575         # decoded/selected instruction flags
 576         comb += self.e.invert_a.eq(self.dec.op.inv_a)
 577         comb += self.e.invert_out.eq(self.dec.op.inv_out)
 578         comb += self.e.input_carry.eq(self.dec.op.cry_in)   # carry comes in
 579         comb += self.e.output_carry.eq(self.dec.op.cry_out) # carry goes out
 580         comb += self.e.is_32bit.eq(self.dec.op.is_32b)
 581         comb += self.e.is_signed.eq(self.dec.op.sgn)
 582         with m.If(self.dec.op.lk):
 583             comb += self.e.lk.eq(self.dec.LK) # XXX TODO: accessor
 584
 585         comb += self.e.byte_reverse.eq(self.dec.op.br)
 586         comb += self.e.sign_extend.eq(self.dec.op.sgn_ext)
 587         comb += self.e.update.eq(self.dec.op.upd) # LD/ST "update" mode.
 588
 589
 590         # These should be removed eventually
 591         comb += self.e.input_cr.eq(self.dec.op.cr_in)   # condition reg comes in
 592         comb += self.e.output_cr.eq(self.dec.op.cr_out) # condition reg goes in
 593
 594
 595         return m
 596
 597     def regspecmap(self, regfile, regname):
 598         """regspecmap: provides PowerDecode2 with an encoding relationship
 599         to Function Unit port regfiles (read-enable, read regnum, write regnum)
 600         regfile and regname arguments are fields 1 and 2 from a given regspec.
 601         """
 602         return regspec_decode(self, regfile, regname)
 603
 604
 605 if __name__ == '__main__':
 606     pdecode = create_pdecode()
 607     dec2 = PowerDecode2(pdecode)
 608     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 609     with open("dec2.il", "w") as f:
 610         f.write(vl)
 611