1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
6 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
7 from nmigen
.cli
import rtlil
9 from soc
.decoder
.power_decoder
import create_pdecode
10 from soc
.decoder
.power_enums
import (InternalOp
, CryIn
, Function
,
11 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
15 class DecodeA(Elaboratable
):
16 """DecodeA from instruction
18 decodes register RA, whether immediate-zero, implicit and
22 def __init__(self
, dec
):
24 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
25 self
.insn_in
= Signal(32, reset_less
=True)
26 self
.reg_out
= Data(5, name
="reg_a")
27 self
.immz_out
= Signal(reset_less
=True)
28 self
.spr_out
= Data(10, "spr_a")
30 def elaborate(self
, platform
):
34 # select Register A field
35 with m
.If((self
.sel_in
== In1Sel
.RA
) |
36 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
37 (self
.reg_out
.data
!= Const(0, 5)))):
38 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
[0:-1])
39 comb
+= self
.reg_out
.ok
.eq(1)
41 # zero immediate requested
42 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
43 (self
.reg_out
.data
== Const(0, 5))):
44 comb
+= self
.immz_out
.eq(1)
46 # decode SPR1 based on instruction type
48 # BC or BCREG: potential implicit register (CTR)
49 with m
.If((op
.internal_op
== InternalOp
.OP_BC
) |
50 (op
.internal_op
== InternalOp
.OP_BCREG
)):
51 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
52 comb
+= self
.spr_out
.data
.eq(SPR
.CTR
) # constant: CTR
53 comb
+= self
.spr_out
.ok
.eq(1)
54 # MFSPR or MTSPR: move-from / move-to SPRs
55 with m
.If((op
.internal_op
== InternalOp
.OP_MFSPR
) |
56 (op
.internal_op
== InternalOp
.OP_MTSPR
)):
57 comb
+= self
.spr_out
.data
.eq(self
.dec
.SPR
[0:-1]) # SPR field, XFX
58 comb
+= self
.spr_out
.ok
.eq(1)
64 def __init__(self
, width
, name
):
66 self
.data
= Signal(width
, name
=name
, reset_less
=True)
67 self
.ok
= Signal(name
="%s_ok" % name
, reset_less
=True)
70 return [self
.data
.eq(rhs
.data
),
74 return [self
.data
, self
.ok
]
77 class DecodeB(Elaboratable
):
78 """DecodeB from instruction
80 decodes register RB, different forms of immediate (signed, unsigned),
84 def __init__(self
, dec
):
86 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
87 self
.insn_in
= Signal(32, reset_less
=True)
88 self
.reg_out
= Data(5, "reg_b")
89 self
.imm_out
= Data(64, "imm_b")
90 self
.spr_out
= Data(10, "spr_b")
92 def elaborate(self
, platform
):
96 # select Register B field
97 with m
.Switch(self
.sel_in
):
98 with m
.Case(In2Sel
.RB
):
99 comb
+= self
.reg_out
.data
.eq(self
.dec
.RB
[0:-1])
100 comb
+= self
.reg_out
.ok
.eq(1)
101 with m
.Case(In2Sel
.CONST_UI
):
102 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
[0:-1])
103 comb
+= self
.imm_out
.ok
.eq(1)
104 with m
.Case(In2Sel
.CONST_SI
): # TODO: sign-extend here?
105 comb
+= self
.imm_out
.data
.eq(self
.dec
.SI
[0:-1])
106 comb
+= self
.imm_out
.ok
.eq(1)
107 with m
.Case(In2Sel
.CONST_UI_HI
):
108 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
[0:-1]<<4)
109 comb
+= self
.imm_out
.ok
.eq(1)
110 with m
.Case(In2Sel
.CONST_SI_HI
): # TODO: sign-extend here?
111 comb
+= self
.imm_out
.data
.eq(self
.dec
.SI
[0:-1]<<4)
112 comb
+= self
.imm_out
.ok
.eq(1)
113 with m
.Case(In2Sel
.CONST_LI
):
114 comb
+= self
.imm_out
.data
.eq(self
.dec
.LI
[0:-1]<<2)
115 comb
+= self
.imm_out
.ok
.eq(1)
116 with m
.Case(In2Sel
.CONST_BD
):
117 comb
+= self
.imm_out
.data
.eq(self
.dec
.BD
[0:-1]<<2)
118 comb
+= self
.imm_out
.ok
.eq(1)
119 with m
.Case(In2Sel
.CONST_DS
):
120 comb
+= self
.imm_out
.data
.eq(self
.dec
.DS
[0:-1]<<2)
121 comb
+= self
.imm_out
.ok
.eq(1)
122 with m
.Case(In2Sel
.CONST_M1
):
123 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
124 comb
+= self
.imm_out
.ok
.eq(1)
125 with m
.Case(In2Sel
.CONST_SH
):
126 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
[0:-1])
127 comb
+= self
.imm_out
.ok
.eq(1)
128 with m
.Case(In2Sel
.CONST_SH32
):
129 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
[0:-1])
130 comb
+= self
.imm_out
.ok
.eq(1)
132 # decode SPR2 based on instruction type
134 # BCREG implicitly uses CTR or LR for 2nd reg
135 with m
.If(op
.internal_op
== InternalOp
.OP_BCREG
):
136 with m
.If(self
.dec
.FormXL
.XO
[9]): # 3.0B p38 top bit of XO
137 comb
+= self
.spr_out
.data
.eq(SPR
.CTR
)
139 comb
+= self
.spr_out
.data
.eq(SPR
.LR
)
140 comb
+= self
.spr_out
.ok
.eq(1)
145 class DecodeC(Elaboratable
):
146 """DecodeC from instruction
151 def __init__(self
, dec
):
153 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
154 self
.insn_in
= Signal(32, reset_less
=True)
155 self
.reg_out
= Data(5, "reg_c")
157 def elaborate(self
, platform
):
161 # select Register C field
162 with m
.If(self
.sel_in
== In3Sel
.RS
):
163 comb
+= self
.reg_out
.data
.eq(self
.dec
.RS
[0:-1])
164 comb
+= self
.reg_out
.ok
.eq(1)
169 class DecodeOut(Elaboratable
):
170 """DecodeOut from instruction
172 decodes output register RA, RT or SPR
175 def __init__(self
, dec
):
177 self
.sel_in
= Signal(OutSel
, reset_less
=True)
178 self
.insn_in
= Signal(32, reset_less
=True)
179 self
.reg_out
= Data(5, "reg_o")
180 self
.spr_out
= Data(10, "spr_o")
182 def elaborate(self
, platform
):
186 # select Register out field
187 with m
.Switch(self
.sel_in
):
188 with m
.Case(OutSel
.RT
):
189 comb
+= self
.reg_out
.data
.eq(self
.dec
.RT
[0:-1])
190 comb
+= self
.reg_out
.ok
.eq(1)
191 with m
.Case(OutSel
.RA
):
192 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
[0:-1])
193 comb
+= self
.reg_out
.ok
.eq(1)
194 with m
.Case(OutSel
.SPR
):
195 comb
+= self
.spr_out
.data
.eq(self
.dec
.SPR
[0:-1]) # from XFX
196 comb
+= self
.spr_out
.ok
.eq(1)
201 class DecodeRC(Elaboratable
):
202 """DecodeRc from instruction
204 decodes Record bit Rc
206 def __init__(self
, dec
):
208 self
.sel_in
= Signal(RC
, reset_less
=True)
209 self
.insn_in
= Signal(32, reset_less
=True)
210 self
.rc_out
= Data(1, "rc")
212 def elaborate(self
, platform
):
216 # select Record bit out field
217 with m
.Switch(self
.sel_in
):
219 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
[0:-1])
220 comb
+= self
.rc_out
.ok
.eq(1)
222 comb
+= self
.rc_out
.data
.eq(1)
223 comb
+= self
.rc_out
.ok
.eq(1)
224 with m
.Case(RC
.NONE
):
225 comb
+= self
.rc_out
.data
.eq(0)
226 comb
+= self
.rc_out
.ok
.eq(1)
231 class DecodeOE(Elaboratable
):
232 """DecodeOE from instruction
234 decodes OE field: uses RC decode detection which might not be good
236 -- For now, use "rc" in the decode table to decide whether oe exists.
237 -- This is not entirely correct architecturally: For mulhd and
238 -- mulhdu, the OE field is reserved. It remains to be seen what an
239 -- actual POWER9 does if we set it on those instructions, for now we
240 -- test that further down when assigning to the multiplier oe input.
242 def __init__(self
, dec
):
244 self
.sel_in
= Signal(RC
, reset_less
=True)
245 self
.insn_in
= Signal(32, reset_less
=True)
246 self
.oe_out
= Data(1, "oe")
248 def elaborate(self
, platform
):
252 # select OE bit out field
253 with m
.Switch(self
.sel_in
):
255 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
[0:-1])
256 comb
+= self
.oe_out
.ok
.eq(1)
263 self
.ca
= Signal(reset_less
=True)
264 self
.ca32
= Signal(reset_less
=True)
265 self
.ov
= Signal(reset_less
=True)
266 self
.ov32
= Signal(reset_less
=True)
267 self
.so
= Signal(reset_less
=True)
270 return [self
.ca
, self
.ca32
, self
.ov
, self
.ov32
, self
.so
, ]
273 class Decode2ToExecute1Type
:
277 self
.valid
= Signal(reset_less
=True)
278 self
.insn_type
= Signal(InternalOp
, reset_less
=True)
279 self
.nia
= Signal(64, reset_less
=True)
280 self
.write_reg
= Data(5, name
="rego")
281 self
.read_reg1
= Data(5, name
="reg1")
282 self
.read_reg2
= Data(5, name
="reg2")
283 self
.read_reg3
= Data(5, name
="reg3")
284 self
.imm_data
= Data(64, name
="imm")
285 self
.write_spr
= Data(10, name
="spro")
286 self
.read_spr1
= Data(10, name
="spr1")
287 self
.read_spr2
= Data(10, name
="spr2")
288 #self.read_data1 = Signal(64, reset_less=True)
289 #self.read_data2 = Signal(64, reset_less=True)
290 #self.read_data3 = Signal(64, reset_less=True)
291 #self.cr = Signal(32, reset_less=True) # NO: this is from the CR SPR
292 #self.xerc = XerBits() # NO: this is from the XER SPR
293 self
.lk
= Signal(reset_less
=True)
294 self
.rc
= Data(1, "rc")
295 self
.oe
= Data(1, "oe")
296 self
.invert_a
= Signal(reset_less
=True)
297 self
.invert_out
= Signal(reset_less
=True)
298 self
.input_carry
= Signal(CryIn
, reset_less
=True)
299 self
.output_carry
= Signal(reset_less
=True)
300 self
.input_cr
= Signal(reset_less
=True)
301 self
.output_cr
= Signal(reset_less
=True)
302 self
.is_32bit
= Signal(reset_less
=True)
303 self
.is_signed
= Signal(reset_less
=True)
304 self
.insn
= Signal(32, reset_less
=True)
305 self
.data_len
= Signal(4, reset_less
=True) # bytes
306 self
.byte_reverse
= Signal(reset_less
=True)
307 self
.sign_extend
= Signal(reset_less
=True)# do we need this?
308 self
.update
= Signal(reset_less
=True) # is this an update instruction?
311 return [self
.valid
, self
.insn_type
, self
.nia
,
312 #self.read_data1, self.read_data2, self.read_data3,
315 self
.invert_a
, self
.invert_out
,
316 self
.input_carry
, self
.output_carry
,
317 self
.input_cr
, self
.output_cr
,
318 self
.is_32bit
, self
.is_signed
,
320 self
.data_len
, self
.byte_reverse
, self
.sign_extend
,
324 self
.write_spr
.ports() + \
325 self
.read_spr1
.ports() + \
326 self
.read_spr2
.ports() + \
327 self
.write_reg
.ports() + \
328 self
.read_reg1
.ports() + \
329 self
.read_reg2
.ports() + \
330 self
.read_reg3
.ports() + \
331 self
.imm_data
.ports()
332 # + self.xerc.ports()
334 class PowerDecode2(Elaboratable
):
336 def __init__(self
, dec
):
339 self
.e
= Decode2ToExecute1Type()
342 return self
.dec
.ports() + self
.e
.ports()
344 def elaborate(self
, platform
):
348 # set up submodule decoders
349 m
.submodules
.dec
= self
.dec
350 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
351 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
352 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
353 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
354 m
.submodules
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
355 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
357 # copy instruction through...
358 for i
in [self
.e
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
359 dec_c
.insn_in
, dec_o
.insn_in
, dec_rc
.insn_in
,
361 comb
+= i
.eq(self
.dec
.opcode_in
)
363 # ...and subdecoders' input fields
364 comb
+= dec_a
.sel_in
.eq(self
.dec
.op
.in1_sel
)
365 comb
+= dec_b
.sel_in
.eq(self
.dec
.op
.in2_sel
)
366 comb
+= dec_c
.sel_in
.eq(self
.dec
.op
.in3_sel
)
367 comb
+= dec_o
.sel_in
.eq(self
.dec
.op
.out_sel
)
368 comb
+= dec_rc
.sel_in
.eq(self
.dec
.op
.rc_sel
)
369 comb
+= dec_oe
.sel_in
.eq(self
.dec
.op
.rc_sel
) # XXX should be OE sel
371 # decode LD/ST length
372 with m
.Switch(self
.dec
.op
.ldst_len
):
373 with m
.Case(LdstLen
.is1B
):
374 comb
+= self
.e
.data_len
.eq(1)
375 with m
.Case(LdstLen
.is2B
):
376 comb
+= self
.e
.data_len
.eq(2)
377 with m
.Case(LdstLen
.is4B
):
378 comb
+= self
.e
.data_len
.eq(4)
379 with m
.Case(LdstLen
.is8B
):
380 comb
+= self
.e
.data_len
.eq(8)
382 #comb += self.e.nia.eq(self.dec.nia) # XXX TODO
383 itype
= Mux(self
.dec
.op
.function_unit
== Function
.NONE
,
384 InternalOp
.OP_ILLEGAL
,
385 self
.dec
.op
.internal_op
)
386 comb
+= self
.e
.insn_type
.eq(itype
)
388 # registers a, b, c and out
389 comb
+= self
.e
.read_reg1
.eq(dec_a
.reg_out
)
390 comb
+= self
.e
.read_reg2
.eq(dec_b
.reg_out
)
391 comb
+= self
.e
.read_reg3
.eq(dec_c
.reg_out
)
392 comb
+= self
.e
.write_reg
.eq(dec_o
.reg_out
)
393 comb
+= self
.e
.imm_data
.eq(dec_b
.imm_out
)
396 comb
+= self
.e
.rc
.eq(dec_rc
.rc_out
)
397 comb
+= self
.e
.oe
.eq(dec_oe
.oe_out
)
400 comb
+= self
.e
.read_spr1
.eq(dec_a
.spr_out
)
401 comb
+= self
.e
.read_spr2
.eq(dec_b
.spr_out
)
402 comb
+= self
.e
.write_spr
.eq(dec_o
.spr_out
)
404 # decoded/selected instruction flags
405 comb
+= self
.e
.invert_a
.eq(self
.dec
.op
.inv_a
)
406 comb
+= self
.e
.invert_out
.eq(self
.dec
.op
.inv_out
)
407 comb
+= self
.e
.input_carry
.eq(self
.dec
.op
.cry_in
)
408 comb
+= self
.e
.output_carry
.eq(self
.dec
.op
.cry_out
)
409 comb
+= self
.e
.is_32bit
.eq(self
.dec
.op
.is_32b
)
410 comb
+= self
.e
.is_signed
.eq(self
.dec
.op
.sgn
)
411 with m
.If(self
.dec
.op
.lk
):
412 comb
+= self
.e
.lk
.eq(self
.dec
.LK
[0:-1]) # XXX TODO: accessor
414 comb
+= self
.e
.byte_reverse
.eq(self
.dec
.op
.br
)
415 comb
+= self
.e
.sign_extend
.eq(self
.dec
.op
.sgn_ext
)
416 comb
+= self
.e
.update
.eq(self
.dec
.op
.upd
)
418 comb
+= self
.e
.input_cr
.eq(self
.dec
.op
.cr_in
)
419 comb
+= self
.e
.output_cr
.eq(self
.dec
.op
.cr_out
)
424 if __name__
== '__main__':
425 pdecode
= create_pdecode()
426 dec2
= PowerDecode2(pdecode
)
427 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
428 with
open("dec2.il", "w") as f
: