src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
   7 from nmigen.cli import rtlil
   8
   9 from nmutil.iocontrol import RecordObject
  10 from nmutil.extend import exts
  11
  12 from soc.decoder.power_regspec_map import regspec_decode
  13 from soc.decoder.power_decoder import create_pdecode
  14 from soc.decoder.power_enums import (InternalOp, CryIn, Function,
  15                                      CRInSel, CROutSel,
  16                                      LdstLen, In1Sel, In2Sel, In3Sel,
  17                                      OutSel, SPR, RC)
  18
  19 from soc.regfile.regfiles import FastRegs
  20
  21 # see traptype (and trap main_stage.py)
  22
  23 TT_FP = 1<<0
  24 TT_PRIV = 1<<1
  25 TT_TRAP = 1<<2
  26 TT_ADDR = 1<<3
  27
  28
  29 def instr_is_priv(m, op, insn):
  30     """determines if the instruction is privileged or not
  31     """
  32     comb = m.d.comb
  33     Signal = is_priv_insn(reset_less=True)
  34     with m.Switch(op):
  35         with m.Case(InternalOp.OP_ATTN)  : comb += is_priv_insn.eq(1)
  36         with m.Case(InternalOp.OP_MFMSR) : comb += is_priv_insn.eq(1)
  37         with m.Case(InternalOp.OP_MTMSRD): comb += is_priv_insn.eq(1)
  38         with m.Case(InternalOp.OP_RFID)  : comb += is_priv_insn.eq(1)
  39         with m.Case(InternalOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
  40     with m.If(op == OP_MFSPR | op == OP_MTSPR):
  41         with m.If(insn[20]): # field XFX.spr[-1] i think
  42             comb += is_priv_insn.eq(1)
  43     return is_priv_insn
  44
  45
  46 class DecodeA(Elaboratable):
  47     """DecodeA from instruction
  48
  49     decodes register RA, whether immediate-zero, implicit and
  50     explicit CSRs
  51     """
  52
  53     def __init__(self, dec):
  54         self.dec = dec
  55         self.sel_in = Signal(In1Sel, reset_less=True)
  56         self.insn_in = Signal(32, reset_less=True)
  57         self.reg_out = Data(5, name="reg_a")
  58         self.immz_out = Signal(reset_less=True)
  59         self.spr_out = Data(10, "spr_a")
  60         self.fast_out = Data(3, "fast_a")
  61
  62     def elaborate(self, platform):
  63         m = Module()
  64         comb = m.d.comb
  65
  66         # select Register A field
  67         ra = Signal(5, reset_less=True)
  68         comb += ra.eq(self.dec.RA)
  69         with m.If((self.sel_in == In1Sel.RA) |
  70                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  71                    (ra != Const(0, 5)))):
  72             comb += self.reg_out.data.eq(ra)
  73             comb += self.reg_out.ok.eq(1)
  74
  75         # zero immediate requested
  76         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
  77                   (self.reg_out.data == Const(0, 5))):
  78             comb += self.immz_out.eq(1)
  79
  80         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
  81         with m.If(self.sel_in == In1Sel.RS):
  82             comb += self.reg_out.data.eq(self.dec.RS)
  83             comb += self.reg_out.ok.eq(1)
  84
  85         # decode Fast-SPR based on instruction type
  86         op = self.dec.op
  87         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
  88         with m.If(op.internal_op == InternalOp.OP_BC):
  89             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
  90                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
  91                 comb += self.fast_out.ok.eq(1)
  92         with m.Elif(op.internal_op == InternalOp.OP_BCREG):
  93             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
  94             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
  95             with m.If(xo9 & ~xo5):
  96                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
  97                 comb += self.fast_out.ok.eq(1)
  98
  99         # MFSPR move from SPRs
 100         with m.If(op.internal_op == InternalOp.OP_MFSPR):
 101             # XXX TODO: fast/slow SPR decoding and mapping
 102             comb += self.spr_out.data.eq(self.dec.SPR) # SPR field, XFX
 103             comb += self.spr_out.ok.eq(1)
 104
 105         return m
 106
 107
 108 class Data(Record):
 109
 110     def __init__(self, width, name):
 111         name_ok = "%s_ok" % name
 112         layout = ((name, width), (name_ok, 1))
 113         Record.__init__(self, layout)
 114         self.data = getattr(self, name) # convenience
 115         self.ok = getattr(self, name_ok) # convenience
 116         self.data.reset_less = True # grrr
 117         self.reset_less = True # grrr
 118
 119     def ports(self):
 120         return [self.data, self.ok]
 121
 122
 123 class DecodeB(Elaboratable):
 124     """DecodeB from instruction
 125
 126     decodes register RB, different forms of immediate (signed, unsigned),
 127     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 128     by industry-standard convention, "lane 2" is where fully-decoded
 129     immediates are muxed in.
 130     """
 131
 132     def __init__(self, dec):
 133         self.dec = dec
 134         self.sel_in = Signal(In2Sel, reset_less=True)
 135         self.insn_in = Signal(32, reset_less=True)
 136         self.reg_out = Data(5, "reg_b")
 137         self.imm_out = Data(64, "imm_b")
 138         self.fast_out = Data(3, "fast_b")
 139
 140     def elaborate(self, platform):
 141         m = Module()
 142         comb = m.d.comb
 143
 144         # select Register B field
 145         with m.Switch(self.sel_in):
 146             with m.Case(In2Sel.RB):
 147                 comb += self.reg_out.data.eq(self.dec.RB)
 148                 comb += self.reg_out.ok.eq(1)
 149             with m.Case(In2Sel.RS):
 150                 comb += self.reg_out.data.eq(self.dec.RS) # for M-Form shiftrot
 151                 comb += self.reg_out.ok.eq(1)
 152             with m.Case(In2Sel.CONST_UI):
 153                 comb += self.imm_out.data.eq(self.dec.UI)
 154                 comb += self.imm_out.ok.eq(1)
 155             with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here?
 156                 comb += self.imm_out.data.eq(
 157                     exts(self.dec.SI, 16, 64))
 158                 comb += self.imm_out.ok.eq(1)
 159             with m.Case(In2Sel.CONST_UI_HI):
 160                 comb += self.imm_out.data.eq(self.dec.UI<<16)
 161                 comb += self.imm_out.ok.eq(1)
 162             with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here?
 163                 comb += self.imm_out.data.eq(self.dec.SI<<16)
 164                 comb += self.imm_out.data.eq(
 165                     exts(self.dec.SI << 16, 32, 64))
 166                 comb += self.imm_out.ok.eq(1)
 167             with m.Case(In2Sel.CONST_LI):
 168                 comb += self.imm_out.data.eq(self.dec.LI<<2)
 169                 comb += self.imm_out.ok.eq(1)
 170             with m.Case(In2Sel.CONST_BD):
 171                 comb += self.imm_out.data.eq(self.dec.BD<<2)
 172                 comb += self.imm_out.ok.eq(1)
 173             with m.Case(In2Sel.CONST_DS):
 174                 comb += self.imm_out.data.eq(self.dec.DS<<2)
 175                 comb += self.imm_out.ok.eq(1)
 176             with m.Case(In2Sel.CONST_M1):
 177                 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
 178                 comb += self.imm_out.ok.eq(1)
 179             with m.Case(In2Sel.CONST_SH):
 180                 comb += self.imm_out.data.eq(self.dec.sh)
 181                 comb += self.imm_out.ok.eq(1)
 182             with m.Case(In2Sel.CONST_SH32):
 183                 comb += self.imm_out.data.eq(self.dec.SH32)
 184                 comb += self.imm_out.ok.eq(1)
 185
 186         # decode SPR2 based on instruction type
 187         op = self.dec.op
 188         # BCREG implicitly uses LR or TAR for 2nd reg
 189         # CTR however is already in fast_spr1 *not* 2.
 190         with m.If(op.internal_op == InternalOp.OP_BCREG):
 191             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
 192             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
 193             with m.If(~xo9):
 194                 comb += self.fast_out.data.eq(FastRegs.LR)
 195                 comb += self.fast_out.ok.eq(1)
 196             with m.Elif(xo5):
 197                 comb += self.fast_out.data.eq(FastRegs.TAR)
 198                 comb += self.fast_out.ok.eq(1)
 199
 200         return m
 201
 202
 203 class DecodeC(Elaboratable):
 204     """DecodeC from instruction
 205
 206     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 207     """
 208
 209     def __init__(self, dec):
 210         self.dec = dec
 211         self.sel_in = Signal(In3Sel, reset_less=True)
 212         self.insn_in = Signal(32, reset_less=True)
 213         self.reg_out = Data(5, "reg_c")
 214
 215     def elaborate(self, platform):
 216         m = Module()
 217         comb = m.d.comb
 218
 219         # select Register C field
 220         with m.Switch(self.sel_in):
 221             with m.Case(In3Sel.RB):
 222                 comb += self.reg_out.data.eq(self.dec.RB) # for M-Form shiftrot
 223                 comb += self.reg_out.ok.eq(1)
 224             with m.Case(In3Sel.RS):
 225                 comb += self.reg_out.data.eq(self.dec.RS)
 226                 comb += self.reg_out.ok.eq(1)
 227
 228         return m
 229
 230
 231 class DecodeOut(Elaboratable):
 232     """DecodeOut from instruction
 233
 234     decodes output register RA, RT or SPR
 235     """
 236
 237     def __init__(self, dec):
 238         self.dec = dec
 239         self.sel_in = Signal(OutSel, reset_less=True)
 240         self.insn_in = Signal(32, reset_less=True)
 241         self.reg_out = Data(5, "reg_o")
 242         self.spr_out = Data(10, "spr_o")
 243         self.fast_out = Data(3, "fast_o")
 244
 245     def elaborate(self, platform):
 246         m = Module()
 247         comb = m.d.comb
 248         op = self.dec.op
 249
 250         # select Register out field
 251         with m.Switch(self.sel_in):
 252             with m.Case(OutSel.RT):
 253                 comb += self.reg_out.data.eq(self.dec.RT)
 254                 comb += self.reg_out.ok.eq(1)
 255             with m.Case(OutSel.RA):
 256                 comb += self.reg_out.data.eq(self.dec.RA)
 257                 comb += self.reg_out.ok.eq(1)
 258             with m.Case(OutSel.SPR):
 259                 comb += self.spr_out.data.eq(self.dec.SPR) # from XFX
 260                 comb += self.spr_out.ok.eq(1)
 261                 # TODO MTSPR 1st spr (fast)
 262                 with m.If(op.internal_op == InternalOp.OP_MTSPR):
 263                     pass
 264                     """
 265                     sprn := decode_spr_num(f_in.insn);
 266                     v.ispr1 := fast_spr_num(sprn);
 267                     -- Make slow SPRs single issue
 268                     if is_fast_spr(v.ispr1) = '0' then
 269                         v.decode.sgl_pipe := '1';
 270                         -- send MMU-related SPRs to loadstore1
 271                         case sprn is
 272                         when SPR_DAR | SPR_DSISR | SPR_PID | SPR_PRTBL =>
 273                             v.decode.unit := LDST;
 274                         when others =>
 275                         end case;
 276                     end if;
 277                     """
 278
 279
 280         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
 281         op = self.dec.op
 282         with m.If((op.internal_op == InternalOp.OP_BC) |
 283                   (op.internal_op == InternalOp.OP_BCREG)):
 284             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
 285                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
 286                 comb += self.fast_out.ok.eq(1)
 287
 288         # RFID 1st spr (fast)
 289         with m.If(op.internal_op == InternalOp.OP_RFID):
 290             comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
 291             comb += self.fast_out.ok.eq(1)
 292
 293         return m
 294
 295
 296 class DecodeOut2(Elaboratable):
 297     """DecodeOut2 from instruction
 298
 299     decodes output registers
 300     """
 301
 302     def __init__(self, dec):
 303         self.dec = dec
 304         self.sel_in = Signal(OutSel, reset_less=True)
 305         self.lk = Signal(reset_less=True)
 306         self.insn_in = Signal(32, reset_less=True)
 307         self.reg_out = Data(5, "reg_o")
 308         self.fast_out = Data(3, "fast_o")
 309
 310     def elaborate(self, platform):
 311         m = Module()
 312         comb = m.d.comb
 313
 314         # update mode LD/ST uses read-reg A also as an output
 315         with m.If(self.dec.op.upd):
 316             comb += self.reg_out.eq(self.dec.RA)
 317             comb += self.reg_out.ok.eq(1)
 318
 319         # BC or BCREG: potential implicit register (LR) output
 320         op = self.dec.op
 321         with m.If((op.internal_op == InternalOp.OP_BC) |
 322                   (op.internal_op == InternalOp.OP_BCREG)):
 323             with m.If(self.lk): # "link" mode
 324                 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
 325                 comb += self.fast_out.ok.eq(1)
 326
 327         # RFID 2nd spr (fast)
 328         with m.If(op.internal_op == InternalOp.OP_RFID):
 329                 comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
 330                 comb += self.fast_out.ok.eq(1)
 331
 332         return m
 333
 334
 335 class DecodeRC(Elaboratable):
 336     """DecodeRc from instruction
 337
 338     decodes Record bit Rc
 339     """
 340     def __init__(self, dec):
 341         self.dec = dec
 342         self.sel_in = Signal(RC, reset_less=True)
 343         self.insn_in = Signal(32, reset_less=True)
 344         self.rc_out = Data(1, "rc")
 345
 346     def elaborate(self, platform):
 347         m = Module()
 348         comb = m.d.comb
 349
 350         # select Record bit out field
 351         with m.Switch(self.sel_in):
 352             with m.Case(RC.RC):
 353                 comb += self.rc_out.data.eq(self.dec.Rc)
 354                 comb += self.rc_out.ok.eq(1)
 355             with m.Case(RC.ONE):
 356                 comb += self.rc_out.data.eq(1)
 357                 comb += self.rc_out.ok.eq(1)
 358             with m.Case(RC.NONE):
 359                 comb += self.rc_out.data.eq(0)
 360                 comb += self.rc_out.ok.eq(1)
 361
 362         return m
 363
 364
 365 class DecodeOE(Elaboratable):
 366     """DecodeOE from instruction
 367
 368     decodes OE field: uses RC decode detection which might not be good
 369
 370     -- For now, use "rc" in the decode table to decide whether oe exists.
 371     -- This is not entirely correct architecturally: For mulhd and
 372     -- mulhdu, the OE field is reserved. It remains to be seen what an
 373     -- actual POWER9 does if we set it on those instructions, for now we
 374     -- test that further down when assigning to the multiplier oe input.
 375     """
 376     def __init__(self, dec):
 377         self.dec = dec
 378         self.sel_in = Signal(RC, reset_less=True)
 379         self.insn_in = Signal(32, reset_less=True)
 380         self.oe_out = Data(1, "oe")
 381
 382     def elaborate(self, platform):
 383         m = Module()
 384         comb = m.d.comb
 385
 386         # select OE bit out field
 387         with m.Switch(self.sel_in):
 388             with m.Case(RC.RC):
 389                 comb += self.oe_out.data.eq(self.dec.OE)
 390                 comb += self.oe_out.ok.eq(1)
 391
 392         return m
 393
 394 class DecodeCRIn(Elaboratable):
 395     """Decodes input CR from instruction
 396
 397     CR indices - insn fields - (not the data *in* the CR) require only 3
 398     bits because they refer to CR0-CR7
 399     """
 400
 401     def __init__(self, dec):
 402         self.dec = dec
 403         self.sel_in = Signal(CRInSel, reset_less=True)
 404         self.insn_in = Signal(32, reset_less=True)
 405         self.cr_bitfield = Data(3, "cr_bitfield")
 406         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 407         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 408         self.whole_reg = Signal(reset_less=True)
 409
 410     def elaborate(self, platform):
 411         m = Module()
 412         comb = m.d.comb
 413
 414         comb += self.cr_bitfield.ok.eq(0)
 415         comb += self.cr_bitfield_b.ok.eq(0)
 416         comb += self.whole_reg.eq(0)
 417         with m.Switch(self.sel_in):
 418             with m.Case(CRInSel.NONE):
 419                 pass # No bitfield activated
 420             with m.Case(CRInSel.CR0):
 421                 comb += self.cr_bitfield.data.eq(0)
 422                 comb += self.cr_bitfield.ok.eq(1)
 423             with m.Case(CRInSel.BI):
 424                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 425                 comb += self.cr_bitfield.ok.eq(1)
 426             with m.Case(CRInSel.BFA):
 427                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 428                 comb += self.cr_bitfield.ok.eq(1)
 429             with m.Case(CRInSel.BA_BB):
 430                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 431                 comb += self.cr_bitfield.ok.eq(1)
 432                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 433                 comb += self.cr_bitfield_b.ok.eq(1)
 434                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 435                 comb += self.cr_bitfield_o.ok.eq(1)
 436             with m.Case(CRInSel.BC):
 437                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 438                 comb += self.cr_bitfield.ok.eq(1)
 439             with m.Case(CRInSel.WHOLE_REG):
 440                 comb += self.whole_reg.eq(1)
 441
 442         return m
 443
 444
 445 class DecodeCROut(Elaboratable):
 446     """Decodes input CR from instruction
 447
 448     CR indices - insn fields - (not the data *in* the CR) require only 3
 449     bits because they refer to CR0-CR7
 450     """
 451
 452     def __init__(self, dec):
 453         self.dec = dec
 454         self.rc_in = Signal(reset_less=True)
 455         self.sel_in = Signal(CROutSel, reset_less=True)
 456         self.insn_in = Signal(32, reset_less=True)
 457         self.cr_bitfield = Data(3, "cr_bitfield")
 458         self.whole_reg = Signal(reset_less=True)
 459
 460     def elaborate(self, platform):
 461         m = Module()
 462         comb = m.d.comb
 463
 464         comb += self.cr_bitfield.ok.eq(0)
 465         comb += self.whole_reg.eq(0)
 466         with m.Switch(self.sel_in):
 467             with m.Case(CROutSel.NONE):
 468                 pass # No bitfield activated
 469             with m.Case(CROutSel.CR0):
 470                 comb += self.cr_bitfield.data.eq(0)
 471                 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
 472             with m.Case(CROutSel.BF):
 473                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
 474                 comb += self.cr_bitfield.ok.eq(1)
 475             with m.Case(CROutSel.BT):
 476                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 477                 comb += self.cr_bitfield.ok.eq(1)
 478             with m.Case(CROutSel.WHOLE_REG):
 479                 comb += self.whole_reg.eq(1)
 480
 481         return m
 482
 483
 484 class XerBits:
 485     def __init__(self):
 486         self.ca = Signal(2, reset_less=True)
 487         self.ov = Signal(2, reset_less=True)
 488         self.so = Signal(reset_less=True)
 489
 490     def ports(self):
 491         return [self.ca, self.ov, self.so]
 492
 493
 494 class Decode2ToExecute1Type(RecordObject):
 495
 496     def __init__(self, name=None):
 497
 498         RecordObject.__init__(self, name=name)
 499
 500         self.valid = Signal(reset_less=True)
 501         self.insn_type = Signal(InternalOp, reset_less=True)
 502         self.fn_unit = Signal(Function, reset_less=True)
 503         self.nia = Signal(64, reset_less=True)
 504         self.write_reg = Data(5, name="rego")
 505         self.write_ea = Data(5, name="ea") # for LD/ST in update mode
 506         self.read_reg1 = Data(5, name="reg1")
 507         self.read_reg2 = Data(5, name="reg2")
 508         self.read_reg3 = Data(5, name="reg3")
 509         self.imm_data = Data(64, name="imm")
 510         self.write_spr = Data(10, name="spro")
 511         self.read_spr1 = Data(10, name="spr1")
 512         self.read_spr2 = Data(10, name="spr2")
 513
 514         self.read_fast1 = Data(3, name="fast1")
 515         self.read_fast2 = Data(3, name="fast2")
 516         self.write_fast1 = Data(3, name="fasto1")
 517         self.write_fast2 = Data(3, name="fasto2")
 518
 519         self.read_cr1 = Data(3, name="cr_in1")
 520         self.read_cr2 = Data(3, name="cr_in2")
 521         self.read_cr3 = Data(3, name="cr_in2")
 522         self.read_cr_whole = Signal(reset_less=True)
 523         self.write_cr = Data(3, name="cr_out")
 524         self.write_cr_whole = Signal(reset_less=True)
 525         self.lk = Signal(reset_less=True)
 526         self.rc = Data(1, "rc")
 527         self.oe = Data(1, "oe")
 528         self.invert_a = Signal(reset_less=True)
 529         self.zero_a = Signal(reset_less=True)
 530         self.invert_out = Signal(reset_less=True)
 531         self.input_carry = Signal(CryIn, reset_less=True)
 532         self.output_carry = Signal(reset_less=True)
 533         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
 534         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
 535         self.is_32bit = Signal(reset_less=True)
 536         self.is_signed = Signal(reset_less=True)
 537         self.insn = Signal(32, reset_less=True)
 538         self.data_len = Signal(4, reset_less=True) # bytes
 539         self.byte_reverse  = Signal(reset_less=True)
 540         self.sign_extend  = Signal(reset_less=True)# do we need this?
 541         self.update  = Signal(reset_less=True) # LD/ST is "update" variant
 542         self.traptype  = Signal(4, reset_less=True) # see trap main_stage.py
 543         self.trapaddr  = Signal(13, reset_less=True)
 544
 545
 546 class PowerDecode2(Elaboratable):
 547
 548     def __init__(self, dec):
 549
 550         self.dec = dec
 551         self.e = Decode2ToExecute1Type()
 552
 553     def ports(self):
 554         return self.dec.ports() + self.e.ports()
 555
 556     def elaborate(self, platform):
 557         m = Module()
 558         comb = m.d.comb
 559         e, op = self.e, self.dec.op
 560
 561         # set up submodule decoders
 562         m.submodules.dec = self.dec
 563         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 564         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 565         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 566         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 567         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
 568         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 569         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 570         m.submodules.dec_cr_in = dec_cr_in = DecodeCRIn(self.dec)
 571         m.submodules.dec_cr_out = dec_cr_out = DecodeCROut(self.dec)
 572
 573         # copy instruction through...
 574         for i in [e.insn, dec_a.insn_in, dec_b.insn_in,
 575                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in, dec_rc.insn_in,
 576                   dec_oe.insn_in, dec_cr_in.insn_in, dec_cr_out.insn_in]:
 577             comb += i.eq(self.dec.opcode_in)
 578
 579         # ...and subdecoders' input fields
 580         comb += dec_a.sel_in.eq(op.in1_sel)
 581         comb += dec_b.sel_in.eq(op.in2_sel)
 582         comb += dec_c.sel_in.eq(op.in3_sel)
 583         comb += dec_o.sel_in.eq(op.out_sel)
 584         comb += dec_o2.sel_in.eq(op.out_sel)
 585         comb += dec_o2.lk.eq(e.lk)
 586         comb += dec_rc.sel_in.eq(op.rc_sel)
 587         comb += dec_oe.sel_in.eq(op.rc_sel) # XXX should be OE sel
 588         comb += dec_cr_in.sel_in.eq(op.cr_in)
 589         comb += dec_cr_out.sel_in.eq(op.cr_out)
 590         comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
 591
 592
 593         comb += e.nia.eq(0)    # XXX TODO (or remove? not sure yet)
 594         fu = op.function_unit
 595         itype = Mux(fu == Function.NONE, InternalOp.OP_ILLEGAL, op.internal_op)
 596         comb += e.insn_type.eq(itype)
 597         comb += e.fn_unit.eq(fu)
 598
 599         # registers a, b, c and out and out2 (LD/ST EA)
 600         comb += e.read_reg1.eq(dec_a.reg_out)
 601         comb += e.read_reg2.eq(dec_b.reg_out)
 602         comb += e.read_reg3.eq(dec_c.reg_out)
 603         comb += e.write_reg.eq(dec_o.reg_out)
 604         comb += e.write_ea.eq(dec_o2.reg_out)
 605         comb += e.imm_data.eq(dec_b.imm_out) # immediate in RB (usually)
 606         comb += e.zero_a.eq(dec_a.immz_out)  # RA==0 detected
 607
 608         # rc and oe out
 609         comb += e.rc.eq(dec_rc.rc_out)
 610         comb += e.oe.eq(dec_oe.oe_out)
 611
 612         # SPRs out
 613         comb += e.read_spr1.eq(dec_a.spr_out)
 614         comb += e.write_spr.eq(dec_o.spr_out)
 615
 616         # Fast regs out
 617         comb += e.read_fast1.eq(dec_a.fast_out)
 618         comb += e.read_fast2.eq(dec_b.fast_out)
 619         comb += e.write_fast1.eq(dec_o.fast_out)
 620         comb += e.write_fast2.eq(dec_o2.fast_out)
 621
 622         comb += e.read_cr1.eq(dec_cr_in.cr_bitfield)
 623         comb += e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
 624         comb += e.read_cr3.eq(dec_cr_in.cr_bitfield_o)
 625         comb += e.read_cr_whole.eq(dec_cr_in.whole_reg)
 626
 627         comb += e.write_cr.eq(dec_cr_out.cr_bitfield)
 628         comb += e.write_cr_whole.eq(dec_cr_out.whole_reg)
 629
 630         # decoded/selected instruction flags
 631         comb += e.data_len.eq(op.ldst_len)
 632         comb += e.invert_a.eq(op.inv_a)
 633         comb += e.invert_out.eq(op.inv_out)
 634         comb += e.input_carry.eq(op.cry_in)   # carry comes in
 635         comb += e.output_carry.eq(op.cry_out) # carry goes out
 636         comb += e.is_32bit.eq(op.is_32b)
 637         comb += e.is_signed.eq(op.sgn)
 638         with m.If(op.lk):
 639             comb += e.lk.eq(self.dec.LK) # XXX TODO: accessor
 640
 641         comb += e.byte_reverse.eq(op.br)
 642         comb += e.sign_extend.eq(op.sgn_ext)
 643         comb += e.update.eq(op.upd) # LD/ST "update" mode.
 644
 645
 646         # These should be removed eventually
 647         comb += e.input_cr.eq(op.cr_in)   # condition reg comes in
 648         comb += e.output_cr.eq(op.cr_out) # condition reg goes in
 649
 650         return m
 651
 652         # privileged instruction
 653         with m.If(instr_is_priv(m, op.internal_op, e.insn) & msr[MSR_PR]):
 654             # don't request registers RA/RT
 655             comb += e.read_reg1.eq(0)
 656             comb += e.read_reg2.eq(0)
 657             comb += e.read_reg3.eq(0)
 658             comb += e.write_reg.eq(0)
 659             comb += e.write_ea.eq(0)
 660             # privileged instruction trap
 661             comb += op.internal_op.eq(InternalOp.OP_TRAP)
 662             comb += e.traptype.eq(TT_PRIV) # request privileged instruction
 663             comb += e.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
 664         return m
 665
 666     def regspecmap(self, regfile, regname):
 667         """regspecmap: provides PowerDecode2 with an encoding relationship
 668         to Function Unit port regfiles (read-enable, read regnum, write regnum)
 669         regfile and regname arguments are fields 1 and 2 from a given regspec.
 670         """
 671         return regspec_decode(self.e, regfile, regname)
 672
 673     def rdflags(self, cu):
 674         rdl = []
 675         for idx in range(cu.n_src):
 676             regfile, regname, _ = cu.get_in_spec(idx)
 677             rdflag, read, write = self.regspecmap(regfile, regname)
 678             rdl.append(rdflag)
 679         print ("rdflags", rdl)
 680         return Cat(*rdl)
 681
 682
 683 if __name__ == '__main__':
 684     pdecode = create_pdecode()
 685     dec2 = PowerDecode2(pdecode)
 686     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 687     with open("dec2.il", "w") as f:
 688         f.write(vl)
 689