1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from nmutil
.util
import sel
13 from soc
.regfile
.regfiles
import XERRegs
15 from nmutil
.picker
import PriorityPicker
16 from nmutil
.iocontrol
import RecordObject
17 from nmutil
.extend
import exts
19 from soc
.experiment
.mem_types
import LDSTException
21 from soc
.decoder
.power_svp64_prefix
import SVP64PrefixDecoder
22 from soc
.decoder
.power_regspec_map
import regspec_decode_read
23 from soc
.decoder
.power_regspec_map
import regspec_decode_write
24 from soc
.decoder
.power_decoder
import create_pdecode
25 from soc
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
27 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
28 OutSel
, SPR
, RC
, LDSTMode
,
30 from soc
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
32 from soc
.sv
.svp64
import SVP64Rec
33 from soc
.consts
import (MSR
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
, field
,
34 SPEC_SIZE
, SPECb
, SPEC_AUG_SIZE
, SVP64CROffs
)
36 from soc
.regfile
.regfiles
import FastRegs
37 from soc
.consts
import TT
38 from soc
.config
.state
import CoreState
39 from soc
.regfile
.util
import spr_to_fast
42 def decode_spr_num(spr
):
43 return Cat(spr
[5:10], spr
[0:5])
46 def instr_is_priv(m
, op
, insn
):
47 """determines if the instruction is privileged or not
50 is_priv_insn
= Signal(reset_less
=True)
52 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
53 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
54 comb
+= is_priv_insn
.eq(1)
55 with m
.Case(MicrOp
.OP_TLBIE
) : comb
+= is_priv_insn
.eq(1)
56 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
57 with m
.If(insn
[20]): # field XFX.spr[-1] i think
58 comb
+= is_priv_insn
.eq(1)
62 class SPRMap(Elaboratable
):
63 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
67 self
.spr_i
= Signal(10, reset_less
=True)
68 self
.spr_o
= Data(SPR
, name
="spr_o")
69 self
.fast_o
= Data(3, name
="fast_o")
71 def elaborate(self
, platform
):
73 with m
.Switch(self
.spr_i
):
74 for i
, x
in enumerate(SPR
):
76 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
77 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
78 for x
, v
in spr_to_fast
.items():
80 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
81 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
85 class SVP64ExtraSpec(Elaboratable
):
86 """SVP64ExtraSpec - decodes SVP64 Extra specification.
88 selects the required EXTRA2/3 field.
90 see https://libre-soc.org/openpower/sv/svp64/
93 self
.extra
= Signal(9, reset_less
=True)
94 self
.etype
= Signal(SVEtype
, reset_less
=True) # 2 or 3 bits
95 self
.idx
= Signal(SVEXTRA
, reset_less
=True) # which part of extra
96 self
.spec
= Signal(3) # EXTRA spec for the register
98 def elaborate(self
, platform
):
104 # back in the LDSTRM-* and RM-* files generated by sv_analysis.py
105 # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
106 # which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
107 # the register-extension information. extract those now
108 with m
.Switch(self
.etype
):
109 # 2-bit index selection mode
110 with m
.Case(SVEtype
.EXTRA2
):
111 with m
.Switch(self
.idx
):
112 with m
.Case(SVEXTRA
.Idx0
): # 1st 2 bits [0:1]
113 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX0_VEC
])
114 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX0_MSB
])
115 with m
.Case(SVEXTRA
.Idx1
): # 2nd 2 bits [2:3]
116 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX1_VEC
])
117 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX1_MSB
])
118 with m
.Case(SVEXTRA
.Idx2
): # 3rd 2 bits [4:5]
119 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX2_VEC
])
120 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX2_MSB
])
121 with m
.Case(SVEXTRA
.Idx3
): # 4th 2 bits [6:7]
122 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX3_VEC
])
123 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX3_MSB
])
124 # 3-bit index selection mode
125 with m
.Case(SVEtype
.EXTRA3
):
126 with m
.Switch(self
.idx
):
127 with m
.Case(SVEXTRA
.Idx0
): # 1st 3 bits [0:2]
128 extra3_idx0
= sel(m
, extra
, EXTRA3
.IDX0
)
129 comb
+= spec
.eq(extra3_idx0
)
130 with m
.Case(SVEXTRA
.Idx1
): # 2nd 3 bits [3:5]
131 extra3_idx1
= sel(m
, extra
, EXTRA3
.IDX1
)
132 comb
+= spec
.eq(extra3_idx1
)
133 with m
.Case(SVEXTRA
.Idx2
): # 3rd 3 bits [6:8]
134 extra3_idx2
= sel(m
, extra
, EXTRA3
.IDX2
)
135 comb
+= spec
.eq(extra3_idx2
)
136 # cannot fit more than 9 bits so there is no 4th thing
141 class SVP64RegExtra(SVP64ExtraSpec
):
142 """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
144 incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
145 depending on info in one of the positions in the EXTRA field.
147 designed so that "no change" to the 5-bit register number occurs if
148 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
150 see https://libre-soc.org/openpower/sv/svp64/
153 SVP64ExtraSpec
.__init
__(self
)
154 self
.reg_in
= Signal(5) # incoming reg number (5 bits, RA, RB)
155 self
.reg_out
= Signal(7) # extra-augmented output (7 bits)
156 self
.isvec
= Signal(1) # reg is marked as vector if true
158 def elaborate(self
, platform
):
159 m
= super().elaborate(platform
) # select required EXTRA2/3
162 # first get the spec. if not changed it's "scalar identity behaviour"
163 # which is zero which is ok.
166 # now decode it. bit 0 is "scalar/vector". note that spec could be zero
167 # from above, which (by design) has the effect of "no change", below.
169 # simple: isvec is top bit of spec
170 comb
+= self
.isvec
.eq(spec
[SPEC
.VEC
])
171 # extra bits for register number augmentation
172 spec_aug
= Signal(SPEC_AUG_SIZE
)
173 comb
+= spec_aug
.eq(field(spec
, SPECb
.MSB
, SPECb
.LSB
, SPEC_SIZE
))
175 # decode vector differently from scalar
176 with m
.If(self
.isvec
):
177 # Vector: shifted up, extra in LSBs (RA << 2) | spec[1:2]
178 comb
+= self
.reg_out
.eq(Cat(spec_aug
, self
.reg_in
))
180 # Scalar: not shifted up, extra in MSBs RA | (spec[1:2] << 5)
181 comb
+= self
.reg_out
.eq(Cat(self
.reg_in
, spec_aug
))
186 class SVP64CRExtra(SVP64ExtraSpec
):
187 """SVP64CRExtra - decodes SVP64 Extra fields to determine CR extension
189 incoming 3-bit CR is turned into a 7-bit and marked as scalar/vector
190 depending on info in one of the positions in the EXTRA field.
192 yes, really, 128 CRs. INT is 128, FP is 128, therefore CRs are 128.
194 designed so that "no change" to the 3-bit CR register number occurs if
195 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
197 see https://libre-soc.org/openpower/sv/svp64/appendix
200 SVP64ExtraSpec
.__init
__(self
)
201 self
.cr_in
= Signal(3) # incoming CR number (3 bits, BA[0:2], BFA)
202 self
.cr_out
= Signal(7) # extra-augmented CR output (7 bits)
203 self
.isvec
= Signal(1) # reg is marked as vector if true
205 def elaborate(self
, platform
):
206 m
= super().elaborate(platform
) # select required EXTRA2/3
209 # first get the spec. if not changed it's "scalar identity behaviour"
210 # which is zero which is ok.
213 # now decode it. bit 0 is "scalar/vector". note that spec could be zero
214 # from above, which (by design) has the effect of "no change", below.
216 # simple: isvec is top bit of spec
217 comb
+= self
.isvec
.eq(spec
[SPEC
.VEC
])
218 # extra bits for register number augmentation
219 spec_aug
= Signal(SPEC_AUG_SIZE
)
220 comb
+= spec_aug
.eq(field(spec
, SPECb
.MSB
, SPECb
.LSB
, SPEC_SIZE
))
222 # decode vector differently from scalar, insert bits 1 and 2 accordingly
223 with m
.If(self
.isvec
):
224 # Vector: shifted up, extra in LSBs (CR << 4) | (spec[1:2] << 2)
225 comb
+= self
.cr_out
.eq(Cat(Const(0, 2), spec_aug
, self
.cr_in
))
227 # Scalar: not shifted up, extra in MSBs CR | (spec[1:2] << 3)
228 comb
+= self
.cr_out
.eq(Cat(self
.cr_in
, spec_aug
))
233 class DecodeA(Elaboratable
):
234 """DecodeA from instruction
236 decodes register RA, implicit and explicit CSRs
239 def __init__(self
, dec
):
241 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
242 self
.insn_in
= Signal(32, reset_less
=True)
243 self
.reg_out
= Data(5, name
="reg_a")
244 self
.spr_out
= Data(SPR
, "spr_a")
245 self
.fast_out
= Data(3, "fast_a")
247 def elaborate(self
, platform
):
252 m
.submodules
.sprmap
= sprmap
= SPRMap()
254 # select Register A field
255 ra
= Signal(5, reset_less
=True)
256 comb
+= ra
.eq(self
.dec
.RA
)
257 with m
.If((self
.sel_in
== In1Sel
.RA
) |
258 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
259 (ra
!= Const(0, 5)))):
260 comb
+= reg
.data
.eq(ra
)
263 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
264 # moved it to 1st position (in1_sel)... because
265 rs
= Signal(5, reset_less
=True)
266 comb
+= rs
.eq(self
.dec
.RS
)
267 with m
.If(self
.sel_in
== In1Sel
.RS
):
268 comb
+= reg
.data
.eq(rs
)
271 # decode Fast-SPR based on instruction type
272 with m
.Switch(op
.internal_op
):
274 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
275 with m
.Case(MicrOp
.OP_BC
):
276 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
278 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
279 comb
+= self
.fast_out
.ok
.eq(1)
280 with m
.Case(MicrOp
.OP_BCREG
):
281 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
282 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
283 with m
.If(xo9
& ~xo5
):
285 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
286 comb
+= self
.fast_out
.ok
.eq(1)
288 # MFSPR move from SPRs
289 with m
.Case(MicrOp
.OP_MFSPR
):
290 spr
= Signal(10, reset_less
=True)
291 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
292 comb
+= sprmap
.spr_i
.eq(spr
)
293 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
294 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
299 class DecodeAImm(Elaboratable
):
300 """DecodeA immediate from instruction
302 decodes register RA, whether immediate-zero, implicit and
306 def __init__(self
, dec
):
308 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
309 self
.immz_out
= Signal(reset_less
=True)
311 def elaborate(self
, platform
):
315 # zero immediate requested
316 ra
= Signal(5, reset_less
=True)
317 comb
+= ra
.eq(self
.dec
.RA
)
318 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) & (ra
== Const(0, 5))):
319 comb
+= self
.immz_out
.eq(1)
324 class DecodeB(Elaboratable
):
325 """DecodeB from instruction
327 decodes register RB, different forms of immediate (signed, unsigned),
328 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
329 by industry-standard convention, "lane 2" is where fully-decoded
330 immediates are muxed in.
333 def __init__(self
, dec
):
335 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
336 self
.insn_in
= Signal(32, reset_less
=True)
337 self
.reg_out
= Data(7, "reg_b")
338 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
339 self
.fast_out
= Data(3, "fast_b")
341 def elaborate(self
, platform
):
347 # select Register B field
348 with m
.Switch(self
.sel_in
):
349 with m
.Case(In2Sel
.RB
):
350 comb
+= reg
.data
.eq(self
.dec
.RB
)
352 with m
.Case(In2Sel
.RS
):
353 # for M-Form shiftrot
354 comb
+= reg
.data
.eq(self
.dec
.RS
)
357 # decode SPR2 based on instruction type
358 # BCREG implicitly uses LR or TAR for 2nd reg
359 # CTR however is already in fast_spr1 *not* 2.
360 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
361 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
362 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
364 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
365 comb
+= self
.fast_out
.ok
.eq(1)
367 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
368 comb
+= self
.fast_out
.ok
.eq(1)
373 class DecodeBImm(Elaboratable
):
374 """DecodeB immediate from instruction
376 def __init__(self
, dec
):
378 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
379 self
.imm_out
= Data(64, "imm_b")
381 def elaborate(self
, platform
):
385 # select Register B Immediate
386 with m
.Switch(self
.sel_in
):
387 with m
.Case(In2Sel
.CONST_UI
): # unsigned
388 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
389 comb
+= self
.imm_out
.ok
.eq(1)
390 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
391 si
= Signal(16, reset_less
=True)
392 comb
+= si
.eq(self
.dec
.SI
)
393 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
394 comb
+= self
.imm_out
.ok
.eq(1)
395 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
396 si_hi
= Signal(32, reset_less
=True)
397 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
398 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
399 comb
+= self
.imm_out
.ok
.eq(1)
400 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
401 ui
= Signal(16, reset_less
=True)
402 comb
+= ui
.eq(self
.dec
.UI
)
403 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
404 comb
+= self
.imm_out
.ok
.eq(1)
405 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
406 li
= Signal(26, reset_less
=True)
407 comb
+= li
.eq(self
.dec
.LI
<< 2)
408 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
409 comb
+= self
.imm_out
.ok
.eq(1)
410 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
411 bd
= Signal(16, reset_less
=True)
412 comb
+= bd
.eq(self
.dec
.BD
<< 2)
413 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
414 comb
+= self
.imm_out
.ok
.eq(1)
415 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
416 ds
= Signal(16, reset_less
=True)
417 comb
+= ds
.eq(self
.dec
.DS
<< 2)
418 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
419 comb
+= self
.imm_out
.ok
.eq(1)
420 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
421 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
422 comb
+= self
.imm_out
.ok
.eq(1)
423 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
424 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
425 comb
+= self
.imm_out
.ok
.eq(1)
426 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
427 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
428 comb
+= self
.imm_out
.ok
.eq(1)
433 class DecodeC(Elaboratable
):
434 """DecodeC from instruction
436 decodes register RC. this is "lane 3" into some CompUnits (not many)
439 def __init__(self
, dec
):
441 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
442 self
.insn_in
= Signal(32, reset_less
=True)
443 self
.reg_out
= Data(5, "reg_c")
445 def elaborate(self
, platform
):
451 # select Register C field
452 with m
.Switch(self
.sel_in
):
453 with m
.Case(In3Sel
.RB
):
454 # for M-Form shiftrot
455 comb
+= reg
.data
.eq(self
.dec
.RB
)
457 with m
.Case(In3Sel
.RS
):
458 comb
+= reg
.data
.eq(self
.dec
.RS
)
464 class DecodeOut(Elaboratable
):
465 """DecodeOut from instruction
467 decodes output register RA, RT or SPR
470 def __init__(self
, dec
):
472 self
.sel_in
= Signal(OutSel
, reset_less
=True)
473 self
.insn_in
= Signal(32, reset_less
=True)
474 self
.reg_out
= Data(5, "reg_o")
475 self
.spr_out
= Data(SPR
, "spr_o")
476 self
.fast_out
= Data(3, "fast_o")
478 def elaborate(self
, platform
):
481 m
.submodules
.sprmap
= sprmap
= SPRMap()
485 # select Register out field
486 with m
.Switch(self
.sel_in
):
487 with m
.Case(OutSel
.RT
):
488 comb
+= reg
.data
.eq(self
.dec
.RT
)
490 with m
.Case(OutSel
.RA
):
491 comb
+= reg
.data
.eq(self
.dec
.RA
)
493 with m
.Case(OutSel
.SPR
):
494 spr
= Signal(10, reset_less
=True)
495 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
496 # MFSPR move to SPRs - needs mapping
497 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
498 comb
+= sprmap
.spr_i
.eq(spr
)
499 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
500 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
503 with m
.Switch(op
.internal_op
):
505 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
506 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
507 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
509 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
510 comb
+= self
.fast_out
.ok
.eq(1)
512 # RFID 1st spr (fast)
513 with m
.Case(MicrOp
.OP_RFID
):
514 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
515 comb
+= self
.fast_out
.ok
.eq(1)
520 class DecodeOut2(Elaboratable
):
521 """DecodeOut2 from instruction
523 decodes output registers (2nd one). note that RA is *implicit* below,
524 which now causes problems with SVP64
526 TODO: SVP64 is a little more complex, here. svp64 allows extending
527 by one more destination by having one more EXTRA field. RA-as-src
528 is not the same as RA-as-dest. limited in that it's the same first
529 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
530 for operations that have src-as-dest: mostly this is LD/ST-with-update
531 but there are others.
534 def __init__(self
, dec
):
536 self
.sel_in
= Signal(OutSel
, reset_less
=True)
537 self
.lk
= Signal(reset_less
=True)
538 self
.insn_in
= Signal(32, reset_less
=True)
539 self
.reg_out
= Data(5, "reg_o2")
540 self
.fast_out
= Data(3, "fast_o2")
542 def elaborate(self
, platform
):
546 #m.submodules.svdec = svdec = SVP64RegExtra()
548 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
549 #reg = Signal(5, reset_less=True)
551 if hasattr(self
.dec
.op
, "upd"):
552 # update mode LD/ST uses read-reg A also as an output
553 with m
.If(self
.dec
.op
.upd
== LDSTMode
.update
):
554 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
555 comb
+= self
.reg_out
.ok
.eq(1)
557 # B, BC or BCREG: potential implicit register (LR) output
558 # these give bl, bcl, bclrl, etc.
559 with m
.Switch(op
.internal_op
):
561 # BC* implicit register (LR)
562 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
563 with m
.If(self
.lk
): # "link" mode
564 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
) # constant: LR
565 comb
+= self
.fast_out
.ok
.eq(1)
567 # RFID 2nd spr (fast)
568 with m
.Case(MicrOp
.OP_RFID
):
569 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
570 comb
+= self
.fast_out
.ok
.eq(1)
575 class DecodeRC(Elaboratable
):
576 """DecodeRc from instruction
578 decodes Record bit Rc
581 def __init__(self
, dec
):
583 self
.sel_in
= Signal(RC
, reset_less
=True)
584 self
.insn_in
= Signal(32, reset_less
=True)
585 self
.rc_out
= Data(1, "rc")
587 def elaborate(self
, platform
):
591 # select Record bit out field
592 with m
.Switch(self
.sel_in
):
594 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
595 comb
+= self
.rc_out
.ok
.eq(1)
597 comb
+= self
.rc_out
.data
.eq(1)
598 comb
+= self
.rc_out
.ok
.eq(1)
599 with m
.Case(RC
.NONE
):
600 comb
+= self
.rc_out
.data
.eq(0)
601 comb
+= self
.rc_out
.ok
.eq(1)
606 class DecodeOE(Elaboratable
):
607 """DecodeOE from instruction
609 decodes OE field: uses RC decode detection which might not be good
611 -- For now, use "rc" in the decode table to decide whether oe exists.
612 -- This is not entirely correct architecturally: For mulhd and
613 -- mulhdu, the OE field is reserved. It remains to be seen what an
614 -- actual POWER9 does if we set it on those instructions, for now we
615 -- test that further down when assigning to the multiplier oe input.
618 def __init__(self
, dec
):
620 self
.sel_in
= Signal(RC
, reset_less
=True)
621 self
.insn_in
= Signal(32, reset_less
=True)
622 self
.oe_out
= Data(1, "oe")
624 def elaborate(self
, platform
):
629 with m
.Switch(op
.internal_op
):
631 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
633 # XXX ARGH! ignoring OE causes incompatibility with microwatt
634 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
635 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
636 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
637 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
638 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
639 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
643 # all other ops decode OE field
645 # select OE bit out field
646 with m
.Switch(self
.sel_in
):
648 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
649 comb
+= self
.oe_out
.ok
.eq(1)
654 class DecodeCRIn(Elaboratable
):
655 """Decodes input CR from instruction
657 CR indices - insn fields - (not the data *in* the CR) require only 3
658 bits because they refer to CR0-CR7
661 def __init__(self
, dec
):
663 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
664 self
.insn_in
= Signal(32, reset_less
=True)
665 self
.cr_bitfield
= Data(3, "cr_bitfield")
666 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
667 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
668 self
.whole_reg
= Data(8, "cr_fxm")
669 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
671 def elaborate(self
, platform
):
675 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
678 # zero-initialisation
679 comb
+= self
.cr_bitfield
.ok
.eq(0)
680 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
681 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
682 comb
+= self
.whole_reg
.ok
.eq(0)
683 comb
+= self
.sv_override
.eq(0)
685 # select the relevant CR bitfields
686 with m
.Switch(self
.sel_in
):
687 with m
.Case(CRInSel
.NONE
):
688 pass # No bitfield activated
689 with m
.Case(CRInSel
.CR0
):
690 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
691 comb
+= self
.cr_bitfield
.ok
.eq(1)
692 comb
+= self
.sv_override
.eq(1)
693 with m
.Case(CRInSel
.CR1
):
694 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
695 comb
+= self
.cr_bitfield
.ok
.eq(1)
696 comb
+= self
.sv_override
.eq(2)
697 with m
.Case(CRInSel
.BI
):
698 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
699 comb
+= self
.cr_bitfield
.ok
.eq(1)
700 with m
.Case(CRInSel
.BFA
):
701 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
702 comb
+= self
.cr_bitfield
.ok
.eq(1)
703 with m
.Case(CRInSel
.BA_BB
):
704 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
705 comb
+= self
.cr_bitfield
.ok
.eq(1)
706 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
707 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
708 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
709 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
710 with m
.Case(CRInSel
.BC
):
711 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
712 comb
+= self
.cr_bitfield
.ok
.eq(1)
713 with m
.Case(CRInSel
.WHOLE_REG
):
714 comb
+= self
.whole_reg
.ok
.eq(1)
715 move_one
= Signal(reset_less
=True)
716 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
717 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
718 # must one-hot the FXM field
719 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
720 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
722 # otherwise use all of it
723 comb
+= self
.whole_reg
.data
.eq(0xff)
728 class DecodeCROut(Elaboratable
):
729 """Decodes input CR from instruction
731 CR indices - insn fields - (not the data *in* the CR) require only 3
732 bits because they refer to CR0-CR7
735 def __init__(self
, dec
):
737 self
.rc_in
= Signal(reset_less
=True)
738 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
739 self
.insn_in
= Signal(32, reset_less
=True)
740 self
.cr_bitfield
= Data(3, "cr_bitfield")
741 self
.whole_reg
= Data(8, "cr_fxm")
742 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
744 def elaborate(self
, platform
):
748 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
751 comb
+= self
.cr_bitfield
.ok
.eq(0)
752 comb
+= self
.whole_reg
.ok
.eq(0)
753 comb
+= self
.sv_override
.eq(0)
755 # please note these MUST match (setting of cr_bitfield.ok) exactly
756 # with write_cr0 below in PowerDecoder2. the reason it's separated
757 # is to avoid having duplicate copies of DecodeCROut in multiple
758 # PowerDecoderSubsets. register decoding should be a one-off in
759 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
761 with m
.Switch(self
.sel_in
):
762 with m
.Case(CROutSel
.NONE
):
763 pass # No bitfield activated
764 with m
.Case(CROutSel
.CR0
):
765 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
766 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
767 comb
+= self
.sv_override
.eq(1)
768 with m
.Case(CROutSel
.CR1
):
769 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
770 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
771 comb
+= self
.sv_override
.eq(2)
772 with m
.Case(CROutSel
.BF
):
773 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
774 comb
+= self
.cr_bitfield
.ok
.eq(1)
775 with m
.Case(CROutSel
.BT
):
776 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
777 comb
+= self
.cr_bitfield
.ok
.eq(1)
778 with m
.Case(CROutSel
.WHOLE_REG
):
779 comb
+= self
.whole_reg
.ok
.eq(1)
780 move_one
= Signal(reset_less
=True)
781 comb
+= move_one
.eq(self
.insn_in
[20])
782 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
784 # must one-hot the FXM field
785 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
786 with m
.If(ppick
.en_o
):
787 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
789 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
791 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
793 # otherwise use all of it
794 comb
+= self
.whole_reg
.data
.eq(0xff)
798 # dictionary of Input Record field names that, if they exist,
799 # will need a corresponding CSV Decoder file column (actually, PowerOp)
800 # to be decoded (this includes the single bit names)
801 record_names
= {'insn_type': 'internal_op',
802 'fn_unit': 'function_unit',
806 'imm_data': 'in2_sel',
807 'invert_in': 'inv_a',
808 'invert_out': 'inv_out',
811 'output_carry': 'cry_out',
812 'input_carry': 'cry_in',
813 'is_32bit': 'is_32b',
816 'data_len': 'ldst_len',
817 'byte_reverse': 'br',
818 'sign_extend': 'sgn_ext',
823 class PowerDecodeSubset(Elaboratable
):
824 """PowerDecodeSubset: dynamic subset decoder
826 only fields actually requested are copied over. hence, "subset" (duh).
828 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
830 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
833 self
.fn_name
= fn_name
835 opkls
= Decode2ToOperand
836 self
.do
= opkls(fn_name
)
837 col_subset
= self
.get_col_subset(self
.do
)
839 # only needed for "main" PowerDecode2
841 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
)
843 # create decoder if one not already given
845 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
846 row_subset
=self
.rowsubsetfn
)
849 # state information needed by the Decoder
851 state
= CoreState("dec2")
854 def get_col_subset(self
, do
):
855 subset
= { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
856 for k
, v
in record_names
.items():
859 print ("get_col_subset", self
.fn_name
, do
.fields
, subset
)
862 def rowsubsetfn(self
, opcode
, row
):
863 return row
['unit'] == self
.fn_name
866 return self
.dec
.ports() + self
.e
.ports() + self
.sv_rm
.ports()
868 def needs_field(self
, field
, op_field
):
873 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
875 def do_copy(self
, field
, val
, final
=False):
876 if final
or self
.final
:
880 if hasattr(do
, field
) and val
is not None:
881 return getattr(do
, field
).eq(val
)
884 def op_get(self
, op_field
):
885 return getattr(self
.dec
.op
, op_field
, None)
887 def elaborate(self
, platform
):
891 op
, do
= self
.dec
.op
, self
.do
892 msr
, cia
= state
.msr
, state
.pc
893 # fill in for a normal instruction (not an exception)
894 # copy over if non-exception, non-privileged etc. is detected
896 if self
.fn_name
is None:
899 name
= self
.fn_name
+ "tmp"
900 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
)
902 # set up submodule decoders
903 m
.submodules
.dec
= self
.dec
904 m
.submodules
.dec_rc
= self
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
905 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
907 # copy instruction through...
908 for i
in [do
.insn
, dec_rc
.insn_in
, dec_oe
.insn_in
, ]:
909 comb
+= i
.eq(self
.dec
.opcode_in
)
911 # ...and subdecoders' input fields
912 comb
+= dec_rc
.sel_in
.eq(op
.rc_sel
)
913 comb
+= dec_oe
.sel_in
.eq(op
.rc_sel
) # XXX should be OE sel
916 comb
+= self
.do_copy("msr", msr
)
917 comb
+= self
.do_copy("cia", cia
)
919 # set up instruction type
920 # no op: defaults to OP_ILLEGAL
921 # FIX https://bugs.libre-soc.org/show_bug.cgi?id=607
922 comb
+= self
.do_copy("insn_type", self
.op_get("internal_op"))
924 # function unit for decoded instruction: requires minor redirect
926 fn
= self
.op_get("function_unit")
927 spr
= Signal(10, reset_less
=True)
928 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
930 # Microwatt doesn't implement the partition table
931 # instead has PRTBL(SVSRR0) register (SPR) to point to process table
932 with m
.If(((self
.dec
.op
.internal_op
== MicrOp
.OP_MTSPR
) |
933 (self
.dec
.op
.internal_op
== MicrOp
.OP_MFSPR
)) &
934 ((spr
== SPR
.DSISR
.value
) |
(spr
== SPR
.DAR
.value
) |
935 (spr
==SPR
.SVSRR0
.value
) |
(spr
==SPR
.PIDR
.value
))):
936 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
938 comb
+= self
.do_copy("fn_unit",fn
)
941 if self
.needs_field("zero_a", "in1_sel"):
942 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
943 comb
+= dec_ai
.sel_in
.eq(op
.in1_sel
)
944 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
945 if self
.needs_field("imm_data", "in2_sel"):
946 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
947 comb
+= dec_bi
.sel_in
.eq(op
.in2_sel
)
948 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
951 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
952 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
954 # CR in/out - note: these MUST match with what happens in
956 rc_out
= self
.dec_rc
.rc_out
.data
957 with m
.Switch(op
.cr_out
):
958 with m
.Case(CROutSel
.CR0
, CROutSel
.CR1
):
959 comb
+= self
.do_copy("write_cr0", rc_out
) # only when RC=1
960 with m
.Case(CROutSel
.BF
, CROutSel
.BT
):
961 comb
+= self
.do_copy("write_cr0", 1)
963 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
964 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
966 # decoded/selected instruction flags
967 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
968 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
969 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
970 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
971 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
972 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
973 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
974 lk
= self
.op_get("lk")
977 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
979 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
980 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
981 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
986 class PowerDecode2(PowerDecodeSubset
):
987 """PowerDecode2: the main instruction decoder.
989 whilst PowerDecode is responsible for decoding the actual opcode, this
990 module encapsulates further specialist, sparse information and
991 expansion of fields that is inconvenient to have in the CSV files.
992 for example: the encoding of the immediates, which are detected
993 and expanded out to their full value from an annotated (enum)
996 implicit register usage is also set up, here. for example: OP_BC
997 requires implicitly reading CTR, OP_RFID requires implicitly writing
1000 in addition, PowerDecoder2 is responsible for detecting whether
1001 instructions are illegal (or privileged) or not, and instead of
1002 just leaving at that, *replacing* the instruction to execute with
1003 a suitable alternative (trap).
1005 LDSTExceptions are done the cycle _after_ they're detected (after
1006 they come out of LDSTCompUnit). basically despite the instruction
1007 being decoded, the results of the decode are completely ignored
1008 and "exception.happened" used to set the "actual" instruction to
1009 "OP_TRAP". the LDSTException data structure gets filled in,
1010 in the CompTrapOpSubset and that's what it fills in SRR.
1012 to make this work, TestIssuer must notice "exception.happened"
1013 after the (failed) LD/ST and copies the LDSTException info from
1014 the output, into here (PowerDecoder2). without incrementing PC.
1017 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
1018 super().__init
__(dec
, opkls
, fn_name
, final
, state
)
1019 self
.exc
= LDSTException("dec2_exc")
1021 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
1022 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
1023 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1024 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1025 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1026 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1027 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1028 self
.o_isvec
= Signal(1, name
="reg_o_isvec")
1029 self
.o2_isvec
= Signal(1, name
="reg_o2_isvec")
1030 self
.no_in_vec
= Signal(1, name
="no_in_vec") # no inputs are vectors
1031 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs are vectors
1033 def get_col_subset(self
, opkls
):
1034 subset
= super().get_col_subset(opkls
)
1035 subset
.add("asmcode")
1036 subset
.add("in1_sel")
1037 subset
.add("in2_sel")
1038 subset
.add("in3_sel")
1039 subset
.add("out_sel")
1040 subset
.add("sv_in1")
1041 subset
.add("sv_in2")
1042 subset
.add("sv_in3")
1043 subset
.add("sv_out")
1044 subset
.add("sv_cr_in")
1045 subset
.add("sv_cr_out")
1046 subset
.add("SV_Etype")
1047 subset
.add("SV_Ptype")
1049 subset
.add("internal_op")
1053 def elaborate(self
, platform
):
1054 m
= super().elaborate(platform
)
1057 e_out
, op
, do_out
= self
.e
, self
.dec
.op
, self
.e
.do
1058 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1059 rc_out
= self
.dec_rc
.rc_out
.data
1063 # fill in for a normal instruction (not an exception)
1064 # copy over if non-exception, non-privileged etc. is detected
1066 # set up submodule decoders
1067 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
1068 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
1069 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
1070 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
1071 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
)
1072 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
)
1073 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
)
1075 # and SVP64 Extra decoders
1076 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1077 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1078 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1079 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1080 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1081 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1082 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1083 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1084 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1086 # debug access to crout_svdec (used in get_pdecode_cr_out)
1087 self
.crout_svdec
= crout_svdec
1089 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1090 reg
= Signal(5, reset_less
=True)
1092 # copy instruction through...
1093 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1094 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
,
1095 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1096 comb
+= i
.eq(self
.dec
.opcode_in
)
1099 comb
+= self
.dec_cr_in
.sel_in
.eq(op
.cr_in
)
1100 comb
+= self
.dec_cr_out
.sel_in
.eq(op
.cr_out
)
1101 comb
+= self
.dec_cr_out
.rc_in
.eq(rc_out
)
1104 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1105 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1107 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1108 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1109 # which in turn were auto-generated by sv_analysis.py
1110 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1114 comb
+= crout_svdec
.idx
.eq(op
.sv_cr_out
) # SVP64 CR out
1115 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1118 # CR in - index selection slightly different due to shared CR field sigh
1119 cr_a_idx
= Signal(SVEXTRA
)
1120 cr_b_idx
= Signal(SVEXTRA
)
1122 # these change slightly, when decoding BA/BB. really should have
1123 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1124 comb
+= cr_a_idx
.eq(op
.sv_cr_in
)
1125 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1126 with m
.If(op
.sv_cr_in
== SVEXTRA
.Idx_1_2
.value
):
1127 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1128 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1130 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1131 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1132 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1134 # indices are slightly different, BA/BB mess sorted above
1135 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1136 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1137 comb
+= crin_svdec_o
.idx
.eq(op
.sv_cr_out
) # SVP64 CR out
1139 # ...and subdecoders' input fields
1140 comb
+= dec_a
.sel_in
.eq(op
.in1_sel
)
1141 comb
+= dec_b
.sel_in
.eq(op
.in2_sel
)
1142 comb
+= dec_c
.sel_in
.eq(op
.in3_sel
)
1143 comb
+= dec_o
.sel_in
.eq(op
.out_sel
)
1144 comb
+= dec_o2
.sel_in
.eq(op
.out_sel
)
1145 if hasattr(do
, "lk"):
1146 comb
+= dec_o2
.lk
.eq(do
.lk
)
1148 # get SVSTATE srcstep (TODO: elwidth, dststep etc.) needed below
1149 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1150 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1152 # registers a, b, c and out and out2 (LD/ST EA)
1153 for to_reg
, fromreg
, svdec
in (
1154 (e
.read_reg1
, dec_a
.reg_out
, in1_svdec
),
1155 (e
.read_reg2
, dec_b
.reg_out
, in2_svdec
),
1156 (e
.read_reg3
, dec_c
.reg_out
, in3_svdec
),
1157 (e
.write_reg
, dec_o
.reg_out
, o_svdec
),
1158 (e
.write_ea
, dec_o2
.reg_out
, o2_svdec
)):
1159 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1160 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
1161 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1162 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1163 # detect if Vectorised: add srcstep if yes. TODO: a LOT.
1164 # this trick only holds when elwidth=default and in single-pred
1165 with m
.If(svdec
.isvec
):
1166 comb
+= to_reg
.data
.eq(srcstep
+svdec
.reg_out
) # 7-bit output
1168 comb
+= to_reg
.data
.eq(svdec
.reg_out
) # 7-bit output
1170 comb
+= in1_svdec
.idx
.eq(op
.sv_in1
) # SVP64 reg #1 (matches in1_sel)
1171 comb
+= in2_svdec
.idx
.eq(op
.sv_in2
) # SVP64 reg #2 (matches in2_sel)
1172 comb
+= in3_svdec
.idx
.eq(op
.sv_in3
) # SVP64 reg #3 (matches in3_sel)
1173 comb
+= o_svdec
.idx
.eq(op
.sv_out
) # SVP64 output (matches out_sel)
1174 # XXX TODO - work out where this should come from. the problem is
1175 # that LD-with-update is implied (computed from "is instruction in
1176 # "update mode" rather than specified cleanly as its own CSV column
1177 #comb += o2_svdec.idx.eq(op.sv_out) # SVP64 output (implicit)
1179 # output reg-is-vectorised (and when no input or output is vectorised)
1180 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1181 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1182 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1183 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1184 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1185 # TODO add SPRs here. must be True when *all* are scalar
1186 l
= map(lambda svdec
: svdec
.isvec
, [in1_svdec
, in2_svdec
, in3_svdec
,
1187 crin_svdec
, crin_svdec_b
, crin_svdec_o
]:
1188 comb
+= self
.no_in_vec
.eq(~
Cat(*l
).bool()) # all input scalar
1189 l
= map(lambda svdec
: svdec
.isvec
, [o2_svdec
, o_svdec
, crout_svdec
])
1190 comb
+= self
.no_out_vec
.eq(~
Cat(*l
).bool()) # all output scalar
1193 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1194 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1197 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1198 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1199 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
)
1200 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
)
1202 # condition registers (CR)
1203 for to_reg
, cr
, name
, svdec
in (
1204 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", crin_svdec
),
1205 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", crin_svdec_b
),
1206 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", crin_svdec_o
),
1207 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", crout_svdec
)):
1208 fromreg
= getattr(cr
, name
)
1209 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1210 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
1211 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1212 with m
.If(svdec
.isvec
):
1213 # check if this is CR0 or CR1: treated differently
1214 # (does not "listen" to EXTRA2/3 spec for a start)
1215 # also: the CRs start from completely different locations
1216 with m
.If(cr
.sv_override
== 1): # CR0
1217 offs
= SVP64CROffs
.CR0
1218 comb
+= to_reg
.data
.eq(srcstep
+offs
)
1219 with m
.Elif(cr
.sv_override
== 2): # CR1
1220 offs
= SVP64CROffs
.CR1
1221 comb
+= to_reg
.data
.eq(srcstep
+1)
1223 comb
+= to_reg
.data
.eq(srcstep
+svdec
.cr_out
) # 7-bit output
1225 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1226 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1228 # sigh this is exactly the sort of thing for which the
1229 # decoder is designed to not need. MTSPR, MFSPR and others need
1230 # access to the XER bits. however setting e.oe is not appropriate
1231 with m
.If(op
.internal_op
== MicrOp
.OP_MFSPR
):
1232 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1233 with m
.If(op
.internal_op
== MicrOp
.OP_CMP
):
1234 comb
+= e
.xer_in
.eq(1<<XERRegs
.SO
) # SO
1235 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
1236 comb
+= e
.xer_out
.eq(1)
1238 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1239 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1240 # *DO NOT* call self.trap here. that would reset absolutely
1241 # everything including destroying read of RA and RB.
1242 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1244 ####################
1245 # ok so the instruction's been decoded, blah blah, however
1246 # now we need to determine if it's actually going to go ahead...
1247 # *or* if in fact it's a privileged operation, whether there's
1248 # an external interrupt, etc. etc. this is a simple priority
1249 # if-elif-elif sequence. decrement takes highest priority,
1250 # EINT next highest, privileged operation third.
1252 # check if instruction is privileged
1253 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1255 # different IRQ conditions
1256 ext_irq_ok
= Signal()
1257 dec_irq_ok
= Signal()
1262 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1263 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1264 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1265 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1267 # LD/ST exceptions. TestIssuer copies the exception info at us
1268 # after a failed LD/ST.
1269 with m
.If(exc
.happened
):
1270 with m
.If(exc
.alignment
):
1271 self
.trap(m
, TT
.PRIV
, 0x600)
1272 with m
.Elif(exc
.instr_fault
):
1273 with m
.If(exc
.segment_fault
):
1274 self
.trap(m
, TT
.PRIV
, 0x480)
1276 # pass exception info to trap to create SRR1
1277 self
.trap(m
, TT
.MEMEXC
, 0x400, exc
)
1279 with m
.If(exc
.segment_fault
):
1280 self
.trap(m
, TT
.PRIV
, 0x380)
1282 self
.trap(m
, TT
.PRIV
, 0x300)
1284 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1285 with m
.Elif(dec_irq_ok
):
1286 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1288 # external interrupt? only if MSR.EE set
1289 with m
.Elif(ext_irq_ok
):
1290 self
.trap(m
, TT
.EINT
, 0x500)
1292 # privileged instruction trap
1293 with m
.Elif(priv_ok
):
1294 self
.trap(m
, TT
.PRIV
, 0x700)
1296 # illegal instruction must redirect to trap. this is done by
1297 # *overwriting* the decoded instruction and starting again.
1298 # (note: the same goes for interrupts and for privileged operations,
1299 # just with different trapaddr and traptype)
1300 with m
.Elif(illeg_ok
):
1301 # illegal instruction trap
1302 self
.trap(m
, TT
.ILLEG
, 0x700)
1304 # no exception, just copy things to the output
1308 ####################
1309 # follow-up after trap/irq to set up SRR0/1
1311 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1312 # Note: OP_SC could actually be modified to just be a trap
1313 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1314 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1315 # TRAP write fast1 = SRR0
1316 comb
+= e_out
.write_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1317 comb
+= e_out
.write_fast1
.ok
.eq(1)
1318 # TRAP write fast2 = SRR1
1319 comb
+= e_out
.write_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1320 comb
+= e_out
.write_fast2
.ok
.eq(1)
1322 # RFID: needs to read SRR0/1
1323 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1324 # TRAP read fast1 = SRR0
1325 comb
+= e_out
.read_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1326 comb
+= e_out
.read_fast1
.ok
.eq(1)
1327 # TRAP read fast2 = SRR1
1328 comb
+= e_out
.read_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1329 comb
+= e_out
.read_fast2
.ok
.eq(1)
1331 # annoying simulator bug
1332 if hasattr(e_out
, "asmcode") and hasattr(self
.dec
.op
, "asmcode"):
1333 comb
+= e_out
.asmcode
.eq(self
.dec
.op
.asmcode
)
1337 def trap(self
, m
, traptype
, trapaddr
, exc
=None):
1338 """trap: this basically "rewrites" the decoded instruction as a trap
1341 op
, e
= self
.dec
.op
, self
.e
1342 comb
+= e
.eq(0) # reset eeeeeverything
1345 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1346 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1347 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1348 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1349 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1350 comb
+= self
.do_copy("ldst_exc", exc
, True) # request type
1351 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # copy of MSR "state"
1352 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1356 def get_rdflags(e
, cu
):
1358 for idx
in range(cu
.n_src
):
1359 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1360 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
1362 print("rdflags", rdl
)
1366 if __name__
== '__main__':
1367 pdecode
= create_pdecode()
1368 dec2
= PowerDecode2(pdecode
)
1369 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1370 with
open("dec2.il", "w") as f
: