1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
6 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
7 from nmigen
.cli
import rtlil
9 from nmutil
.iocontrol
import RecordObject
10 from nmutil
.extend
import exts
12 from soc
.decoder
.power_regspec_map
import regspec_decode
13 from soc
.decoder
.power_decoder
import create_pdecode
14 from soc
.decoder
.power_enums
import (InternalOp
, CryIn
, Function
,
16 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
19 from soc
.regfile
.regfiles
import FastRegs
21 class DecodeA(Elaboratable
):
22 """DecodeA from instruction
24 decodes register RA, whether immediate-zero, implicit and
28 def __init__(self
, dec
):
30 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
31 self
.insn_in
= Signal(32, reset_less
=True)
32 self
.reg_out
= Data(5, name
="reg_a")
33 self
.immz_out
= Signal(reset_less
=True)
34 self
.spr_out
= Data(10, "spr_a")
35 self
.fast_out
= Data(3, "fast_a")
37 def elaborate(self
, platform
):
41 # select Register A field
42 ra
= Signal(5, reset_less
=True)
43 comb
+= ra
.eq(self
.dec
.RA
)
44 with m
.If((self
.sel_in
== In1Sel
.RA
) |
45 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
46 (ra
!= Const(0, 5)))):
47 comb
+= self
.reg_out
.data
.eq(ra
)
48 comb
+= self
.reg_out
.ok
.eq(1)
50 # zero immediate requested
51 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
52 (self
.reg_out
.data
== Const(0, 5))):
53 comb
+= self
.immz_out
.eq(1)
55 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
56 with m
.If(self
.sel_in
== In1Sel
.RS
):
57 comb
+= self
.reg_out
.data
.eq(self
.dec
.RS
)
58 comb
+= self
.reg_out
.ok
.eq(1)
60 # decode Fast-SPR based on instruction type
62 # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
63 with m
.If(op
.internal_op
== InternalOp
.OP_BC
):
64 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
65 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
) # constant: CTR
66 comb
+= self
.fast_out
.ok
.eq(1)
67 with m
.Elif(op
.internal_op
== InternalOp
.OP_BCREG
):
68 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
69 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
70 with m
.If(xo9
& ~xo5
):
71 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
) # constant: CTR
72 comb
+= self
.fast_out
.ok
.eq(1)
74 # MFSPR or MTSPR: move-from / move-to SPRs
75 with m
.If((op
.internal_op
== InternalOp
.OP_MFSPR
) |
76 (op
.internal_op
== InternalOp
.OP_MTSPR
)):
77 # XXX TODO: fast/slow SPR decoding and mapping
78 comb
+= self
.spr_out
.data
.eq(self
.dec
.SPR
) # SPR field, XFX
79 comb
+= self
.spr_out
.ok
.eq(1)
86 def __init__(self
, width
, name
):
87 name_ok
= "%s_ok" % name
88 layout
= ((name
, width
), (name_ok
, 1))
89 Record
.__init
__(self
, layout
)
90 self
.data
= getattr(self
, name
) # convenience
91 self
.ok
= getattr(self
, name_ok
) # convenience
92 self
.data
.reset_less
= True # grrr
93 self
.reset_less
= True # grrr
96 return [self
.data
, self
.ok
]
99 class DecodeB(Elaboratable
):
100 """DecodeB from instruction
102 decodes register RB, different forms of immediate (signed, unsigned),
103 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
104 by industry-standard convention, "lane 2" is where fully-decoded
105 immediates are muxed in.
108 def __init__(self
, dec
):
110 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
111 self
.insn_in
= Signal(32, reset_less
=True)
112 self
.reg_out
= Data(5, "reg_b")
113 self
.imm_out
= Data(64, "imm_b")
114 self
.fast_out
= Data(3, "fast_b")
116 def elaborate(self
, platform
):
120 # select Register B field
121 with m
.Switch(self
.sel_in
):
122 with m
.Case(In2Sel
.RB
):
123 comb
+= self
.reg_out
.data
.eq(self
.dec
.RB
)
124 comb
+= self
.reg_out
.ok
.eq(1)
125 with m
.Case(In2Sel
.RS
):
126 comb
+= self
.reg_out
.data
.eq(self
.dec
.RS
) # for M-Form shiftrot
127 comb
+= self
.reg_out
.ok
.eq(1)
128 with m
.Case(In2Sel
.CONST_UI
):
129 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
130 comb
+= self
.imm_out
.ok
.eq(1)
131 with m
.Case(In2Sel
.CONST_SI
): # TODO: sign-extend here?
132 comb
+= self
.imm_out
.data
.eq(
133 exts(self
.dec
.SI
, 16, 64))
134 comb
+= self
.imm_out
.ok
.eq(1)
135 with m
.Case(In2Sel
.CONST_UI_HI
):
136 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
<<16)
137 comb
+= self
.imm_out
.ok
.eq(1)
138 with m
.Case(In2Sel
.CONST_SI_HI
): # TODO: sign-extend here?
139 comb
+= self
.imm_out
.data
.eq(self
.dec
.SI
<<16)
140 comb
+= self
.imm_out
.data
.eq(
141 exts(self
.dec
.SI
<< 16, 32, 64))
142 comb
+= self
.imm_out
.ok
.eq(1)
143 with m
.Case(In2Sel
.CONST_LI
):
144 comb
+= self
.imm_out
.data
.eq(self
.dec
.LI
<<2)
145 comb
+= self
.imm_out
.ok
.eq(1)
146 with m
.Case(In2Sel
.CONST_BD
):
147 comb
+= self
.imm_out
.data
.eq(self
.dec
.BD
<<2)
148 comb
+= self
.imm_out
.ok
.eq(1)
149 with m
.Case(In2Sel
.CONST_DS
):
150 comb
+= self
.imm_out
.data
.eq(self
.dec
.DS
<<2)
151 comb
+= self
.imm_out
.ok
.eq(1)
152 with m
.Case(In2Sel
.CONST_M1
):
153 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
154 comb
+= self
.imm_out
.ok
.eq(1)
155 with m
.Case(In2Sel
.CONST_SH
):
156 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
157 comb
+= self
.imm_out
.ok
.eq(1)
158 with m
.Case(In2Sel
.CONST_SH32
):
159 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
160 comb
+= self
.imm_out
.ok
.eq(1)
162 # decode SPR2 based on instruction type
164 # BCREG implicitly uses LR or TAR for 2nd reg
165 # CTR however is already in fast_spr1 *not* 2.
166 with m
.If(op
.internal_op
== InternalOp
.OP_BCREG
):
167 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
168 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
170 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
171 comb
+= self
.fast_out
.ok
.eq(1)
173 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
174 comb
+= self
.fast_out
.ok
.eq(1)
179 class DecodeC(Elaboratable
):
180 """DecodeC from instruction
182 decodes register RC. this is "lane 3" into some CompUnits (not many)
185 def __init__(self
, dec
):
187 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
188 self
.insn_in
= Signal(32, reset_less
=True)
189 self
.reg_out
= Data(5, "reg_c")
191 def elaborate(self
, platform
):
195 # select Register C field
196 with m
.Switch(self
.sel_in
):
197 with m
.Case(In3Sel
.RB
):
198 comb
+= self
.reg_out
.data
.eq(self
.dec
.RB
) # for M-Form shiftrot
199 comb
+= self
.reg_out
.ok
.eq(1)
200 with m
.Case(In3Sel
.RS
):
201 comb
+= self
.reg_out
.data
.eq(self
.dec
.RS
)
202 comb
+= self
.reg_out
.ok
.eq(1)
207 class DecodeOut(Elaboratable
):
208 """DecodeOut from instruction
210 decodes output register RA, RT or SPR
213 def __init__(self
, dec
):
215 self
.sel_in
= Signal(OutSel
, reset_less
=True)
216 self
.insn_in
= Signal(32, reset_less
=True)
217 self
.reg_out
= Data(5, "reg_o")
218 self
.spr_out
= Data(10, "spr_o")
219 self
.fast_out
= Data(3, "fast_o")
221 def elaborate(self
, platform
):
225 # select Register out field
226 with m
.Switch(self
.sel_in
):
227 with m
.Case(OutSel
.RT
):
228 comb
+= self
.reg_out
.data
.eq(self
.dec
.RT
)
229 comb
+= self
.reg_out
.ok
.eq(1)
230 with m
.Case(OutSel
.RA
):
231 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
232 comb
+= self
.reg_out
.ok
.eq(1)
233 with m
.Case(OutSel
.SPR
):
234 comb
+= self
.spr_out
.data
.eq(self
.dec
.SPR
) # from XFX
235 comb
+= self
.spr_out
.ok
.eq(1)
237 # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
239 with m
.If((op
.internal_op
== InternalOp
.OP_BC
) |
240 (op
.internal_op
== InternalOp
.OP_BCREG
)):
241 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
242 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
) # constant: CTR
243 comb
+= self
.fast_out
.ok
.eq(1)
245 # RFID 1st spr (fast)
246 with m
.If(op
.internal_op
== InternalOp
.OP_RFID
):
247 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
248 comb
+= self
.fast_out
.ok
.eq(1)
253 class DecodeOut2(Elaboratable
):
254 """DecodeOut2 from instruction
256 decodes output registers
259 def __init__(self
, dec
):
261 self
.sel_in
= Signal(OutSel
, reset_less
=True)
262 self
.lk
= Signal(reset_less
=True)
263 self
.insn_in
= Signal(32, reset_less
=True)
264 self
.reg_out
= Data(5, "reg_o")
265 self
.fast_out
= Data(3, "fast_o")
267 def elaborate(self
, platform
):
271 # update mode LD/ST uses read-reg A also as an output
272 with m
.If(self
.dec
.op
.upd
):
273 comb
+= self
.reg_out
.eq(self
.dec
.RA
)
274 comb
+= self
.reg_out
.ok
.eq(1)
276 # BC or BCREG: potential implicit register (LR) output
278 with m
.If((op
.internal_op
== InternalOp
.OP_BC
) |
279 (op
.internal_op
== InternalOp
.OP_BCREG
)):
280 with m
.If(self
.lk
): # "link" mode
281 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
) # constant: LR
282 comb
+= self
.fast_out
.ok
.eq(1)
284 # RFID 2nd spr (fast)
285 with m
.If(op
.internal_op
== InternalOp
.OP_RFID
):
286 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
287 comb
+= self
.fast_out
.ok
.eq(1)
292 class DecodeRC(Elaboratable
):
293 """DecodeRc from instruction
295 decodes Record bit Rc
297 def __init__(self
, dec
):
299 self
.sel_in
= Signal(RC
, reset_less
=True)
300 self
.insn_in
= Signal(32, reset_less
=True)
301 self
.rc_out
= Data(1, "rc")
303 def elaborate(self
, platform
):
307 # select Record bit out field
308 with m
.Switch(self
.sel_in
):
310 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
311 comb
+= self
.rc_out
.ok
.eq(1)
313 comb
+= self
.rc_out
.data
.eq(1)
314 comb
+= self
.rc_out
.ok
.eq(1)
315 with m
.Case(RC
.NONE
):
316 comb
+= self
.rc_out
.data
.eq(0)
317 comb
+= self
.rc_out
.ok
.eq(1)
322 class DecodeOE(Elaboratable
):
323 """DecodeOE from instruction
325 decodes OE field: uses RC decode detection which might not be good
327 -- For now, use "rc" in the decode table to decide whether oe exists.
328 -- This is not entirely correct architecturally: For mulhd and
329 -- mulhdu, the OE field is reserved. It remains to be seen what an
330 -- actual POWER9 does if we set it on those instructions, for now we
331 -- test that further down when assigning to the multiplier oe input.
333 def __init__(self
, dec
):
335 self
.sel_in
= Signal(RC
, reset_less
=True)
336 self
.insn_in
= Signal(32, reset_less
=True)
337 self
.oe_out
= Data(1, "oe")
339 def elaborate(self
, platform
):
343 # select OE bit out field
344 with m
.Switch(self
.sel_in
):
346 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
347 comb
+= self
.oe_out
.ok
.eq(1)
351 class DecodeCRIn(Elaboratable
):
352 """Decodes input CR from instruction
354 CR indices - insn fields - (not the data *in* the CR) require only 3
355 bits because they refer to CR0-CR7
358 def __init__(self
, dec
):
360 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
361 self
.insn_in
= Signal(32, reset_less
=True)
362 self
.cr_bitfield
= Data(3, "cr_bitfield")
363 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
364 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
365 self
.whole_reg
= Signal(reset_less
=True)
367 def elaborate(self
, platform
):
371 comb
+= self
.cr_bitfield
.ok
.eq(0)
372 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
373 comb
+= self
.whole_reg
.eq(0)
374 with m
.Switch(self
.sel_in
):
375 with m
.Case(CRInSel
.NONE
):
376 pass # No bitfield activated
377 with m
.Case(CRInSel
.CR0
):
378 comb
+= self
.cr_bitfield
.data
.eq(0)
379 comb
+= self
.cr_bitfield
.ok
.eq(1)
380 with m
.Case(CRInSel
.BI
):
381 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
382 comb
+= self
.cr_bitfield
.ok
.eq(1)
383 with m
.Case(CRInSel
.BFA
):
384 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
385 comb
+= self
.cr_bitfield
.ok
.eq(1)
386 with m
.Case(CRInSel
.BA_BB
):
387 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
388 comb
+= self
.cr_bitfield
.ok
.eq(1)
389 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
390 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
391 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
392 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
393 with m
.Case(CRInSel
.BC
):
394 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
395 comb
+= self
.cr_bitfield
.ok
.eq(1)
396 with m
.Case(CRInSel
.WHOLE_REG
):
397 comb
+= self
.whole_reg
.eq(1)
402 class DecodeCROut(Elaboratable
):
403 """Decodes input CR from instruction
405 CR indices - insn fields - (not the data *in* the CR) require only 3
406 bits because they refer to CR0-CR7
409 def __init__(self
, dec
):
411 self
.rc_in
= Signal(reset_less
=True)
412 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
413 self
.insn_in
= Signal(32, reset_less
=True)
414 self
.cr_bitfield
= Data(3, "cr_bitfield")
415 self
.whole_reg
= Signal(reset_less
=True)
417 def elaborate(self
, platform
):
421 comb
+= self
.cr_bitfield
.ok
.eq(0)
422 comb
+= self
.whole_reg
.eq(0)
423 with m
.Switch(self
.sel_in
):
424 with m
.Case(CROutSel
.NONE
):
425 pass # No bitfield activated
426 with m
.Case(CROutSel
.CR0
):
427 comb
+= self
.cr_bitfield
.data
.eq(0)
428 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
429 with m
.Case(CROutSel
.BF
):
430 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
[0:-1])
431 comb
+= self
.cr_bitfield
.ok
.eq(1)
432 with m
.Case(CROutSel
.BT
):
433 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
434 comb
+= self
.cr_bitfield
.ok
.eq(1)
435 with m
.Case(CROutSel
.WHOLE_REG
):
436 comb
+= self
.whole_reg
.eq(1)
443 self
.ca
= Signal(2, reset_less
=True)
444 self
.ov
= Signal(2, reset_less
=True)
445 self
.so
= Signal(reset_less
=True)
448 return [self
.ca
, self
.ov
, self
.so
]
451 class Decode2ToExecute1Type(RecordObject
):
453 def __init__(self
, name
=None):
455 RecordObject
.__init
__(self
, name
=name
)
457 self
.valid
= Signal(reset_less
=True)
458 self
.insn_type
= Signal(InternalOp
, reset_less
=True)
459 self
.fn_unit
= Signal(Function
, reset_less
=True)
460 self
.nia
= Signal(64, reset_less
=True)
461 self
.write_reg
= Data(5, name
="rego")
462 self
.write_ea
= Data(5, name
="ea") # for LD/ST in update mode
463 self
.read_reg1
= Data(5, name
="reg1")
464 self
.read_reg2
= Data(5, name
="reg2")
465 self
.read_reg3
= Data(5, name
="reg3")
466 self
.imm_data
= Data(64, name
="imm")
467 self
.write_spr
= Data(10, name
="spro")
468 self
.read_spr1
= Data(10, name
="spr1")
469 self
.read_spr2
= Data(10, name
="spr2")
471 self
.read_fast1
= Data(3, name
="fast1")
472 self
.read_fast2
= Data(3, name
="fast2")
473 self
.write_fast1
= Data(3, name
="fasto1")
474 self
.write_fast2
= Data(3, name
="fasto2")
476 self
.read_cr1
= Data(3, name
="cr_in1")
477 self
.read_cr2
= Data(3, name
="cr_in2")
478 self
.read_cr3
= Data(3, name
="cr_in2")
479 self
.read_cr_whole
= Signal(reset_less
=True)
480 self
.write_cr
= Data(3, name
="cr_out")
481 self
.write_cr_whole
= Signal(reset_less
=True)
482 self
.lk
= Signal(reset_less
=True)
483 self
.rc
= Data(1, "rc")
484 self
.oe
= Data(1, "oe")
485 self
.invert_a
= Signal(reset_less
=True)
486 self
.zero_a
= Signal(reset_less
=True)
487 self
.invert_out
= Signal(reset_less
=True)
488 self
.input_carry
= Signal(CryIn
, reset_less
=True)
489 self
.output_carry
= Signal(reset_less
=True)
490 self
.input_cr
= Signal(reset_less
=True) # instr. has a CR as input
491 self
.output_cr
= Signal(reset_less
=True) # instr. has a CR as output
492 self
.is_32bit
= Signal(reset_less
=True)
493 self
.is_signed
= Signal(reset_less
=True)
494 self
.insn
= Signal(32, reset_less
=True)
495 self
.data_len
= Signal(4, reset_less
=True) # bytes
496 self
.byte_reverse
= Signal(reset_less
=True)
497 self
.sign_extend
= Signal(reset_less
=True)# do we need this?
498 self
.update
= Signal(reset_less
=True) # LD/ST is "update" variant
501 class PowerDecode2(Elaboratable
):
503 def __init__(self
, dec
):
506 self
.e
= Decode2ToExecute1Type()
509 return self
.dec
.ports() + self
.e
.ports()
511 def elaborate(self
, platform
):
515 # set up submodule decoders
516 m
.submodules
.dec
= self
.dec
517 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
518 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
519 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
520 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
521 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
)
522 m
.submodules
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
523 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
524 m
.submodules
.dec_cr_in
= dec_cr_in
= DecodeCRIn(self
.dec
)
525 m
.submodules
.dec_cr_out
= dec_cr_out
= DecodeCROut(self
.dec
)
527 # copy instruction through...
528 for i
in [self
.e
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
529 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
, dec_rc
.insn_in
,
530 dec_oe
.insn_in
, dec_cr_in
.insn_in
, dec_cr_out
.insn_in
]:
531 comb
+= i
.eq(self
.dec
.opcode_in
)
533 # ...and subdecoders' input fields
534 comb
+= dec_a
.sel_in
.eq(self
.dec
.op
.in1_sel
)
535 comb
+= dec_b
.sel_in
.eq(self
.dec
.op
.in2_sel
)
536 comb
+= dec_c
.sel_in
.eq(self
.dec
.op
.in3_sel
)
537 comb
+= dec_o
.sel_in
.eq(self
.dec
.op
.out_sel
)
538 comb
+= dec_o2
.sel_in
.eq(self
.dec
.op
.out_sel
)
539 comb
+= dec_o2
.lk
.eq(self
.e
.lk
)
540 comb
+= dec_rc
.sel_in
.eq(self
.dec
.op
.rc_sel
)
541 comb
+= dec_oe
.sel_in
.eq(self
.dec
.op
.rc_sel
) # XXX should be OE sel
542 comb
+= dec_cr_in
.sel_in
.eq(self
.dec
.op
.cr_in
)
543 comb
+= dec_cr_out
.sel_in
.eq(self
.dec
.op
.cr_out
)
544 comb
+= dec_cr_out
.rc_in
.eq(dec_rc
.rc_out
.data
)
546 # decode LD/ST length
547 with m
.Switch(self
.dec
.op
.ldst_len
):
548 with m
.Case(LdstLen
.is1B
):
549 comb
+= self
.e
.data_len
.eq(1)
550 with m
.Case(LdstLen
.is2B
):
551 comb
+= self
.e
.data_len
.eq(2)
552 with m
.Case(LdstLen
.is4B
):
553 comb
+= self
.e
.data_len
.eq(4)
554 with m
.Case(LdstLen
.is8B
):
555 comb
+= self
.e
.data_len
.eq(8)
557 comb
+= self
.e
.nia
.eq(0) # XXX TODO
558 fu
= self
.dec
.op
.function_unit
559 itype
= Mux(fu
== Function
.NONE
,
560 InternalOp
.OP_ILLEGAL
,
561 self
.dec
.op
.internal_op
)
562 comb
+= self
.e
.insn_type
.eq(itype
)
563 comb
+= self
.e
.fn_unit
.eq(fu
)
565 # registers a, b, c and out and out2 (LD/ST EA)
566 comb
+= self
.e
.read_reg1
.eq(dec_a
.reg_out
)
567 comb
+= self
.e
.read_reg2
.eq(dec_b
.reg_out
)
568 comb
+= self
.e
.read_reg3
.eq(dec_c
.reg_out
)
569 comb
+= self
.e
.write_reg
.eq(dec_o
.reg_out
)
570 comb
+= self
.e
.write_ea
.eq(dec_o2
.reg_out
)
571 comb
+= self
.e
.imm_data
.eq(dec_b
.imm_out
) # immediate in RB (usually)
572 comb
+= self
.e
.zero_a
.eq(dec_a
.immz_out
) # RA==0 detected
575 comb
+= self
.e
.rc
.eq(dec_rc
.rc_out
)
576 comb
+= self
.e
.oe
.eq(dec_oe
.oe_out
)
579 comb
+= self
.e
.read_spr1
.eq(dec_a
.spr_out
)
580 comb
+= self
.e
.write_spr
.eq(dec_o
.spr_out
)
583 comb
+= self
.e
.read_fast1
.eq(dec_a
.fast_out
)
584 comb
+= self
.e
.read_fast2
.eq(dec_b
.fast_out
)
585 comb
+= self
.e
.write_fast1
.eq(dec_o
.fast_out
)
586 comb
+= self
.e
.write_fast2
.eq(dec_o2
.fast_out
)
588 comb
+= self
.e
.read_cr1
.eq(dec_cr_in
.cr_bitfield
)
589 comb
+= self
.e
.read_cr2
.eq(dec_cr_in
.cr_bitfield_b
)
590 comb
+= self
.e
.read_cr3
.eq(dec_cr_in
.cr_bitfield_o
)
591 comb
+= self
.e
.read_cr_whole
.eq(dec_cr_in
.whole_reg
)
593 comb
+= self
.e
.write_cr
.eq(dec_cr_out
.cr_bitfield
)
594 comb
+= self
.e
.write_cr_whole
.eq(dec_cr_out
.whole_reg
)
596 # decoded/selected instruction flags
597 comb
+= self
.e
.invert_a
.eq(self
.dec
.op
.inv_a
)
598 comb
+= self
.e
.invert_out
.eq(self
.dec
.op
.inv_out
)
599 comb
+= self
.e
.input_carry
.eq(self
.dec
.op
.cry_in
) # carry comes in
600 comb
+= self
.e
.output_carry
.eq(self
.dec
.op
.cry_out
) # carry goes out
601 comb
+= self
.e
.is_32bit
.eq(self
.dec
.op
.is_32b
)
602 comb
+= self
.e
.is_signed
.eq(self
.dec
.op
.sgn
)
603 with m
.If(self
.dec
.op
.lk
):
604 comb
+= self
.e
.lk
.eq(self
.dec
.LK
) # XXX TODO: accessor
606 comb
+= self
.e
.byte_reverse
.eq(self
.dec
.op
.br
)
607 comb
+= self
.e
.sign_extend
.eq(self
.dec
.op
.sgn_ext
)
608 comb
+= self
.e
.update
.eq(self
.dec
.op
.upd
) # LD/ST "update" mode.
611 # These should be removed eventually
612 comb
+= self
.e
.input_cr
.eq(self
.dec
.op
.cr_in
) # condition reg comes in
613 comb
+= self
.e
.output_cr
.eq(self
.dec
.op
.cr_out
) # condition reg goes in
618 def regspecmap(self
, regfile
, regname
):
619 """regspecmap: provides PowerDecode2 with an encoding relationship
620 to Function Unit port regfiles (read-enable, read regnum, write regnum)
621 regfile and regname arguments are fields 1 and 2 from a given regspec.
623 return regspec_decode(self
.e
, regfile
, regname
)
625 def rdflags(self
, cu
):
627 for idx
in range(cu
.n_src
):
628 regfile
, regname
, _
= cu
.get_in_spec(idx
)
629 rdflag
, read
, write
= self
.regspecmap(regfile
, regname
)
631 print ("rdflags", rdl
)
635 if __name__
== '__main__':
636 pdecode
= create_pdecode()
637 dec2
= PowerDecode2(pdecode
)
638 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
639 with
open("dec2.il", "w") as f
: