1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from nmutil
.util
import sel
13 from soc
.regfile
.regfiles
import XERRegs
15 from nmutil
.picker
import PriorityPicker
16 from nmutil
.iocontrol
import RecordObject
17 from nmutil
.extend
import exts
19 from soc
.experiment
.mem_types
import LDSTException
21 from soc
.decoder
.power_regspec_map
import regspec_decode_read
22 from soc
.decoder
.power_regspec_map
import regspec_decode_write
23 from soc
.decoder
.power_decoder
import create_pdecode
24 from soc
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
26 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
27 OutSel
, SPR
, RC
, LDSTMode
,
29 from soc
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
31 from soc
.sv
.svp64
import SVP64Rec
32 from soc
.consts
import (MSR
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
, field
,
33 SPEC_SIZE
, SPECb
, SPEC_AUG_SIZE
, SVP64CROffs
)
35 from soc
.regfile
.regfiles
import FastRegs
36 from soc
.consts
import TT
37 from soc
.config
.state
import CoreState
38 from soc
.regfile
.util
import spr_to_fast
41 def decode_spr_num(spr
):
42 return Cat(spr
[5:10], spr
[0:5])
45 def instr_is_priv(m
, op
, insn
):
46 """determines if the instruction is privileged or not
49 is_priv_insn
= Signal(reset_less
=True)
51 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
52 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
53 comb
+= is_priv_insn
.eq(1)
54 with m
.Case(MicrOp
.OP_TLBIE
) : comb
+= is_priv_insn
.eq(1)
55 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
56 with m
.If(insn
[20]): # field XFX.spr[-1] i think
57 comb
+= is_priv_insn
.eq(1)
61 class SPRMap(Elaboratable
):
62 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
66 self
.spr_i
= Signal(10, reset_less
=True)
67 self
.spr_o
= Data(SPR
, name
="spr_o")
68 self
.fast_o
= Data(3, name
="fast_o")
70 def elaborate(self
, platform
):
72 with m
.Switch(self
.spr_i
):
73 for i
, x
in enumerate(SPR
):
75 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
76 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
77 for x
, v
in spr_to_fast
.items():
79 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
80 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
84 class SVP64ExtraSpec(Elaboratable
):
85 """SVP64ExtraSpec - decodes SVP64 Extra specification.
87 selects the required EXTRA2/3 field.
89 see https://libre-soc.org/openpower/sv/svp64/
92 self
.extra
= Signal(9, reset_less
=True)
93 self
.etype
= Signal(SVEtype
, reset_less
=True) # 2 or 3 bits
94 self
.idx
= Signal(SVEXTRA
, reset_less
=True) # which part of extra
95 self
.spec
= Signal(3) # EXTRA spec for the register
97 def elaborate(self
, platform
):
103 # back in the LDSTRM-* and RM-* files generated by sv_analysis.py
104 # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
105 # which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
106 # the register-extension information. extract those now
107 with m
.Switch(self
.etype
):
108 # 2-bit index selection mode
109 with m
.Case(SVEtype
.EXTRA2
):
110 with m
.Switch(self
.idx
):
111 with m
.Case(SVEXTRA
.Idx0
): # 1st 2 bits [0:1]
112 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX0_VEC
])
113 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX0_MSB
])
114 with m
.Case(SVEXTRA
.Idx1
): # 2nd 2 bits [2:3]
115 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX1_VEC
])
116 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX1_MSB
])
117 with m
.Case(SVEXTRA
.Idx2
): # 3rd 2 bits [4:5]
118 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX2_VEC
])
119 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX2_MSB
])
120 with m
.Case(SVEXTRA
.Idx3
): # 4th 2 bits [6:7]
121 comb
+= spec
[SPEC
.VEC
].eq(extra
[EXTRA2
.IDX3_VEC
])
122 comb
+= spec
[SPEC
.MSB
].eq(extra
[EXTRA2
.IDX3_MSB
])
123 # 3-bit index selection mode
124 with m
.Case(SVEtype
.EXTRA3
):
125 with m
.Switch(self
.idx
):
126 with m
.Case(SVEXTRA
.Idx0
): # 1st 3 bits [0:2]
127 extra3_idx0
= sel(m
, extra
, EXTRA3
.IDX0
)
128 comb
+= spec
.eq(extra3_idx0
)
129 with m
.Case(SVEXTRA
.Idx1
): # 2nd 3 bits [3:5]
130 extra3_idx1
= sel(m
, extra
, EXTRA3
.IDX1
)
131 comb
+= spec
.eq(extra3_idx1
)
132 with m
.Case(SVEXTRA
.Idx2
): # 3rd 3 bits [6:8]
133 extra3_idx2
= sel(m
, extra
, EXTRA3
.IDX2
)
134 comb
+= spec
.eq(extra3_idx2
)
135 # cannot fit more than 9 bits so there is no 4th thing
140 class SVP64RegExtra(SVP64ExtraSpec
):
141 """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
143 incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
144 depending on info in one of the positions in the EXTRA field.
146 designed so that "no change" to the 5-bit register number occurs if
147 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
149 see https://libre-soc.org/openpower/sv/svp64/
152 SVP64ExtraSpec
.__init
__(self
)
153 self
.reg_in
= Signal(5) # incoming reg number (5 bits, RA, RB)
154 self
.reg_out
= Signal(7) # extra-augmented output (7 bits)
155 self
.isvec
= Signal(1) # reg is marked as vector if true
157 def elaborate(self
, platform
):
158 m
= super().elaborate(platform
) # select required EXTRA2/3
161 # first get the spec. if not changed it's "scalar identity behaviour"
162 # which is zero which is ok.
165 # now decode it. bit 0 is "scalar/vector". note that spec could be zero
166 # from above, which (by design) has the effect of "no change", below.
168 # simple: isvec is top bit of spec
169 comb
+= self
.isvec
.eq(spec
[SPEC
.VEC
])
170 # extra bits for register number augmentation
171 spec_aug
= Signal(SPEC_AUG_SIZE
)
172 comb
+= spec_aug
.eq(field(spec
, SPECb
.MSB
, SPECb
.LSB
, SPEC_SIZE
))
174 # decode vector differently from scalar
175 with m
.If(self
.isvec
):
176 # Vector: shifted up, extra in LSBs (RA << 2) | spec[1:2]
177 comb
+= self
.reg_out
.eq(Cat(spec_aug
, self
.reg_in
))
179 # Scalar: not shifted up, extra in MSBs RA | (spec[1:2] << 5)
180 comb
+= self
.reg_out
.eq(Cat(self
.reg_in
, spec_aug
))
185 class SVP64CRExtra(SVP64ExtraSpec
):
186 """SVP64CRExtra - decodes SVP64 Extra fields to determine CR extension
188 incoming 3-bit CR is turned into a 7-bit and marked as scalar/vector
189 depending on info in one of the positions in the EXTRA field.
191 yes, really, 128 CRs. INT is 128, FP is 128, therefore CRs are 128.
193 designed so that "no change" to the 3-bit CR register number occurs if
194 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
196 see https://libre-soc.org/openpower/sv/svp64/appendix
199 SVP64ExtraSpec
.__init
__(self
)
200 self
.cr_in
= Signal(3) # incoming CR number (3 bits, BA[0:2], BFA)
201 self
.cr_out
= Signal(7) # extra-augmented CR output (7 bits)
202 self
.isvec
= Signal(1) # reg is marked as vector if true
204 def elaborate(self
, platform
):
205 m
= super().elaborate(platform
) # select required EXTRA2/3
208 # first get the spec. if not changed it's "scalar identity behaviour"
209 # which is zero which is ok.
212 # now decode it. bit 0 is "scalar/vector". note that spec could be zero
213 # from above, which (by design) has the effect of "no change", below.
215 # simple: isvec is top bit of spec
216 comb
+= self
.isvec
.eq(spec
[SPEC
.VEC
])
217 # extra bits for register number augmentation
218 spec_aug
= Signal(SPEC_AUG_SIZE
)
219 comb
+= spec_aug
.eq(field(spec
, SPECb
.MSB
, SPECb
.LSB
, SPEC_SIZE
))
221 # decode vector differently from scalar, insert bits 1 and 2 accordingly
222 with m
.If(self
.isvec
):
223 # Vector: shifted up, extra in LSBs (CR << 4) | (spec[1:2] << 2)
224 comb
+= self
.cr_out
.eq(Cat(Const(0, 2), spec_aug
, self
.cr_in
))
226 # Scalar: not shifted up, extra in MSBs CR | (spec[1:2] << 3)
227 comb
+= self
.cr_out
.eq(Cat(self
.cr_in
, spec_aug
))
232 class DecodeA(Elaboratable
):
233 """DecodeA from instruction
235 decodes register RA, implicit and explicit CSRs
238 def __init__(self
, dec
):
240 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
241 self
.insn_in
= Signal(32, reset_less
=True)
242 self
.reg_out
= Data(5, name
="reg_a")
243 self
.spr_out
= Data(SPR
, "spr_a")
244 self
.fast_out
= Data(3, "fast_a")
246 def elaborate(self
, platform
):
251 m
.submodules
.sprmap
= sprmap
= SPRMap()
253 # select Register A field
254 ra
= Signal(5, reset_less
=True)
255 comb
+= ra
.eq(self
.dec
.RA
)
256 with m
.If((self
.sel_in
== In1Sel
.RA
) |
257 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
258 (ra
!= Const(0, 5)))):
259 comb
+= reg
.data
.eq(ra
)
262 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
263 # moved it to 1st position (in1_sel)... because
264 rs
= Signal(5, reset_less
=True)
265 comb
+= rs
.eq(self
.dec
.RS
)
266 with m
.If(self
.sel_in
== In1Sel
.RS
):
267 comb
+= reg
.data
.eq(rs
)
270 # decode Fast-SPR based on instruction type
271 with m
.Switch(op
.internal_op
):
273 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
274 with m
.Case(MicrOp
.OP_BC
):
275 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
277 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
278 comb
+= self
.fast_out
.ok
.eq(1)
279 with m
.Case(MicrOp
.OP_BCREG
):
280 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
281 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
282 with m
.If(xo9
& ~xo5
):
284 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
285 comb
+= self
.fast_out
.ok
.eq(1)
287 # MFSPR move from SPRs
288 with m
.Case(MicrOp
.OP_MFSPR
):
289 spr
= Signal(10, reset_less
=True)
290 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
291 comb
+= sprmap
.spr_i
.eq(spr
)
292 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
293 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
298 class DecodeAImm(Elaboratable
):
299 """DecodeA immediate from instruction
301 decodes register RA, whether immediate-zero, implicit and
305 def __init__(self
, dec
):
307 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
308 self
.immz_out
= Signal(reset_less
=True)
310 def elaborate(self
, platform
):
314 # zero immediate requested
315 ra
= Signal(5, reset_less
=True)
316 comb
+= ra
.eq(self
.dec
.RA
)
317 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) & (ra
== Const(0, 5))):
318 comb
+= self
.immz_out
.eq(1)
323 class DecodeB(Elaboratable
):
324 """DecodeB from instruction
326 decodes register RB, different forms of immediate (signed, unsigned),
327 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
328 by industry-standard convention, "lane 2" is where fully-decoded
329 immediates are muxed in.
332 def __init__(self
, dec
):
334 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
335 self
.insn_in
= Signal(32, reset_less
=True)
336 self
.reg_out
= Data(7, "reg_b")
337 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
338 self
.fast_out
= Data(3, "fast_b")
340 def elaborate(self
, platform
):
346 # select Register B field
347 with m
.Switch(self
.sel_in
):
348 with m
.Case(In2Sel
.RB
):
349 comb
+= reg
.data
.eq(self
.dec
.RB
)
351 with m
.Case(In2Sel
.RS
):
352 # for M-Form shiftrot
353 comb
+= reg
.data
.eq(self
.dec
.RS
)
356 # decode SPR2 based on instruction type
357 # BCREG implicitly uses LR or TAR for 2nd reg
358 # CTR however is already in fast_spr1 *not* 2.
359 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
360 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
361 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
363 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
364 comb
+= self
.fast_out
.ok
.eq(1)
366 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
367 comb
+= self
.fast_out
.ok
.eq(1)
372 class DecodeBImm(Elaboratable
):
373 """DecodeB immediate from instruction
375 def __init__(self
, dec
):
377 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
378 self
.imm_out
= Data(64, "imm_b")
380 def elaborate(self
, platform
):
384 # select Register B Immediate
385 with m
.Switch(self
.sel_in
):
386 with m
.Case(In2Sel
.CONST_UI
): # unsigned
387 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
388 comb
+= self
.imm_out
.ok
.eq(1)
389 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
390 si
= Signal(16, reset_less
=True)
391 comb
+= si
.eq(self
.dec
.SI
)
392 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
393 comb
+= self
.imm_out
.ok
.eq(1)
394 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
395 si_hi
= Signal(32, reset_less
=True)
396 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
397 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
398 comb
+= self
.imm_out
.ok
.eq(1)
399 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
400 ui
= Signal(16, reset_less
=True)
401 comb
+= ui
.eq(self
.dec
.UI
)
402 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
403 comb
+= self
.imm_out
.ok
.eq(1)
404 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
405 li
= Signal(26, reset_less
=True)
406 comb
+= li
.eq(self
.dec
.LI
<< 2)
407 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
408 comb
+= self
.imm_out
.ok
.eq(1)
409 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
410 bd
= Signal(16, reset_less
=True)
411 comb
+= bd
.eq(self
.dec
.BD
<< 2)
412 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
413 comb
+= self
.imm_out
.ok
.eq(1)
414 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
415 ds
= Signal(16, reset_less
=True)
416 comb
+= ds
.eq(self
.dec
.DS
<< 2)
417 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
418 comb
+= self
.imm_out
.ok
.eq(1)
419 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
420 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
421 comb
+= self
.imm_out
.ok
.eq(1)
422 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
423 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
424 comb
+= self
.imm_out
.ok
.eq(1)
425 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
426 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
427 comb
+= self
.imm_out
.ok
.eq(1)
432 class DecodeC(Elaboratable
):
433 """DecodeC from instruction
435 decodes register RC. this is "lane 3" into some CompUnits (not many)
438 def __init__(self
, dec
):
440 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
441 self
.insn_in
= Signal(32, reset_less
=True)
442 self
.reg_out
= Data(5, "reg_c")
444 def elaborate(self
, platform
):
450 # select Register C field
451 with m
.Switch(self
.sel_in
):
452 with m
.Case(In3Sel
.RB
):
453 # for M-Form shiftrot
454 comb
+= reg
.data
.eq(self
.dec
.RB
)
456 with m
.Case(In3Sel
.RS
):
457 comb
+= reg
.data
.eq(self
.dec
.RS
)
463 class DecodeOut(Elaboratable
):
464 """DecodeOut from instruction
466 decodes output register RA, RT or SPR
469 def __init__(self
, dec
):
471 self
.sel_in
= Signal(OutSel
, reset_less
=True)
472 self
.insn_in
= Signal(32, reset_less
=True)
473 self
.reg_out
= Data(5, "reg_o")
474 self
.spr_out
= Data(SPR
, "spr_o")
475 self
.fast_out
= Data(3, "fast_o")
477 def elaborate(self
, platform
):
480 m
.submodules
.sprmap
= sprmap
= SPRMap()
484 # select Register out field
485 with m
.Switch(self
.sel_in
):
486 with m
.Case(OutSel
.RT
):
487 comb
+= reg
.data
.eq(self
.dec
.RT
)
489 with m
.Case(OutSel
.RA
):
490 comb
+= reg
.data
.eq(self
.dec
.RA
)
492 with m
.Case(OutSel
.SPR
):
493 spr
= Signal(10, reset_less
=True)
494 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
495 # MFSPR move to SPRs - needs mapping
496 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
497 comb
+= sprmap
.spr_i
.eq(spr
)
498 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
499 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
502 with m
.Switch(op
.internal_op
):
504 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
505 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
506 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
508 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
509 comb
+= self
.fast_out
.ok
.eq(1)
511 # RFID 1st spr (fast)
512 with m
.Case(MicrOp
.OP_RFID
):
513 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
514 comb
+= self
.fast_out
.ok
.eq(1)
519 class DecodeOut2(Elaboratable
):
520 """DecodeOut2 from instruction
522 decodes output registers (2nd one). note that RA is *implicit* below,
523 which now causes problems with SVP64
525 TODO: SVP64 is a little more complex, here. svp64 allows extending
526 by one more destination by having one more EXTRA field. RA-as-src
527 is not the same as RA-as-dest. limited in that it's the same first
528 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
529 for operations that have src-as-dest: mostly this is LD/ST-with-update
530 but there are others.
533 def __init__(self
, dec
):
535 self
.sel_in
= Signal(OutSel
, reset_less
=True)
536 self
.lk
= Signal(reset_less
=True)
537 self
.insn_in
= Signal(32, reset_less
=True)
538 self
.reg_out
= Data(5, "reg_o2")
539 self
.fast_out
= Data(3, "fast_o2")
541 def elaborate(self
, platform
):
545 #m.submodules.svdec = svdec = SVP64RegExtra()
547 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
548 #reg = Signal(5, reset_less=True)
550 if hasattr(self
.dec
.op
, "upd"):
551 # update mode LD/ST uses read-reg A also as an output
552 with m
.If(self
.dec
.op
.upd
== LDSTMode
.update
):
553 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
554 comb
+= self
.reg_out
.ok
.eq(1)
556 # B, BC or BCREG: potential implicit register (LR) output
557 # these give bl, bcl, bclrl, etc.
558 with m
.Switch(op
.internal_op
):
560 # BC* implicit register (LR)
561 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
562 with m
.If(self
.lk
): # "link" mode
563 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
) # constant: LR
564 comb
+= self
.fast_out
.ok
.eq(1)
566 # RFID 2nd spr (fast)
567 with m
.Case(MicrOp
.OP_RFID
):
568 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
569 comb
+= self
.fast_out
.ok
.eq(1)
574 class DecodeRC(Elaboratable
):
575 """DecodeRc from instruction
577 decodes Record bit Rc
580 def __init__(self
, dec
):
582 self
.sel_in
= Signal(RC
, reset_less
=True)
583 self
.insn_in
= Signal(32, reset_less
=True)
584 self
.rc_out
= Data(1, "rc")
586 def elaborate(self
, platform
):
590 # select Record bit out field
591 with m
.Switch(self
.sel_in
):
593 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
594 comb
+= self
.rc_out
.ok
.eq(1)
596 comb
+= self
.rc_out
.data
.eq(1)
597 comb
+= self
.rc_out
.ok
.eq(1)
598 with m
.Case(RC
.NONE
):
599 comb
+= self
.rc_out
.data
.eq(0)
600 comb
+= self
.rc_out
.ok
.eq(1)
605 class DecodeOE(Elaboratable
):
606 """DecodeOE from instruction
608 decodes OE field: uses RC decode detection which might not be good
610 -- For now, use "rc" in the decode table to decide whether oe exists.
611 -- This is not entirely correct architecturally: For mulhd and
612 -- mulhdu, the OE field is reserved. It remains to be seen what an
613 -- actual POWER9 does if we set it on those instructions, for now we
614 -- test that further down when assigning to the multiplier oe input.
617 def __init__(self
, dec
):
619 self
.sel_in
= Signal(RC
, reset_less
=True)
620 self
.insn_in
= Signal(32, reset_less
=True)
621 self
.oe_out
= Data(1, "oe")
623 def elaborate(self
, platform
):
628 with m
.Switch(op
.internal_op
):
630 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
632 # XXX ARGH! ignoring OE causes incompatibility with microwatt
633 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
634 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
635 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
636 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
637 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
638 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
642 # all other ops decode OE field
644 # select OE bit out field
645 with m
.Switch(self
.sel_in
):
647 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
648 comb
+= self
.oe_out
.ok
.eq(1)
653 class DecodeCRIn(Elaboratable
):
654 """Decodes input CR from instruction
656 CR indices - insn fields - (not the data *in* the CR) require only 3
657 bits because they refer to CR0-CR7
660 def __init__(self
, dec
):
662 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
663 self
.insn_in
= Signal(32, reset_less
=True)
664 self
.cr_bitfield
= Data(3, "cr_bitfield")
665 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
666 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
667 self
.whole_reg
= Data(8, "cr_fxm")
668 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
670 def elaborate(self
, platform
):
674 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
677 # zero-initialisation
678 comb
+= self
.cr_bitfield
.ok
.eq(0)
679 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
680 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
681 comb
+= self
.whole_reg
.ok
.eq(0)
682 comb
+= self
.sv_override
.eq(0)
684 # select the relevant CR bitfields
685 with m
.Switch(self
.sel_in
):
686 with m
.Case(CRInSel
.NONE
):
687 pass # No bitfield activated
688 with m
.Case(CRInSel
.CR0
):
689 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
690 comb
+= self
.cr_bitfield
.ok
.eq(1)
691 comb
+= self
.sv_override
.eq(1)
692 with m
.Case(CRInSel
.CR1
):
693 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
694 comb
+= self
.cr_bitfield
.ok
.eq(1)
695 comb
+= self
.sv_override
.eq(2)
696 with m
.Case(CRInSel
.BI
):
697 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
698 comb
+= self
.cr_bitfield
.ok
.eq(1)
699 with m
.Case(CRInSel
.BFA
):
700 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
701 comb
+= self
.cr_bitfield
.ok
.eq(1)
702 with m
.Case(CRInSel
.BA_BB
):
703 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
704 comb
+= self
.cr_bitfield
.ok
.eq(1)
705 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
706 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
707 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
708 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
709 with m
.Case(CRInSel
.BC
):
710 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
711 comb
+= self
.cr_bitfield
.ok
.eq(1)
712 with m
.Case(CRInSel
.WHOLE_REG
):
713 comb
+= self
.whole_reg
.ok
.eq(1)
714 move_one
= Signal(reset_less
=True)
715 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
716 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
717 # must one-hot the FXM field
718 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
719 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
721 # otherwise use all of it
722 comb
+= self
.whole_reg
.data
.eq(0xff)
727 class DecodeCROut(Elaboratable
):
728 """Decodes input CR from instruction
730 CR indices - insn fields - (not the data *in* the CR) require only 3
731 bits because they refer to CR0-CR7
734 def __init__(self
, dec
):
736 self
.rc_in
= Signal(reset_less
=True)
737 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
738 self
.insn_in
= Signal(32, reset_less
=True)
739 self
.cr_bitfield
= Data(3, "cr_bitfield")
740 self
.whole_reg
= Data(8, "cr_fxm")
741 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
743 def elaborate(self
, platform
):
747 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
750 comb
+= self
.cr_bitfield
.ok
.eq(0)
751 comb
+= self
.whole_reg
.ok
.eq(0)
752 comb
+= self
.sv_override
.eq(0)
754 with m
.Switch(self
.sel_in
):
755 with m
.Case(CROutSel
.NONE
):
756 pass # No bitfield activated
757 with m
.Case(CROutSel
.CR0
):
758 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
759 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
760 comb
+= self
.sv_override
.eq(1)
761 with m
.Case(CROutSel
.CR1
):
762 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
763 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
764 comb
+= self
.sv_override
.eq(2)
765 with m
.Case(CROutSel
.BF
):
766 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
767 comb
+= self
.cr_bitfield
.ok
.eq(1)
768 with m
.Case(CROutSel
.BT
):
769 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
770 comb
+= self
.cr_bitfield
.ok
.eq(1)
771 with m
.Case(CROutSel
.WHOLE_REG
):
772 comb
+= self
.whole_reg
.ok
.eq(1)
773 move_one
= Signal(reset_less
=True)
774 comb
+= move_one
.eq(self
.insn_in
[20])
775 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
777 # must one-hot the FXM field
778 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
779 with m
.If(ppick
.en_o
):
780 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
782 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
784 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
786 # otherwise use all of it
787 comb
+= self
.whole_reg
.data
.eq(0xff)
791 # dictionary of Input Record field names that, if they exist,
792 # will need a corresponding CSV Decoder file column (actually, PowerOp)
793 # to be decoded (this includes the single bit names)
794 record_names
= {'insn_type': 'internal_op',
795 'fn_unit': 'function_unit',
799 'imm_data': 'in2_sel',
800 'invert_in': 'inv_a',
801 'invert_out': 'inv_out',
804 'output_carry': 'cry_out',
805 'input_carry': 'cry_in',
806 'is_32bit': 'is_32b',
809 'data_len': 'ldst_len',
810 'byte_reverse': 'br',
811 'sign_extend': 'sgn_ext',
816 class PowerDecodeSubset(Elaboratable
):
817 """PowerDecodeSubset: dynamic subset decoder
819 only fields actually requested are copied over. hence, "subset" (duh).
821 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
823 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
826 self
.fn_name
= fn_name
828 opkls
= Decode2ToOperand
829 self
.do
= opkls(fn_name
)
830 col_subset
= self
.get_col_subset(self
.do
)
832 # only needed for "main" PowerDecode2
834 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
)
836 # create decoder if one not already given
838 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
839 row_subset
=self
.rowsubsetfn
)
842 # state information needed by the Decoder
844 state
= CoreState("dec2")
847 def get_col_subset(self
, do
):
848 subset
= { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
849 for k
, v
in record_names
.items():
852 print ("get_col_subset", self
.fn_name
, do
.fields
, subset
)
855 def rowsubsetfn(self
, opcode
, row
):
856 return row
['unit'] == self
.fn_name
859 return self
.dec
.ports() + self
.e
.ports() + self
.sv_rm
.ports()
861 def needs_field(self
, field
, op_field
):
866 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
868 def do_copy(self
, field
, val
, final
=False):
869 if final
or self
.final
:
873 if hasattr(do
, field
) and val
is not None:
874 return getattr(do
, field
).eq(val
)
877 def op_get(self
, op_field
):
878 return getattr(self
.dec
.op
, op_field
, None)
880 def elaborate(self
, platform
):
884 op
, do
= self
.dec
.op
, self
.do
885 msr
, cia
= state
.msr
, state
.pc
886 # fill in for a normal instruction (not an exception)
887 # copy over if non-exception, non-privileged etc. is detected
889 if self
.fn_name
is None:
892 name
= self
.fn_name
+ "tmp"
893 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
)
895 # set up submodule decoders
896 m
.submodules
.dec
= self
.dec
897 m
.submodules
.dec_rc
= self
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
898 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
900 # copy instruction through...
901 for i
in [do
.insn
, dec_rc
.insn_in
, dec_oe
.insn_in
, ]:
902 comb
+= i
.eq(self
.dec
.opcode_in
)
904 # ...and subdecoders' input fields
905 comb
+= dec_rc
.sel_in
.eq(op
.rc_sel
)
906 comb
+= dec_oe
.sel_in
.eq(op
.rc_sel
) # XXX should be OE sel
909 comb
+= self
.do_copy("msr", msr
)
910 comb
+= self
.do_copy("cia", cia
)
912 # set up instruction type
913 # no op: defaults to OP_ILLEGAL
914 if self
.fn_name
=="MMU":
915 # mmu is special case: needs SPR opcode as well
916 mmu0
= self
.mmu0_spr_dec
917 with m
.If(((mmu0
.dec
.op
.internal_op
== MicrOp
.OP_MTSPR
) |
918 (mmu0
.dec
.op
.internal_op
== MicrOp
.OP_MFSPR
))):
919 comb
+= self
.do_copy("insn_type", mmu0
.op_get("internal_op"))
921 comb
+= self
.do_copy("insn_type", self
.op_get("internal_op"))
923 comb
+= self
.do_copy("insn_type", self
.op_get("internal_op"))
925 # function unit for decoded instruction: requires minor redirect
927 fn
= self
.op_get("function_unit")
928 spr
= Signal(10, reset_less
=True)
929 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
931 # XXX BUG - don't use hardcoded magic constants.
932 # also use ".value" otherwise the test fails. bit of a pain
933 # https://bugs.libre-soc.org/show_bug.cgi?id=603
935 SPR_PID
= 48 # TODO read docs for POWER9
936 # Microwatt doesn't implement the partition table
937 # instead has PRTBL register (SPR) to point to process table
938 SPR_PRTBL
= 720 # see common.vhdl in microwatt, not in POWER9
939 with m
.If(((self
.dec
.op
.internal_op
== MicrOp
.OP_MTSPR
) |
940 (self
.dec
.op
.internal_op
== MicrOp
.OP_MFSPR
)) &
941 ((spr
== SPR
.DSISR
) |
(spr
== SPR
.DAR
)
942 |
(spr
==SPR_PRTBL
) |
(spr
==SPR_PID
))):
943 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
945 comb
+= self
.do_copy("fn_unit",fn
)
948 if self
.needs_field("zero_a", "in1_sel"):
949 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
950 comb
+= dec_ai
.sel_in
.eq(op
.in1_sel
)
951 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
952 if self
.needs_field("imm_data", "in2_sel"):
953 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
954 comb
+= dec_bi
.sel_in
.eq(op
.in2_sel
)
955 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
958 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
959 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
962 rc_out
= self
.dec_rc
.rc_out
.data
963 with m
.Switch(op
.cr_out
):
964 with m
.Case(CROutSel
.CR0
, CROutSel
.CR1
):
965 comb
+= self
.do_copy("write_cr0", rc_out
) # only when RC=1
966 with m
.Case(CROutSel
.BF
, CROutSel
.BT
):
967 comb
+= self
.do_copy("write_cr0", 1)
969 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
970 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
972 # decoded/selected instruction flags
973 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
974 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
975 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
976 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
977 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
978 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
979 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
980 lk
= self
.op_get("lk")
983 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
985 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
986 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
987 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
992 class PowerDecode2(PowerDecodeSubset
):
993 """PowerDecode2: the main instruction decoder.
995 whilst PowerDecode is responsible for decoding the actual opcode, this
996 module encapsulates further specialist, sparse information and
997 expansion of fields that is inconvenient to have in the CSV files.
998 for example: the encoding of the immediates, which are detected
999 and expanded out to their full value from an annotated (enum)
1002 implicit register usage is also set up, here. for example: OP_BC
1003 requires implicitly reading CTR, OP_RFID requires implicitly writing
1006 in addition, PowerDecoder2 is responsible for detecting whether
1007 instructions are illegal (or privileged) or not, and instead of
1008 just leaving at that, *replacing* the instruction to execute with
1009 a suitable alternative (trap).
1011 LDSTExceptions are done the cycle _after_ they're detected (after
1012 they come out of LDSTCompUnit). basically despite the instruction
1013 being decoded, the results of the decode are completely ignored
1014 and "exception.happened" used to set the "actual" instruction to
1015 "OP_TRAP". the LDSTException data structure gets filled in,
1016 in the CompTrapOpSubset and that's what it fills in SRR.
1018 to make this work, TestIssuer must notice "exception.happened"
1019 after the (failed) LD/ST and copies the LDSTException info from
1020 the output, into here (PowerDecoder2). without incrementing PC.
1023 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
1024 super().__init
__(dec
, opkls
, fn_name
, final
, state
)
1025 self
.exc
= LDSTException("dec2_exc")
1027 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
1028 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
1029 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1030 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1031 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1032 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1033 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1034 self
.o_isvec
= Signal(1, name
="reg_o_isvec")
1035 self
.o2_isvec
= Signal(1, name
="reg_o2_isvec")
1036 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs are vectors
1038 def get_col_subset(self
, opkls
):
1039 subset
= super().get_col_subset(opkls
)
1040 subset
.add("asmcode")
1041 subset
.add("in1_sel")
1042 subset
.add("in2_sel")
1043 subset
.add("in3_sel")
1044 subset
.add("out_sel")
1045 subset
.add("sv_in1")
1046 subset
.add("sv_in2")
1047 subset
.add("sv_in3")
1048 subset
.add("sv_out")
1049 subset
.add("sv_cr_in")
1050 subset
.add("sv_cr_out")
1051 subset
.add("SV_Etype")
1052 subset
.add("SV_Ptype")
1054 subset
.add("internal_op")
1058 def elaborate(self
, platform
):
1059 m
= super().elaborate(platform
)
1062 e_out
, op
, do_out
= self
.e
, self
.dec
.op
, self
.e
.do
1063 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1064 rc_out
= self
.dec_rc
.rc_out
.data
1068 # fill in for a normal instruction (not an exception)
1069 # copy over if non-exception, non-privileged etc. is detected
1071 # set up submodule decoders
1072 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
1073 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
1074 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
1075 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
1076 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
)
1077 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
)
1078 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
)
1080 # and SVP64 Extra decoders
1081 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1082 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1083 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1084 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1085 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1086 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1087 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1088 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1089 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1091 # debug access to crout_svdec (used in get_pdecode_cr_out)
1092 self
.crout_svdec
= crout_svdec
1094 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1095 reg
= Signal(5, reset_less
=True)
1097 # copy instruction through...
1098 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1099 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
,
1100 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1101 comb
+= i
.eq(self
.dec
.opcode_in
)
1104 comb
+= self
.dec_cr_in
.sel_in
.eq(op
.cr_in
)
1105 comb
+= self
.dec_cr_out
.sel_in
.eq(op
.cr_out
)
1106 comb
+= self
.dec_cr_out
.rc_in
.eq(rc_out
)
1109 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1110 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1112 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1113 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1114 # which in turn were auto-generated by sv_analysis.py
1115 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1119 comb
+= crout_svdec
.idx
.eq(op
.sv_cr_out
) # SVP64 CR out
1120 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1123 # CR in - index selection slightly different due to shared CR field sigh
1124 cr_a_idx
= Signal(SVEXTRA
)
1125 cr_b_idx
= Signal(SVEXTRA
)
1127 # these change slightly, when decoding BA/BB. really should have
1128 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1129 comb
+= cr_a_idx
.eq(op
.sv_cr_in
)
1130 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1131 with m
.If(op
.sv_cr_in
== SVEXTRA
.Idx_1_2
.value
):
1132 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1133 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1135 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1136 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1137 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1139 # indices are slightly different, BA/BB mess sorted above
1140 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1141 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1142 comb
+= crin_svdec_o
.idx
.eq(op
.sv_cr_out
) # SVP64 CR out
1144 # ...and subdecoders' input fields
1145 comb
+= dec_a
.sel_in
.eq(op
.in1_sel
)
1146 comb
+= dec_b
.sel_in
.eq(op
.in2_sel
)
1147 comb
+= dec_c
.sel_in
.eq(op
.in3_sel
)
1148 comb
+= dec_o
.sel_in
.eq(op
.out_sel
)
1149 comb
+= dec_o2
.sel_in
.eq(op
.out_sel
)
1150 if hasattr(do
, "lk"):
1151 comb
+= dec_o2
.lk
.eq(do
.lk
)
1153 # get SVSTATE srcstep (TODO: elwidth, dststep etc.) needed below
1154 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1155 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1157 # registers a, b, c and out and out2 (LD/ST EA)
1158 for to_reg
, fromreg
, svdec
in (
1159 (e
.read_reg1
, dec_a
.reg_out
, in1_svdec
),
1160 (e
.read_reg2
, dec_b
.reg_out
, in2_svdec
),
1161 (e
.read_reg3
, dec_c
.reg_out
, in3_svdec
),
1162 (e
.write_reg
, dec_o
.reg_out
, o_svdec
),
1163 (e
.write_ea
, dec_o2
.reg_out
, o2_svdec
)):
1164 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1165 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
1166 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1167 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1168 # detect if Vectorised: add srcstep if yes. TODO: a LOT.
1169 # this trick only holds when elwidth=default and in single-pred
1170 with m
.If(svdec
.isvec
):
1171 comb
+= to_reg
.data
.eq(srcstep
+svdec
.reg_out
) # 7-bit output
1173 comb
+= to_reg
.data
.eq(svdec
.reg_out
) # 7-bit output
1175 comb
+= in1_svdec
.idx
.eq(op
.sv_in1
) # SVP64 reg #1 (matches in1_sel)
1176 comb
+= in2_svdec
.idx
.eq(op
.sv_in2
) # SVP64 reg #2 (matches in2_sel)
1177 comb
+= in3_svdec
.idx
.eq(op
.sv_in3
) # SVP64 reg #3 (matches in3_sel)
1178 comb
+= o_svdec
.idx
.eq(op
.sv_out
) # SVP64 output (matches out_sel)
1179 # XXX TODO - work out where this should come from. the problem is
1180 # that LD-with-update is implied (computed from "is instruction in
1181 # "update mode" rather than specified cleanly as its own CSV column
1182 #comb += o2_svdec.idx.eq(op.sv_out) # SVP64 output (implicit)
1184 # output reg-is-vectorised (and when no output is vectorised)
1185 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1186 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1187 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1188 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1189 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1190 # TODO: include SPRs and CRs here! must be True when *all* are scalar
1191 comb
+= self
.no_out_vec
.eq((~o2_svdec
.isvec
) & (~o_svdec
.isvec
) &
1192 (~crout_svdec
.isvec
))
1195 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1196 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1199 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1200 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1201 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
)
1202 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
)
1204 # condition registers (CR)
1205 for to_reg
, cr
, name
, svdec
in (
1206 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", crin_svdec
),
1207 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", crin_svdec_b
),
1208 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", crin_svdec_o
),
1209 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", crout_svdec
)):
1210 fromreg
= getattr(cr
, name
)
1211 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1212 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
1213 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1214 with m
.If(svdec
.isvec
):
1215 # check if this is CR0 or CR1: treated differently
1216 # (does not "listen" to EXTRA2/3 spec for a start)
1217 # also: the CRs start from completely different locations
1218 with m
.If(cr
.sv_override
== 1): # CR0
1219 offs
= SVP64CROffs
.CR0
1220 comb
+= to_reg
.data
.eq(srcstep
+offs
)
1221 with m
.Elif(cr
.sv_override
== 2): # CR1
1222 offs
= SVP64CROffs
.CR1
1223 comb
+= to_reg
.data
.eq(srcstep
+1)
1225 comb
+= to_reg
.data
.eq(srcstep
+svdec
.cr_out
) # 7-bit output
1227 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1228 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1230 # sigh this is exactly the sort of thing for which the
1231 # decoder is designed to not need. MTSPR, MFSPR and others need
1232 # access to the XER bits. however setting e.oe is not appropriate
1233 with m
.If(op
.internal_op
== MicrOp
.OP_MFSPR
):
1234 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1235 with m
.If(op
.internal_op
== MicrOp
.OP_CMP
):
1236 comb
+= e
.xer_in
.eq(1<<XERRegs
.SO
) # SO
1237 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
1238 comb
+= e
.xer_out
.eq(1)
1240 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1241 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1242 # *DO NOT* call self.trap here. that would reset absolutely
1243 # everything including destroying read of RA and RB.
1244 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1246 ####################
1247 # ok so the instruction's been decoded, blah blah, however
1248 # now we need to determine if it's actually going to go ahead...
1249 # *or* if in fact it's a privileged operation, whether there's
1250 # an external interrupt, etc. etc. this is a simple priority
1251 # if-elif-elif sequence. decrement takes highest priority,
1252 # EINT next highest, privileged operation third.
1254 # check if instruction is privileged
1255 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1257 # different IRQ conditions
1258 ext_irq_ok
= Signal()
1259 dec_irq_ok
= Signal()
1264 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1265 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1266 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1267 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1269 # LD/ST exceptions. TestIssuer copies the exception info at us
1270 # after a failed LD/ST.
1271 with m
.If(exc
.happened
):
1272 with m
.If(exc
.alignment
):
1273 self
.trap(m
, TT
.PRIV
, 0x600)
1274 with m
.Elif(exc
.instr_fault
):
1275 with m
.If(exc
.segment_fault
):
1276 self
.trap(m
, TT
.PRIV
, 0x480)
1278 # pass exception info to trap to create SRR1
1279 self
.trap(m
, TT
.MEMEXC
, 0x400, exc
)
1281 with m
.If(exc
.segment_fault
):
1282 self
.trap(m
, TT
.PRIV
, 0x380)
1284 self
.trap(m
, TT
.PRIV
, 0x300)
1286 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1287 with m
.Elif(dec_irq_ok
):
1288 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1290 # external interrupt? only if MSR.EE set
1291 with m
.Elif(ext_irq_ok
):
1292 self
.trap(m
, TT
.EINT
, 0x500)
1294 # privileged instruction trap
1295 with m
.Elif(priv_ok
):
1296 self
.trap(m
, TT
.PRIV
, 0x700)
1298 # illegal instruction must redirect to trap. this is done by
1299 # *overwriting* the decoded instruction and starting again.
1300 # (note: the same goes for interrupts and for privileged operations,
1301 # just with different trapaddr and traptype)
1302 with m
.Elif(illeg_ok
):
1303 # illegal instruction trap
1304 self
.trap(m
, TT
.ILLEG
, 0x700)
1306 # no exception, just copy things to the output
1310 ####################
1311 # follow-up after trap/irq to set up SRR0/1
1313 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1314 # Note: OP_SC could actually be modified to just be a trap
1315 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1316 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1317 # TRAP write fast1 = SRR0
1318 comb
+= e_out
.write_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1319 comb
+= e_out
.write_fast1
.ok
.eq(1)
1320 # TRAP write fast2 = SRR1
1321 comb
+= e_out
.write_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1322 comb
+= e_out
.write_fast2
.ok
.eq(1)
1324 # RFID: needs to read SRR0/1
1325 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1326 # TRAP read fast1 = SRR0
1327 comb
+= e_out
.read_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1328 comb
+= e_out
.read_fast1
.ok
.eq(1)
1329 # TRAP read fast2 = SRR1
1330 comb
+= e_out
.read_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1331 comb
+= e_out
.read_fast2
.ok
.eq(1)
1333 # annoying simulator bug
1334 if hasattr(e_out
, "asmcode") and hasattr(self
.dec
.op
, "asmcode"):
1335 comb
+= e_out
.asmcode
.eq(self
.dec
.op
.asmcode
)
1339 def trap(self
, m
, traptype
, trapaddr
, exc
=None):
1340 """trap: this basically "rewrites" the decoded instruction as a trap
1343 op
, e
= self
.dec
.op
, self
.e
1344 comb
+= e
.eq(0) # reset eeeeeverything
1347 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1348 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1349 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1350 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1351 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1352 comb
+= self
.do_copy("ldst_exc", exc
, True) # request type
1353 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # copy of MSR "state"
1354 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1357 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
1358 # identifies if an instruction is a SVP64-encoded prefix, and extracts
1359 # the 24-bit SVP64 context (RM) if it is
1360 class SVP64PrefixDecoder(Elaboratable
):
1363 self
.opcode_in
= Signal(32, reset_less
=True)
1364 self
.raw_opcode_in
= Signal
.like(self
.opcode_in
, reset_less
=True)
1365 self
.is_svp64_mode
= Signal(1, reset_less
=True)
1366 self
.svp64_rm
= Signal(24, reset_less
=True)
1367 self
.bigendian
= Signal(reset_less
=True)
1369 def elaborate(self
, platform
):
1371 opcode_in
= self
.opcode_in
1373 # sigh copied this from TopPowerDecoder
1374 # raw opcode in assumed to be in LE order: byte-reverse it to get BE
1375 raw_le
= self
.raw_opcode_in
1377 for i
in range(0, 32, 8):
1378 l
.append(raw_le
[i
:i
+8])
1381 comb
+= opcode_in
.eq(Mux(self
.bigendian
, raw_be
, raw_le
))
1383 # start identifying if the incoming opcode is SVP64 prefix)
1384 major
= sel(m
, opcode_in
, SVP64P
.OPC
)
1385 ident
= sel(m
, opcode_in
, SVP64P
.SVP64_7_9
)
1387 comb
+= self
.is_svp64_mode
.eq(
1388 (major
== Const(1, 6)) & # EXT01
1389 (ident
== Const(0b11, 2)) # identifier bits
1392 with m
.If(self
.is_svp64_mode
):
1393 # now grab the 24-bit ReMap context bits,
1394 rm
= sel(m
, opcode_in
, SVP64P
.RM
)
1395 comb
+= self
.svp64_rm
.eq(rm
)
1400 return [self
.opcode_in
, self
.raw_opcode_in
, self
.is_svp64_mode
,
1401 self
.svp64_rm
, self
.bigendian
]
1403 def get_rdflags(e
, cu
):
1405 for idx
in range(cu
.n_src
):
1406 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1407 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
1409 print("rdflags", rdl
)
1413 if __name__
== '__main__':
1414 svp64
= SVP64PowerDecoder()
1415 vl
= rtlil
.convert(svp64
, ports
=svp64
.ports())
1416 with
open("svp64_dec.il", "w") as f
:
1418 pdecode
= create_pdecode()
1419 dec2
= PowerDecode2(pdecode
)
1420 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1421 with
open("dec2.il", "w") as f
: