src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl
   7 from nmigen.cli import rtlil
   8
   9 from soc.decoder.power_decoder import create_pdecode
  10 from soc.decoder.power_enums import (InternalOp, CryIn, Function,
  11                                      LdstLen, In1Sel, In2Sel, In3Sel,
  12                                      OutSel, SPR, RC)
  13
  14
  15 class DecodeA(Elaboratable):
  16     """DecodeA from instruction
  17
  18     decodes register RA, whether immediate-zero, implicit and
  19     explicit CSRs
  20     """
  21
  22     def __init__(self, dec):
  23         self.dec = dec
  24         self.sel_in = Signal(In1Sel, reset_less=True)
  25         self.insn_in = Signal(32, reset_less=True)
  26         self.reg_out = Data(5, name="reg_a")
  27         self.immz_out = Signal(reset_less=True)
  28         self.spr_out = Data(10, "spr_a")
  29
  30     def elaborate(self, platform):
  31         m = Module()
  32         comb = m.d.comb
  33
  34         # select Register A field
  35         ra = Signal(5, reset_less=True)
  36         comb += ra.eq(self.dec.RA)
  37         with m.If((self.sel_in == In1Sel.RA) |
  38                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  39                    (ra != Const(0, 5)))):
  40             comb += self.reg_out.data.eq(ra)
  41             comb += self.reg_out.ok.eq(1)
  42
  43         # zero immediate requested
  44         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
  45                   (self.reg_out.data == Const(0, 5))):
  46             comb += self.immz_out.eq(1)
  47
  48         # decode SPR1 based on instruction type
  49         op = self.dec.op
  50         # BC or BCREG: potential implicit register (CTR)
  51         with m.If((op.internal_op == InternalOp.OP_BC) |
  52                   (op.internal_op == InternalOp.OP_BCREG)):
  53             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
  54                 comb += self.spr_out.data.eq(SPR.CTR) # constant: CTR
  55                 comb += self.spr_out.ok.eq(1)
  56         # MFSPR or MTSPR: move-from / move-to SPRs
  57         with m.If((op.internal_op == InternalOp.OP_MFSPR) |
  58                   (op.internal_op == InternalOp.OP_MTSPR)):
  59             comb += self.spr_out.data.eq(self.dec.SPR) # SPR field, XFX
  60             comb += self.spr_out.ok.eq(1)
  61
  62         return m
  63
  64 class Data:
  65
  66     def __init__(self, width, name):
  67
  68         self.data = Signal(width, name=name, reset_less=True)
  69         self.ok = Signal(name="%s_ok" % name, reset_less=True)
  70
  71     def eq(self, rhs):
  72         return [self.data.eq(rhs.data),
  73                 self.ok.eq(rhs.ok)]
  74
  75     def ports(self):
  76         return [self.data, self.ok]
  77
  78
  79 class DecodeB(Elaboratable):
  80     """DecodeB from instruction
  81
  82     decodes register RB, different forms of immediate (signed, unsigned),
  83     and implicit SPRs
  84     """
  85
  86     def __init__(self, dec):
  87         self.dec = dec
  88         self.sel_in = Signal(In2Sel, reset_less=True)
  89         self.insn_in = Signal(32, reset_less=True)
  90         self.reg_out = Data(5, "reg_b")
  91         self.imm_out = Data(64, "imm_b")
  92         self.spr_out = Data(10, "spr_b")
  93
  94     def exts(self, exts_data, width, fullwidth):
  95         exts_data = exts_data[0:width]
  96         topbit = exts_data[-1]
  97         signbits = Repl(topbit, fullwidth-width)
  98         return Cat(exts_data, signbits)
  99
 100
 101     def elaborate(self, platform):
 102         m = Module()
 103         comb = m.d.comb
 104
 105         # select Register B field
 106         with m.Switch(self.sel_in):
 107             with m.Case(In2Sel.RB):
 108                 comb += self.reg_out.data.eq(self.dec.RB)
 109                 comb += self.reg_out.ok.eq(1)
 110             with m.Case(In2Sel.CONST_UI):
 111                 comb += self.imm_out.data.eq(self.dec.UI)
 112                 comb += self.imm_out.ok.eq(1)
 113             with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here?
 114                 comb += self.imm_out.data.eq(
 115                     self.exts(self.dec.SI, 16, 64))
 116                 comb += self.imm_out.ok.eq(1)
 117             with m.Case(In2Sel.CONST_UI_HI):
 118                 comb += self.imm_out.data.eq(self.dec.UI<<16)
 119                 comb += self.imm_out.ok.eq(1)
 120             with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here?
 121                 comb += self.imm_out.data.eq(self.dec.SI<<16)
 122                 comb += self.imm_out.data.eq(
 123                     self.exts(self.dec.SI << 16, 32, 64))
 124                 comb += self.imm_out.ok.eq(1)
 125             with m.Case(In2Sel.CONST_LI):
 126                 comb += self.imm_out.data.eq(self.dec.LI<<2)
 127                 comb += self.imm_out.ok.eq(1)
 128             with m.Case(In2Sel.CONST_BD):
 129                 comb += self.imm_out.data.eq(self.dec.BD<<2)
 130                 comb += self.imm_out.ok.eq(1)
 131             with m.Case(In2Sel.CONST_DS):
 132                 comb += self.imm_out.data.eq(self.dec.DS<<2)
 133                 comb += self.imm_out.ok.eq(1)
 134             with m.Case(In2Sel.CONST_M1):
 135                 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
 136                 comb += self.imm_out.ok.eq(1)
 137             with m.Case(In2Sel.CONST_SH):
 138                 comb += self.imm_out.data.eq(self.dec.sh)
 139                 comb += self.imm_out.ok.eq(1)
 140             with m.Case(In2Sel.CONST_SH32):
 141                 comb += self.imm_out.data.eq(self.dec.SH32)
 142                 comb += self.imm_out.ok.eq(1)
 143
 144         # decode SPR2 based on instruction type
 145         op = self.dec.op
 146         # BCREG implicitly uses CTR or LR for 2nd reg
 147         with m.If(op.internal_op == InternalOp.OP_BCREG):
 148             with m.If(self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO
 149                 comb += self.spr_out.data.eq(SPR.CTR)
 150             with m.Else():
 151                 comb += self.spr_out.data.eq(SPR.LR)
 152             comb += self.spr_out.ok.eq(1)
 153
 154         return m
 155
 156
 157 class DecodeC(Elaboratable):
 158     """DecodeC from instruction
 159
 160     decodes register RC
 161     """
 162
 163     def __init__(self, dec):
 164         self.dec = dec
 165         self.sel_in = Signal(In3Sel, reset_less=True)
 166         self.insn_in = Signal(32, reset_less=True)
 167         self.reg_out = Data(5, "reg_c")
 168
 169     def elaborate(self, platform):
 170         m = Module()
 171         comb = m.d.comb
 172
 173         # select Register C field
 174         with m.If(self.sel_in == In3Sel.RS):
 175             comb += self.reg_out.data.eq(self.dec.RS)
 176             comb += self.reg_out.ok.eq(1)
 177
 178         return m
 179
 180
 181 class DecodeOut(Elaboratable):
 182     """DecodeOut from instruction
 183
 184     decodes output register RA, RT or SPR
 185     """
 186
 187     def __init__(self, dec):
 188         self.dec = dec
 189         self.sel_in = Signal(OutSel, reset_less=True)
 190         self.insn_in = Signal(32, reset_less=True)
 191         self.reg_out = Data(5, "reg_o")
 192         self.spr_out = Data(10, "spr_o")
 193
 194     def elaborate(self, platform):
 195         m = Module()
 196         comb = m.d.comb
 197
 198         # select Register out field
 199         with m.Switch(self.sel_in):
 200             with m.Case(OutSel.RT):
 201                 comb += self.reg_out.data.eq(self.dec.RT)
 202                 comb += self.reg_out.ok.eq(1)
 203             with m.Case(OutSel.RA):
 204                 comb += self.reg_out.data.eq(self.dec.RA)
 205                 comb += self.reg_out.ok.eq(1)
 206             with m.Case(OutSel.SPR):
 207                 comb += self.spr_out.data.eq(self.dec.SPR) # from XFX
 208                 comb += self.spr_out.ok.eq(1)
 209
 210         return m
 211
 212
 213 class DecodeRC(Elaboratable):
 214     """DecodeRc from instruction
 215
 216     decodes Record bit Rc
 217     """
 218     def __init__(self, dec):
 219         self.dec = dec
 220         self.sel_in = Signal(RC, reset_less=True)
 221         self.insn_in = Signal(32, reset_less=True)
 222         self.rc_out = Data(1, "rc")
 223
 224     def elaborate(self, platform):
 225         m = Module()
 226         comb = m.d.comb
 227
 228         # select Record bit out field
 229         with m.Switch(self.sel_in):
 230             with m.Case(RC.RC):
 231                 comb += self.rc_out.data.eq(self.dec.Rc)
 232                 comb += self.rc_out.ok.eq(1)
 233             with m.Case(RC.ONE):
 234                 comb += self.rc_out.data.eq(1)
 235                 comb += self.rc_out.ok.eq(1)
 236             with m.Case(RC.NONE):
 237                 comb += self.rc_out.data.eq(0)
 238                 comb += self.rc_out.ok.eq(1)
 239
 240         return m
 241
 242
 243 class DecodeOE(Elaboratable):
 244     """DecodeOE from instruction
 245
 246     decodes OE field: uses RC decode detection which might not be good
 247
 248     -- For now, use "rc" in the decode table to decide whether oe exists.
 249     -- This is not entirely correct architecturally: For mulhd and
 250     -- mulhdu, the OE field is reserved. It remains to be seen what an
 251     -- actual POWER9 does if we set it on those instructions, for now we
 252     -- test that further down when assigning to the multiplier oe input.
 253     """
 254     def __init__(self, dec):
 255         self.dec = dec
 256         self.sel_in = Signal(RC, reset_less=True)
 257         self.insn_in = Signal(32, reset_less=True)
 258         self.oe_out = Data(1, "oe")
 259
 260     def elaborate(self, platform):
 261         m = Module()
 262         comb = m.d.comb
 263
 264         # select OE bit out field
 265         with m.Switch(self.sel_in):
 266             with m.Case(RC.RC):
 267                 comb += self.oe_out.data.eq(self.dec.OE)
 268                 comb += self.oe_out.ok.eq(1)
 269
 270         return m
 271
 272
 273 class XerBits:
 274     def __init__(self):
 275         self.ca = Signal(reset_less=True)
 276         self.ca32 = Signal(reset_less=True)
 277         self.ov = Signal(reset_less=True)
 278         self.ov32 = Signal(reset_less=True)
 279         self.so = Signal(reset_less=True)
 280
 281     def ports(self):
 282         return [self.ca, self.ca32, self.ov, self.ov32, self.so, ]
 283
 284
 285 class Decode2ToExecute1Type:
 286
 287     def __init__(self):
 288
 289         self.valid = Signal(reset_less=True)
 290         self.insn_type = Signal(InternalOp, reset_less=True)
 291         self.nia = Signal(64, reset_less=True)
 292         self.write_reg = Data(5, name="rego")
 293         self.read_reg1 = Data(5, name="reg1")
 294         self.read_reg2 = Data(5, name="reg2")
 295         self.read_reg3 = Data(5, name="reg3")
 296         self.imm_data = Data(64, name="imm")
 297         self.write_spr = Data(10, name="spro")
 298         self.read_spr1 = Data(10, name="spr1")
 299         self.read_spr2 = Data(10, name="spr2")
 300         #self.read_data1 = Signal(64, reset_less=True)
 301         #self.read_data2 = Signal(64, reset_less=True)
 302         #self.read_data3 = Signal(64, reset_less=True)
 303         #self.cr = Signal(32, reset_less=True) # NO: this is from the CR SPR
 304         #self.xerc = XerBits() # NO: this is from the XER SPR
 305         self.lk = Signal(reset_less=True)
 306         self.rc = Data(1, "rc")
 307         self.oe = Data(1, "oe")
 308         self.invert_a = Signal(reset_less=True)
 309         self.invert_out = Signal(reset_less=True)
 310         self.input_carry = Signal(CryIn, reset_less=True)
 311         self.output_carry = Signal(reset_less=True)
 312         self.input_cr = Signal(reset_less=True)
 313         self.output_cr = Signal(reset_less=True)
 314         self.is_32bit = Signal(reset_less=True)
 315         self.is_signed = Signal(reset_less=True)
 316         self.insn = Signal(32, reset_less=True)
 317         self.data_len = Signal(4, reset_less=True) # bytes
 318         self.byte_reverse  = Signal(reset_less=True)
 319         self.sign_extend  = Signal(reset_less=True)# do we need this?
 320         self.update  = Signal(reset_less=True) # is this an update instruction?
 321
 322     def ports(self):
 323         return [self.valid, self.insn_type, self.nia,
 324                 #self.read_data1, self.read_data2, self.read_data3,
 325                 #self.cr,
 326                 self.lk,
 327                 self.invert_a, self.invert_out,
 328                 self.input_carry, self.output_carry,
 329                 self.input_cr, self.output_cr,
 330                 self.is_32bit, self.is_signed,
 331                 self.insn,
 332                 self.data_len, self.byte_reverse , self.sign_extend ,
 333                 self.update] + \
 334                 self.oe.ports() + \
 335                 self.rc.ports() + \
 336                 self.write_spr.ports() + \
 337                 self.read_spr1.ports() + \
 338                 self.read_spr2.ports() + \
 339                 self.write_reg.ports() + \
 340                 self.read_reg1.ports() + \
 341                 self.read_reg2.ports() + \
 342                 self.read_reg3.ports() + \
 343                 self.imm_data.ports()
 344                 # + self.xerc.ports()
 345
 346 class PowerDecode2(Elaboratable):
 347
 348     def __init__(self, dec):
 349
 350         self.dec = dec
 351         self.e = Decode2ToExecute1Type()
 352
 353     def ports(self):
 354         return self.dec.ports() + self.e.ports()
 355
 356     def elaborate(self, platform):
 357         m = Module()
 358         comb = m.d.comb
 359
 360         # set up submodule decoders
 361         m.submodules.dec = self.dec
 362         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 363         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 364         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 365         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 366         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 367         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 368
 369         # copy instruction through...
 370         for i in [self.e.insn, dec_a.insn_in, dec_b.insn_in,
 371                   dec_c.insn_in, dec_o.insn_in, dec_rc.insn_in,
 372                   dec_oe.insn_in]:
 373             comb += i.eq(self.dec.opcode_in)
 374
 375         # ...and subdecoders' input fields
 376         comb += dec_a.sel_in.eq(self.dec.op.in1_sel)
 377         comb += dec_b.sel_in.eq(self.dec.op.in2_sel)
 378         comb += dec_c.sel_in.eq(self.dec.op.in3_sel)
 379         comb += dec_o.sel_in.eq(self.dec.op.out_sel)
 380         comb += dec_rc.sel_in.eq(self.dec.op.rc_sel)
 381         comb += dec_oe.sel_in.eq(self.dec.op.rc_sel) # XXX should be OE sel
 382
 383         # decode LD/ST length
 384         with m.Switch(self.dec.op.ldst_len):
 385             with m.Case(LdstLen.is1B):
 386                 comb += self.e.data_len.eq(1)
 387             with m.Case(LdstLen.is2B):
 388                 comb += self.e.data_len.eq(2)
 389             with m.Case(LdstLen.is4B):
 390                 comb += self.e.data_len.eq(4)
 391             with m.Case(LdstLen.is8B):
 392                 comb += self.e.data_len.eq(8)
 393
 394         #comb += self.e.nia.eq(self.dec.nia) # XXX TODO
 395         itype = Mux(self.dec.op.function_unit == Function.NONE,
 396                     InternalOp.OP_ILLEGAL,
 397                     self.dec.op.internal_op)
 398         comb += self.e.insn_type.eq(itype)
 399
 400         # registers a, b, c and out
 401         comb += self.e.read_reg1.eq(dec_a.reg_out)
 402         comb += self.e.read_reg2.eq(dec_b.reg_out)
 403         comb += self.e.read_reg3.eq(dec_c.reg_out)
 404         comb += self.e.write_reg.eq(dec_o.reg_out)
 405         comb += self.e.imm_data.eq(dec_b.imm_out)
 406
 407         # rc and oe out
 408         comb += self.e.rc.eq(dec_rc.rc_out)
 409         comb += self.e.oe.eq(dec_oe.oe_out)
 410
 411         # SPRs out
 412         comb += self.e.read_spr1.eq(dec_a.spr_out)
 413         comb += self.e.read_spr2.eq(dec_b.spr_out)
 414         comb += self.e.write_spr.eq(dec_o.spr_out)
 415
 416         # decoded/selected instruction flags
 417         comb += self.e.invert_a.eq(self.dec.op.inv_a)
 418         comb += self.e.invert_out.eq(self.dec.op.inv_out)
 419         comb += self.e.input_carry.eq(self.dec.op.cry_in)
 420         comb += self.e.output_carry.eq(self.dec.op.cry_out)
 421         comb += self.e.is_32bit.eq(self.dec.op.is_32b)
 422         comb += self.e.is_signed.eq(self.dec.op.sgn)
 423         with m.If(self.dec.op.lk):
 424             comb += self.e.lk.eq(self.dec.LK) # XXX TODO: accessor
 425
 426         comb += self.e.byte_reverse.eq(self.dec.op.br)
 427         comb += self.e.sign_extend.eq(self.dec.op.sgn_ext)
 428         comb += self.e.update.eq(self.dec.op.upd)
 429
 430         comb += self.e.input_cr.eq(self.dec.op.cr_in)
 431         comb += self.e.output_cr.eq(self.dec.op.cr_out)
 432
 433
 434         return m
 435
 436
 437 if __name__ == '__main__':
 438     pdecode = create_pdecode()
 439     dec2 = PowerDecode2(pdecode)
 440     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 441     with open("dec2.il", "w") as f:
 442         f.write(vl)
 443