1 # SPDX-License: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2020, Michael Nolan
5 """Enums used in OpenPOWER ISA decoding
7 Note: for SV, from v3.1B p12:
9 The designated SPR sandbox consists of non-privileged SPRs 704-719 and
10 privileged SPRs 720-735.
13 from enum
import Enum
, unique
16 from os
.path
import dirname
, join
17 from collections
import namedtuple
21 filedir
= os
.path
.dirname(os
.path
.abspath(__file__
))
22 basedir
= dirname(dirname(dirname(filedir
)))
23 tabledir
= join(basedir
, 'libreriscv')
24 tabledir
= join(tabledir
, 'openpower')
25 return join(tabledir
, 'isatables')
27 def find_wiki_file(name
):
28 filedir
= os
.path
.dirname(os
.path
.abspath(__file__
))
29 basedir
= dirname(dirname(dirname(filedir
)))
30 tabledir
= join(basedir
, 'libreriscv')
31 tabledir
= join(tabledir
, 'openpower')
32 tabledir
= join(tabledir
, 'isatables')
34 return join(find_wiki_dir(), name
)
38 file_path
= find_wiki_file(name
)
39 with
open(file_path
, 'r') as csvfile
:
40 reader
= csv
.DictReader(csvfile
)
44 # names of the fields in the tables that don't correspond to an enum
45 single_bit_flags
= ['inv A', 'inv out',
46 'cry out', 'BR', 'sgn ext', 'rsrv', '32b',
47 'sgn', 'lk', 'sgl pipe']
49 # default values for fields in the table
50 default_values
= {'unit': "NONE", 'internal op': "OP_ILLEGAL",
51 'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
55 'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
58 def get_signal_name(name
):
61 return name
.lower().replace(' ', '_')
63 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
64 # is to process and guard the operation. they are roughly divided by having
65 # the same register input/output signature (X-Form, etc.)
80 SV
= 1 << 12 # Simple-V https://libre-soc.org/openpower/sv
115 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
136 Idx_1_2
= 5 # due to weird BA/BB for crops
139 class SVP64PredInt(Enum
):
150 class SVP64PredCR(Enum
):
161 class SVP64RMMode(Enum
):
169 # supported instructions: make sure to keep up-to-date with CSV files
170 # just like everything else
172 "NONE", "add", "addc", "addco", "adde", "addeo", "addi", "addic", "addic.",
173 "addis", "addme", "addmeo", "addo", "addze", "addzeo", "and", "andc",
174 "andi.", "andis.", "attn", "b", "bc", "bcctr", "bclr", "bctar",
175 "bpermd", "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
176 "cntlzd", "cntlzw", "cnttzd", "cnttzw", "crand", "crandc", "creqv",
177 "crnand", "crnor", "cror", "crorc", "crxor", "darn", "dcbf", "dcbst",
178 "dcbt", "dcbtst", "dcbz", "divd", "divde", "divdeo", "divdeu",
179 "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
180 "divweu", "divweuo", "divwo", "divwu", "divwuo", "eqv", "extsb",
181 "extsh", "extsw", "extswsli", "hrfid", "icbi", "icbt", "isel", "isync",
182 "lbarx", "lbz", "lbzu", "lbzux", "lbzx", "ld", "ldarx", "ldbrx",
183 "ldu", "ldux", "ldx", "lha", "lharx", "lhau", "lhaux", "lhax",
184 "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", "lwa", "lwarx", "lwaux",
185 "lwax", "lwbrx", "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", "mcrf", "mcrxr",
186 "mcrxrx", "mfcr/mfocrf", "mfmsr", "mfspr", "modsd", "modsw", "modud",
187 "moduw", "mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr", "mulhd", "mulhdu",
188 "mulhw", "mulhwu", "mulld", "mulldo", "mulli", "mullw", "mullwo",
189 "nand", "neg", "nego", "nop", "nor", "or", "orc", "ori", "oris",
190 "popcntb", "popcntd", "popcntw", "prtyd", "prtyw", "rfid", "rldcl",
191 "rldcr", "rldic", "rldicl", "rldicr", "rldimi", "rlwimi", "rlwinm",
193 "setvl", # https://libre-soc.org/openpower/sv/setvl
194 "sim_cfg", "slbia", "sld", "slw", "srad", "sradi", "sraw",
195 "srawi", "srd", "srw", "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
196 "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx", "sth", "sthbrx", "sthcx",
197 "sthu", "sthux", "sthx", "stw", "stwbrx", "stwcx", "stwu", "stwux",
198 "stwx", "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
199 "subfme", "subfmeo", "subfo", "subfze", "subfzeo", "sync", "td",
200 "tdi", "tlbie", "tlbiel", "tw", "twi", "xor", "xori", "xoris",
203 # two-way lookup of instruction-to-index and vice-versa
206 for i
, insn
in enumerate(_insns
):
210 # Internal Operation numbering. Add new opcodes here (FPADD, FPMUL etc.)
213 OP_ILLEGAL
= 0 # important that this is zero (see power_decoder.py)
294 RS
= 4 # for some ALU/Logical operations
312 RS
= 13 # for shiftrot (M-Form)
319 RB
= 2 # for shiftrot (M-Form)
340 class LDSTMode(Enum
):
375 class CROutSel(Enum
):
384 # SPRs - Special-Purpose Registers. See V3.0B Figure 18 p971 and
385 # http://libre-riscv.org/openpower/isatables/sprs.csv
386 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
388 spr_csv
= get_csv("sprs.csv")
389 spr_info
= namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length idx')
393 info
= spr_info(SPR
=row
['SPR'], priv_mtspr
=row
['priv_mtspr'],
394 priv_mfspr
=row
['priv_mfspr'], length
=int(row
['len']),
396 spr_dict
[int(row
['Idx'])] = info
397 spr_byname
[row
['SPR']] = info
398 fields
= [(row
['SPR'], int(row
['Idx'])) for row
in spr_csv
]
399 SPR
= Enum('SPR', fields
)
410 if __name__
== '__main__':
411 # find out what the heck is in SPR enum :)
412 print("sprs", len(SPR
))
415 print(SPR
.__members
__['TAR'])
417 print(x
, x
.value
, str(x
), x
.name
)
419 print ("function", Function
.ALU
.name
)